CC2545RGZT [TI]
2.4GHz 射频超值系列 SoC，具有 32kB 闪存、31 GPIO、I2C、SPI 和 UART | RGZ | 48 | -40 to 85;
| 型号： | CC2545RGZT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.4GHz 射频超值系列 SoC，具有 32kB 闪存、31 GPIO、I2C、SPI 和 UART | RGZ | 48 | -40 to 85 射频 闪存 |
| 文件： | 总32页 (文件大小：2707K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CC2545
www.ti.com.cn
ZHCSAA7A –JUNE 2012–REVISED AUGUST 2012
针对 2.4GHz 射频 (RF) 应用的片上系统
1
特性
•
微控制器
–
具有代码预取功能的高性能和低功耗 8051
微控制器内核
•
射频 (RF) 部分
–
–
单片 2.4GHz RF 收发器和微控制器 (MCU)
–
–
–
–
32KB 闪存程序内存
支持 250kbps，500kbps，1Mbps 和 2Mbps
数据速率
1KB SRAM
支持硬件调试
–
出色的链路预算，无需外部前端即可实现长距离
通信
扩展基带自动化，包括自动确认和地址解码
–
–
高达 4dBm 的可编程输出功率
•
外设
出色的接收器灵敏度（2Mbps 时为 -
90Bm，256kbps 时为 -9dBm）
–
–
–
–
–
可访问所有内存区域和外设的两个通道 DMA
通用定时器（1 个 16 位，2 个 8 位）
无线电定时器，40 位
红外 (IR) 生成电路
–
适用于符合世界范围内的射频标准的系
统：ETSI EN 300 328 和 EN 300 440 2 类
（欧洲），FCC CFR47 15 部分（美国），和
ARIB STD-T66（日本）
几个振荡器：
–
–
–
–
32MHz 晶体振荡器 (XOSC)
16MHz RC 振荡器 (RCOSC)
32kHz XOSC
–
精确的接收到的信号强度指示器 (RSSI) 功能
•
•
布局
–
–
–
–
极少的外部组件
32MHz RCOSC
适用于单层印刷电路板 (PCB) 应用的引脚引线
–
–
–
具有捕捉功能的 32kHz 睡眠定时器
提供参考设计
高级加密标准 (AES) 安全协处理器
48 引脚 7mm x 7mm 四方扁平无引线
(QFN)（31 个通用 I/O 引脚）封装
通用异步收发器 (UART) / 串行外设接口 (SPI) /
串行接口
2
低功率
–
31 个通用 I/O 引脚（3 x 20mA 驱动强度，剩
余的引脚有 4mA 的驱动强度）
–
–
–
–
–
–
–
激活模式 RX 最佳性能：20.8mA
激活模式 TX (0dBm)：26.3mA
–
–
–
安全装置定时器
功率模式 1（5µs 唤醒）：235µA
功率模式 2（睡眠定时器打开）：0.9µA
功率模式 3（外部中断）：0.4µA
宽电源电压范围（2V 至 3.6V）
真随机数生成器
模数转换器 (ADC) 和模拟比较器
应用范围
在所有功率模式下的完全 RAM 和寄存器保持
•
•
•
私有的 2.4 GHz 系统
人机接口器件（键盘、鼠标）
消费类电子产品
空白
空白
空白
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
版权 © 2012, Texas Instruments Incorporated
English Data Sheet: SWRS106
CC2545
ZHCSAA7A –JUNE 2012–REVISED AUGUST 2012
www.ti.com.cn
这些装置包含有限的内置 ESD 保护。
存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损伤。
说明
CC2545 是一款经优化的针对数据速率高达 2Mbps 且使用低物料清单成本制造的片上系统 (SoC) 解决方案。
CC2545 将处于领先地位的 RF 收发器的出色性能与一个单周期 8051 兼容 CPU，32KB 系统内可编程闪存存储
器，高达 1KB RAM，31 个通用 I/O 引脚与很多其它功能强大的特性组合在一起。 CC2545 有高效的功率模
式（RAM 和寄存器保持电流低于 1μA），这使得它非常适合应用于要求超低功耗的低占空比系统。 运行模式间较
短的转换时间进一步确保了低能耗。
CC2545 与 CC2541/CC2543/CC2544 兼容。 它采用带有 SPI/UART/I2C 接口的 7mm x 7mm QFN48 封装。 供
货时，CC2545 带有由德州仪器 (TI) 提供的完整参考设计。
此器件针对无线消费类产品和人机接口器件 (HID) 应用。 CC2545 专为诸如无线键盘等的外设器件而设计。
方框图请见图 7。
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Supply voltage VDD
Voltage on any digital pin
Input RF level
TEST CONDITIONS
MIN
–0.3
–0.3
MAX
UNIT
V
All supply pins must have the same voltage
3.9
VDD+0.3 <= 3.9
V
10
dBm
°C
Storage temperature range
–40
125
All pads, according to human-body model, JEDEC
STD 22, method A114 (HBM)
2000
750
V
V
ESD(2)
According to charged-device model, JEDEC STD
22, method C101 (CDM)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) CAUTION: ESD sensitive device. Precaution should be used when handing the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
TEST CONDITIONS
MIN
–40
2.0
MAX
85
UNIT
°C
Operating ambient temperature range, TA
Operating supply voltage VDD
All supply pins must have same voltage
3.6
V
2
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CC2545
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ZHCSAA7A –JUNE 2012–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2545EM reference design with TA = 25°C and VDD = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
2 Mbps, GFSK, 320-kHz deviation
MIN
TYP
MAX
UNIT
RX mode, no peripherals active, low MCU activity
20.8
26.3
30.2
3
mA
mA
mA
mA
mA
TX mode, 0-dBm output power, no peripherals active, low MCU activity
TX mode, 5-dBm output power, no peripherals active, low MCU activity
Active mode, 16-MHz RCOSC, Low MCU activity
Active mode, 32-MHz clock frequency, low MCU activity
6
Power mode 0, CPU clock halted, all peripherals on, no clock division, 32-
MHz crystal selected
4.5
3
mA
mA
I core– Core current
consumption
Power mode 0, CPU clock halted, all peripherals on, clock division at max
(Limits max speed in peripherals except radio), 32-MHz crystal selected
Power mode 1. Digital regulator ON; 16-MHz RCOSC and 32-MHz crystal
oscillator OFF; 32.753-kHz RCOSC, POR, BOD, and sleep timer active;
RAM and register retention
235
µA
Power mode 2. Digital regulator OFF, 16 MHz RCOSC and 32 MHz
crystal oscillator OFF; 32.753 kHz RCOSC, POR and sleep timer active;
RAM and register retention
0.9
0.4
µA
µA
Power mode 3. Digital regulator OFF, no clocks, POR active; RAM and
register retention
Timer 1 (16-bit). Timer running, 32-MHz XOSC used
Radio timer(40 bit). Timer running, 32-MHz XOSC used
Timer 3 (8-bit). Timer running, 32-MHz XOSC used
Timer 4 (8-bit). Timer running, 32-MHz XOSC used
Sleep timer. Including 32.753-kHz RCOSC
90
90
60
70
0.6
µA
µA
µA
µA
µA
I peri– Peripheral
current consumption
(Adds to core
current Icore for each
peripheral unit
activated)
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2545EM reference design with TA = 25°C and VDD = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP AND TIMING
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC.
Power mode 1 → Active
5
µs
µs
µs
Digital regulator off, 16 MHz RCOSC and 32 MHz crystal
oscillator off. Start-up of regulator and 16 MHz RCOSC.
Power mode 2 or 3 → Active
130
500
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC, with
32-MHz XOSC OFF.
Active → TX or RX
With 32-MHz XOSC initially ON.
RCOSC, with 32MHz XOSC OFF.
180
130
µs
µs
RX/TX turnaround
RADIO PART
RF frequency range
Programmable in 1-MHz steps
2379
2496
MHz
2 Mbps, GFSK 320-kHz deviation
2-Mbps, GFSK 500 kHz deviation
1-Mbps, GFSK 250 kHz deviation
1-Mbps, GFSK 160 kHz deviation
500 kbps, MSK
Data rates and modulation
formats
250 kbps, MSK
250 kbps, GSK 160 kHz deviation
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RF RECEIVE SECTION
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3 V, and fC = 2440 MHz, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
2 Mbps, GFSK, 320-kHz DEVIATION, 0.1% BER
Receiver sensitivity
–86
–8
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
±2-MHz offset, wanted signal at –67 dBm
–13
–1
In-band blocking rejection
±4-MHz offset, wanted signal at –67 dBm
>±6-MHz offset, wanted signal at –67 dBm
34
dB
38
1-MHz resolution. Wanted signal at –67 dBm, f < 2 GHz
Two exception frequencies with poorer performance
–32
–38
–12
1-MHz resolution. Wanted signal at –67 dBm, 2 GHz > f < 3 GHz
Two exception frequencies with poorer performance
Out-of-band blocking rejection
dBm
1-MHz resolution. Wanted signal at –67 dBm, f > 3GHz
Two exception frequencies with poorer performance
Wanted signal at –64 dBm, 1st interferer is CW, 2nd interferer is GFSK-
modulated signal. Offsets of interferers are:
6 and 12 MHz
Intermodulation
–43
dBm
8 and 16 MHz
10 and 20 MHz
Including both initial tolerance and drift. Sensitivity better than –70 dBm.
250 byte payload.
Frequency error tolerance(1)
Symbol rate error tolerance(2)
–300
–120
300 kHz
120 ppm
Sensitivity better than -70 dBm. 250 byte payload.
2 Mbps, GFSK, 500 kHz DEVIATION, 0.1% BER
Receiver sensitivity
–90
–3
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
–10
–3
±2 MHz offset, wanted signal at –67 dBm
±4 MHz offset, wanted signal at –67 dBm
>±6 MHz offset, wanted signal at –67 dBm
dB
In-band blocking rejection
36
dB
44
dB
Including both initial tolerance and drift. Sensitivity better than –70 dBm.
250 byte payload.
Frequency error tolerance(1)
Symbol rate error tolerance(2)
–300
–120
300 kHz
120 ppm
Sensitivity better than -70 dBm. 250 byte payload.
1 Mbps, GFSK, 250 kHz DEVIATION, 0.1% BER
Receiver sensitivity
–94
6
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
–7
0
±1 MHz offset, wanted signal –67 dBm
±2 MHz offset, wanted signal –67 dBm
±3 MHz offset, wanted signal –67 dBm
>±5 MHz offset, wanted signal –67 dBm
30
34
38
In-band blocking rejection
dB
Including both initial tolerance and drift. Sensitivity better than –70 dBm.
250 byte payload.
Frequency error tolerance
Symbol rate error tolerance
–250
-80
250 kHz
80 ppm
Sensitivity better than –70 dBm. 250 byte payload.
(1) Difference between center frequency of the received RF signal and local oscillator frequency
(2) Difference between incoming symbol rate and the internally generated symbol rate
4
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ZHCSAA7A –JUNE 2012–REVISED AUGUST 2012
RF RECEIVE SECTION (接下页)
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3 V, and fC = 2440 MHz, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1 Mbps, GFSK, 160 kHz DEVIATION, 0.1% BER
Receiver sensitivity
–91
6
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
±1 MHz offset, wanted signal at –67 dBm
–8
2
±2 MHz offset, wanted signal at –67 dBm
±3 MHz offset, wanted signal at –67 dBm
>±5 MHz offset, wanted signal at –67 dBm
Including both initial tolerance and drift, Sensitivity better than –67 dBm
Maximum packet length
28
33
36
In band blocking rejection
dB
Frequency error tolerance
Symbol rate error tolerance
500 kbps, MSK, 0.1% BER
Receiver sensitivity
–250
–80
250 kHz
80 ppm
–98
6
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
–5
21
32
33
±1 MHz offset, wanted signal at –67 dBm
±2 MHz offset, wanted signal at –67 dBm
>±2 MHz offset, wanted signal at –67 dBm
Including both initial tolerance and drift, Sensitivity better than –67dBm
Maximum packet length
In band blocking rejection
dB
Frequency error tolerance
Symbol rate error tolerance
–150
–60
150 kHz
60 ppm
250 kbps, GFSK, 160 kHz DEVIATION , 0.1% BER
Receiver sensitivity
Saturation
–98
6
dBm
dBm
dB
Co-channel rejection
Wanted signal at –67 dBm
–2
22
32
32
±1 MHz offset, wanted signal at –67 dBm
±2 MHz offset, wanted signal at –67 dBm
>±2 MHz offset, wanted signal at –67 dBm
Including both initial tolerance and drift, Sensitivity better than –67 dBm
Maximum packet length
In-band blocking rejection
dB
Frequency error tolerance
Symbol rate error tolerance
250 kbps, MSK, 0.1% BER
Receiver sensitivity
–150
–60
150 kHz
60 ppm
–98
6
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
–5
21
32
33
±1 MHz offset, wanted signal at –67 dBm
±2 MHz offset, wanted signal at –67 dBm
>2 MHz offset, wanted signal at –67 dBm
Including both initial tolerance and drift, Sensitivity better than –67 dBm
Maximum packet length
In-band blocking rejection
dB
Frequency error tolerance
Symbol rate error tolerance
ALL RATES/FORMATS
–150
–60
150 kHz
60 ppm
Spurious emission in RX.
Conducted measurement
f < 1 GHz
f > 1 GHz
–67
–60
dBm
dBm
Spurious emission in RX.
Conducted measurement
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RF TRANSMIT SECTION
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, and fC = 2440 MHz, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delivered to a single-ended 50-Ω load through a balun using
maximum recommended output power setting.
Output power, maximum setting
5
dBm
Delivered to a single-ended 50-Ω load through a balun using
minimum recommended output power setting.
Output power, minimum setting
–20
dBm
Programmable output power range Delivered to a single-ended 50-Ω load through a balun.
25
dB
f < 1 GHz
–46
–44
dBm
dBm
Spurious emission in TX.
Conducted measurement
f > 1 GHz
Suitable for Systems Targeting Compliance With Worldwide Radio Frequency Regulations: ETSI EN
300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Use a simple LC filter (1.6nH and 1.8pF in parallel to ground) to pass ETSI conducted requirements below 1GHz
in restricted bands. For radiated measurements low antenna gain for these frequencies (depending on antenna
design) can achieve the same attenuation of these low frequency components (see EM reference design).
32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
Crystal frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32
MHz
250 kbps and 500 kbps data rates
1 Mbps data rate
2 Mbps data rate
–30
–40
–60
30
40
60
Crystal frequency accuracy
requirement
ppm
Equivalent series resistance
Crystal shunt capacitance
Crystal load capacitance
Start-up time
6
1
60
7
Ω
pF
pF
ms
10
16
0.25
The crystal oscillator must be in power down for a guard time
before it is used again. This requirement is valid for all modes of
operation. The need for power-down guard time can vary with
crystal type and load.
Power-down guard time
3
ms
32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
Crystal frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32.768
kHz
Crystal frequency accuracy
requirement(1)
-100
+100
ppm
Equivalent series resistance
Crystal shunt capacitance
Crystal load capacitance
Start-up time
40
0.9
12
130
2
Ω
pF
pF
s
16
0.4
(1) Crystal frequency accuracy requirement is highly dependent on application. Higher accuracy enables more accurate duty-cycling which
in turn will reduce current consumption. The chip can handle much less accurate crystals.
6
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ZHCSAA7A –JUNE 2012–REVISED AUGUST 2012
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
Calibrated frequency
TEST CONDITIONS
MIN
TYP
32.753
±0.2%
0.4
MAX
UNIT
kHz
Frequency accuracy after calibration
Temperature coefficient
Supply-voltage coefficient
Calibration time
%/ºC
%/V
ms
3
2
16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
Calibrated frequency
TEST CONDITIONS
MIN
TYP
16
MAX
UNIT
MHz
Uncalibrated frequency accuracy
Frequency accuracy after calibration
Start-up time
±18%
±0.6%
10
µs
µs
Initial calibration time
50
RSSI CHARACTERISTICS
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted.
2Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Reduced gain by AC algorithm
High gain by AGC algorithm
Reduced gain by AGC algorithm
High gain by AGC algorithm
64
64
79
99
±3
1
RSSI range(1)
RSSI offset(1)
dB
dBm
Absolute uncalibrated accuracy(1)
Step size (LSB value)
All Other Rates/Formats
RSSI range(1)
dB
dB
64
99
±3
1
dB
dBm
dB
RSSI offset(1)
Absolute uncalibrated accuracy
Step size (LSB value)
dB
(1) Assuming CC2545 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
At ±1 MHz from carrier
MIN
TYP
–112
–119
–122
MAX
UNIT
Phase noise, unmodulated carrier At ±3 MHz from carrier
At ±5 MHz from carrier
dBc/Hz
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ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
1480
4.5
1
MAX
UNIT
12-bit
/ 0.1ºC
/ 0.1V
ºC
Output
Temperature coefficient
Voltage coefficient
Measured using integrated ADC, internal band-gap
voltage reference, and maximum resolution
Initial accuracy without calibration
Accuracy using 1-point calibration
Current consumption when enabled
±10
±5
ºC
0.5
mA
COMPARATOR CHARACTERISTICS
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2545 reference designs, post-calibration.
PARAMETER
Common-mode maximum voltage
Common-mode minimum voltage
Input offset voltage
TEST CONDITIONS
MIN
TYP MAX UNIT
VDD
–0.3
1
V
mV
µV/°C
mV/V
nA
Offset vs temperature
Offset vs operating voltage
Supply current
16
4
230
0.15
Hysteresis
mV
8
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ADC CHARACTERISTICS
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
VDD is voltage on AVDD5 pin
VDD is voltage on AVDD5 pin
MIN
0
TYP
MAX
VDD
VDD
VDD
UNIT
V
Input voltage
External reference voltage
0
V
External reference voltage differential VDD is voltage on AVDD5 pin
0
V
Input resistance, signal
Full-scale signal(1)
Simulated using 4-MHz clock speed
Peak-to-peak, defines 0 dBFS
197
2.97
5.7
kΩ
V
Single-ended input, 7-bit setting
Single-ended input, 9-bit setting
7.5
Single-ended input, 10-bit setting
Single-ended input, 12-bit setting
Differential input, 7-bit setting
9.3
10.3
6.5
ENOB(1)
Effective number of bits
bits
Differential input, 9-bit setting
8.3
Differential input, 10-bit setting
10
Differential input, 12-bit setting
11.5
9.7
10-bit setting, clocked by RCOSC
12-bit setting, clocked by RCOSC
7-bit setting, both single and differential
Single ended input, 12-bit setting, –6 dBFS(1)
Differential input, 12-bit setting, –6 dBFS(1)
Single-ended input, 12-bit setting(1)
Differential input, 12-bit setting(1)
Single-ended input, 12-bit setting, –6 dBFS(1)
Differential input, 12-bit setting, –6 dBFS(1)
10.9
0–20
–75.2
–86.6
70.2
79.3
78.8
88.9
Useful power bandwidth
Total harmonic distortion
kHz
dB
THD
Signal to nonharmonic ratio
dB
dB
Differential input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
CMRR
Common-mode rejection ratio
Crosstalk
>84
>84
Single ended input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
dB
Offset
Midscale
–3
0.68%
0.05
0.9
mV
Gain error
12-bit setting, mean(1)
12-bit setting, maximum(1)
12-bit setting, mean(1)
DNL
INL
Differential nonlinearity
Integral nonlinearity
LSB
LSB
4.6
12-bit setting, maximum(1)
12-bit setting, mean, clocked by RCOSC
12-bit setting, max, clocked by RCOSC
Single ended input, 7-bit setting(1)
Single ended input, 9-bit setting(1)
Single ended input, 10-bit setting(1)
Single ended input, 12-bit setting(1)
Differential input, 7-bit setting(1)
Differential input, 9-bit setting(1)
Differential input, 10-bit setting(1)
Differential input, 12-bit setting(1)
7-bit setting
13.3
10
29
35.4
46.8
57.5
66.6
40.7
51.6
61.8
70.8
20
SINAD
(–THD+N)
Signal-to-noise-and-distortion
dB
9-bit setting
36
Conversion time
μs
10-bit setting
68
12-bit setting
132
(1) Measured with 300-Hz sine-wave input and VDD as reference.
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ADC CHARACTERISTICS (接下页)
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
4
MAX
UNIT
mA
Power consumption
Internal reference VDD coefficient
mV/V
Internal reference temperature
coefficient
0.4
mV/10°C
V
Internal reference voltage
1.15
DC CHARACTERISTICS
Measured on Texas Instruments CC2545EM reference design with TA = 25°C, VDD = 3.0 V, unless otherwise noted.(1)
PARAMETER
Logic-0 input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
0.5
Logic-1 input voltage
2.5
–50
–50
V
Logic-0 input current
50
50
nA
nA
kΩ
V
Logic-1 input current
I/O pin pullup and pulldown resistors
Logic-0 output voltage 4-mA pins
Logic-1 output voltage 4-mA pins
Logic-0 output voltage 20-mA pins
Logic-1 output voltage, 20-mA pins
20
Output load 4 mA
Output load 4 mA
0.5
0.5
2.4
2.4
V
Output load 20 mA
Output load 20 mA
V
V
(1) Note that only two of the three 20-mA pins can drive in the same direction at the same time, and toggle at the same time.
CONTROL INPUT AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V.
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
System clock, fSYSCLK
tSYSCLK = 1/ fSYSCLK
16
32
MHz
See item 1, 图 1. This is the shortest pulse that is recognized as a
complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
RESET_N low duration
Interrupt pulse duration
1
µs
ns
See item 2, 图 1.This is the shortest pulse that is recognized as an
interrupt request.
20
RESET_N
1
2
Px.n
T0299-01
图 1. Control Input AC Characteristics
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SPI AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
250
250
TYP MAX UNIT
Master, RX and TX
Slave, RX and TX
Master
t1
SCK period
ns
SCK duty cycle
50%
Master
63
63
63
63
SSN low to SCK, 图 2
and 图 3
t2
t3
ns
Slave
Master
SCK to SSN high
ns
Slave
t4
t5
t6
t7
MOSI early out
MOSI late out
MISO setup
Master, load = 10 pF
Master, load = 10 pF
Master
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
90
10
MISO hold
Master
SCK duty cycle
MOSI setup
Slave
50%
t10
t11
t8
Slave
35
10
MOSI hold
Slave
MISO early out
MISO late out
Slave, load = 10 pF
Slave, load = 10 pF
Master, TX only
Master, RX and TX
Slave, RX only
Slave, RX and TX
0
95
8
t9
4
Operating frequency
MHz
8
4
SCK
t2
t3
SSN
t4
t5
MOSI
D0
X
D1
t6
t7
MISO
X
D0
X
T0478-01
图 2. SPI Master AC Characteristics
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SCK
t2
t3
SSN
t8
t9
MISO
D0
X
D1
t10
t11
MOSI
X
D0
X
T0479-01
图 3. SPI Slave AC Characteristics
DEBUG INTERFACE AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
12
UNIT
MHz
ns
fclk_dbg
Debug clock frequency (see 图 4)
Allowed high pulse on clock (see 图 4)
Allowed low pulse on clock (see 图 4)
t1
t2
35
35
ns
EXT_RESET_N low to first falling edge on debug
clock (see 图 5)
t3
t4
t5
167
83
ns
ns
ns
Falling edge on clock to EXT_RESET_N high (see
图 5)
EXT_RESET_N high to first debug command (see
图 5)
83
t6
t7
t8
Debug data setup (see 图 6)
Debug data hold (see 图 6)
Clock-to-data delay (see 图 6)
2
4
ns
ns
ns
Load = 10 pF
30
Time
DEBUG_CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
图 4. Debug Clock – Basic Timing
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Time
DEBUG_CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
图 5. Debug Enable Timing
Time
DEBUG_CLK
P2_2
DEBUG_DATA
(to CC2545)
P2_1
DEBUG_DATA
(from CC2545)
P2_1
t6
t7
t8
T0438-03
图 6. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system
clock rate (16 MHz or 32 MHz).
Input capture pulse duration
1.5
tSYSCLK
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DEVICE INFORMATION
PIN DESCRIPTIONS
CC2545
RTC Package
(Top View)
40 39 38 37
48 47 46 45 44 43 42 41
1
2
P3_3
P3_2
36
35
34
33
32
31
P1_6/ XOSC32K_Q2
RBIAS
VDD
3
P3_1
P3_0
4
VDD
5
VSS
P2_3
P2_2
P2_1
P2_0
P0_7
6
VSS
RF_N
7
30
29
28
RF_P
VSS
Ground Pad
8
9
VDD
10
11
12
27
26
25
XOSC_Q2
XOSC_Q1
VDD
P0_6
P0_5
P0_4
17 18 19 20 21 22 23 24
13 14 15 16
P0145-01
(1) NOTE: The exposed ground pad must be connected to a solid ground plane; this is the main ground connection for
the chip.
表 1. Pin Description Table
NAME
P3_3
P3_2
P3_1
P3_0
P2_3
P2_2
P2_1
P2_0
P0_7
P0_6
P0_5
P0_4
P0_3
PIN
1
PIN TYPE
DESCRIPTION
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Port 3.3
Port 3.2
Port 3.1
Port 3.0
Port 2.3
Port 2.2
Port 2.1
Port 2.0
Port 0.7
Port 0.6
Port 0.5
Port 0.4
Port 0.3
2
3
4
5
6
7
8
9
10
11
12
13
14
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表 1. Pin Description Table (接下页)
NAME
P0_2
PIN
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PIN TYPE
DESCRIPTION
Digital I/O
Port 0.2
Port 0.1
Port 0.0
Port 2.7
Port 2.6
Port 2.5
Port 2.4
P0_1
Digital I/O
P0_0
Digital I/O
P2_7
Digital I/O
P2_6
Digital I/O
P2_5
Digital I/O
P2_4
Digital I/O
VDD
Power (analog)
Digital input
Digital I/O / Debug
Digital I/O / Debug
Power (analog)
Analog I/O
2-V-3.6V analog power-supply connection
Reset, active-low
RESET_N
P1_4/DC
P1_3/DD
VDD
Port 1.4/Debug
Port 1.3/Debug
2-V-3.6V analog power-supply connection
32-MHz crystal oscillator pin 1or external-clock input
32-MHz crystal oscillator pin 2
2-V-3.6V analog power-supply connection
Connect to ground
XOSC_Q1
XOSC_Q2
VDD
Analog I/O
Power (analog)
Unused pin
RF I/O
VSS
RF_P
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RF_N
31
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
VSS
VDD
32
33
34
35
36
Unused pin
Connect to ground
Power (analog)
Power (analog)
Analog I/O
2-V-3.6V analog power-supply connection
2-V-3.6V analog power-supply connection
External precision bias resistor for reference current
Port 1.6/32.768-kHz XOSC
VDD
RBIAS
P1_6/
XOSC32K_
Q2
Digital I/O / Analog I/O
P1_5/
XOSC32k_
Q1
37
Digital I/O / Analog I/O
Port 1.5/32.768-kHz XOSC
P1_2
P1_1
P1_0
VDD
38
39
40
41
42
Digital I/O
Port 1.2, 20mA
Digital I/O
Port 1.1, 20mA
Digital I/O
Port 1.0, 20mA
Power (analog)
Power (digital)
2-V-3.6V analog power-supply connection
DCPL1
1.8-V digital power-supply decoupling. Do not use for supplying external
circuits.
VDD
VSS
43
44
45
46
47
48
Power (analog)
Unused pin
Digital I/O
2-V-3.6V analog power-supply connection
Connect to ground
Port 3.7
P3_7
P3_6
P3_5
P3_4
VSS
Digital I/O
Port 3.6
Digital I/O
Port 3.5
Digital I/O
Port 3.4
Ground Pad Ground
Must be connected to solid ground as this is the main ground connection
for the chip. See Pinout Diagram.
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BLOCK DIAGRAM
A block diagram of the CC2545 is shown in 图 7. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given. See CC2543/44/45 User's
Guide (SWRU283) for more details.
POWER ON RESET
BROWN OUT
RESET_N
RESET
WATCHDOG TIMER
VDD(2.0 -3.6 V)
DCOUPL
CHIP VOLTAGE
REGULATOR
ON -
XOSC_Q2
XOSC_Q1
32 MHz
CRYSTAL OSC
CLOCK MUX &
CALIBRATION
32.768 kHz
CRYSTAL OSC
SLEEP TIMER
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P3_0
DEBUG
INTERFACE
HIGH SPEED
RC-OSC
32 kHz
RC- OSC
POWER MG.TCONTROLLER
PDATA
RAM
SRAM
XRAM
IRAM
SFR
8051 CPU
CORE
MEMORY
ARBITRATOR
FLASH
FLASH
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
UNIFIED
DMA
FLASH CTRL
IRQ
CTRL
ANALOG COMPARATOR
FIFOCTRL
SRAM
ROM
PSEUDO
RANDOM
NUMBER
RADIO
REGISTERS
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
GENERATOR
Link Layer Engine
AES
ENCRYPTION
&
DS ADC
AUDIO / DC
DECRYPTION
DEMODULATOR
MODULATOR
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
USART 0
RECEIVE
TRANSMIT
I2C
TIMER1 (16-bit)
TIMER 2
(RADIO TIMER)
SDA
SCL
_
RF P RF N
_
TIMER 3 (8-bit)
TIMER 4 (8-bit)
DIGITAL
ANALOG
MIXED
图 7. CC2545 Block Diagram
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BLOCK DESCRIPTIONS
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 15-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in 图 7 as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The 1-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.
The 18-KB/32-KB flash block provides in-circuit programmable non-volatile program memory for the device,
and maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile two-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USART, timers, etc.)
can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or
XREG address and flash/SRAM.
The interrupt controller services a total of 17 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is
in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode (when
in sleep mode, the device is in low-power mode PM1, PM2 or PM3).
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which
oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051
core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is
possible to perform in-circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between several different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that can use either an external 32.768-kHz XOSC or an internal
32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes. Typical applications of this
timer are as a real-time counter or as a wake-up timer to get out of power modes 1 or 2.
A built-in watchdog timer allows the CC2545 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
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Timer 2 is a 40-bit timer used by the Radio. It has a 16-bit counter with a configurable timer period and a 24-bit
overflow counter that can be used to keep track of the number of periods that have transpired. A 40-bit capture
register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the
exact time at which a packet ends. There are two 16-bit timer-compare registers and two 24-bit overflow-
compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 is configurable as either an SPI master/slave or a UART. It provides double buffering on both RX and
TX and hardware flow control and is thus well suited to high-throughput full-duplex applications. The USART has
its own high-precision baud-rate generator, thus leaving the ordinary timers free for other uses. When configured
as SPI slaves, the USART samples the input signal using SCK directly instead of using some oversampling
scheme, and are thus well-suited for high data rates.
I2C module provides a digital peripheral connection with two pins and supports both master and slave operation.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ultralow power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is mapped into the digital I/O port and can be treated by the MCU as a regular digital input.
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TYPICAL CHARACTERISTICS
All curves are for measurements performed at 2Mbps, GFSK, 320-kHz deviation.
RX CURRENT
vs
TX CURRENT
vs
TEMPERATURE
TEMPERATURE
32
31
30
29
28
27
24
3-V Supply
TXPOWER Setting = 0xE5
3-V Supply
Standard Gain Setting
−70 dBm Input
2 Mbps, GFSK, 320 kHz deviation
23
22
21
20
19
−40
−20
0
20
40
60
80
−40
−20
0
20
Temperature (°C)
40
60
80
Temperature (°C)
G002
G001
图 8.
图 9.
RX SENSITIVITY
vs
TX POWER
vs
TEMPERATURE
TEMPERATURE
10
8
−80
−82
−84
−86
−88
−90
3-V Supply
3-V Supply
Standard Gain Setting
TXPOWER Setting = 0xE5
2 Mbps, GFSK, 320 kHz deviation
6
4
2
0
−40
−20
0
20
40
60
80
−40
−20
0
20
Temperature (°C)
40
60
80
Temperature (°C)
G004
G003
图 10.
图 11.
RX CURRENT
vs
TX CURRENT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
32
31
30
29
28
27
24
23
22
21
20
19
TA = 25°C
TA = 25°C
Standard Gain Setting
TXPOWER Setting = 0xE5
−70 dBm Input
2 Mbps, GFSK, 320 kHz deviation
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
Supply Voltage (V)
G006
G005
图 12.
图 13.
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TYPICAL CHARACTERISTICS (接下页)
All curves are for measurements performed at 2Mbps, GFSK, 320-kHz deviation.
RX SENSITIVITY
vs
TX POWER
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
10
8
−80
−82
−84
−86
−88
−90
TA = 25°C
TXPOWER Setting = 0xE5
TA = 25°C
Standard Gain Setting
2 Mbps, GFSK, 320 kHz deviation
6
4
2
0
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
Supply Voltage (V)
G008
G007
图 14.
图 15.
RX SENSITIVITY
vs
TX POWER
vs
FREQUENCY
FREQUENCY
10
8
−80
−82
−84
−86
−88
−90
3-V Supply
TA = 25°C
3-V Supply
TA = 25°C
Standard Gain Setting
TXPOWER Setting = 0xE5
2 Mbps, GFSK, 320 kHz deviation
6
4
2
0
2400
2420
2440
Frequency (MHz)
2460
2480
2400
2420
2440
Frequency (MHz)
2460
2480
G011
G009
图 16.
图 17.
RX INTERFERER REJECTION (SELECTIVITY)
vs
INTERFERER FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
3-V Supply
TA = 25°C
Standard Gain Setting
Wanted Signal at
2440 MHz with
−67 dBm Level
2400
2420
2440
2460
2480
Frequency (MHz)
G010
图 18.
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TYPICAL CHARACTERISTICS (接下页)
表 2. Recommended Output Power Settings(1)
TXPOWER Register Setting
Typical Output Power (dBm)
0xE5
0xD5
0xC5
0xB5
0xA5
0x95
0x85
0x75
0x65
0x55
0x45
0x35
0x25
0x15
0x05
5
4
3
2
0
–2
–3
–4
–6
–8
–11
–13
–15
–17
–20
(1) Measured on Texas Instruments CC2545 EM reference design with TA = 25°C, VDD = 3 V, and fc = 2440 MHz. See SWRU283 for
recommended register settings.
版权 © 2012, Texas Instruments Incorporated
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21
CC2545
ZHCSAA7A –JUNE 2012–REVISED AUGUST 2012
www.ti.com.cn
APPLICATION INFORMATION
APPLICATION INFORMATION
Few external components are required for the operation of the CC2545. A typical application circuit is shown in
图 19. For suggestions of component values other than those listed in 表 3, see reference design CC2545EM.
The performance stated in this data sheet is only valid for the CC2545EM reference design. To obtain similar
performance, the reference design should be copied as closely as possible.
2.0V-3.6V
Power Supply
Optional32-kHz Crystal
C421
XOSC32K_Q1
XOSC32K_Q1
1 P3_3
P1_6 36
RBIAS 35
VDD 34
R351
2 P3_2
3 P3_1
4 P3_0
5 P2_3
6 P2_2
7 P2_1
8 P2_0
9 P0_7
10 P0_6
11 P0_5
12 P0_4
Antenna
(50 Ohm)
VDD 33
VSS 32
RF_N 31
RF_P 30
VSS 29
CC2545
DIE ATTACH PAD:
VDD 28
XOSC_Q2 27
XOSC_Q1 26
VDD 25
C271
C261
Power supply decoupling capacitors are not shown
Digital I/O not connected
图 19. CC2545 Application Circuit
表 3. Overview of External Components (Excluding Balun, Crystal and Supply Decoupling Capacitors)
Component
C421
Description
Value
1 µF
Decoupling capacitor for the internal 1.8V digital voltage
regulator
R351
Precision resistor ±1%, used for internal biasing
56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2545EM,
for recommended balun.
22
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版权 © 2012, Texas Instruments Incorporated
CC2545
www.ti.com.cn
ZHCSAA7A –JUNE 2012–REVISED AUGUST 2012
Crystal
An external 32-MHz crystal with two loading capacitors is used for the 32-MHz crystal oscillator. The load
capacitance seen by the 32-MHz crystal is given by:
1
CL =
+ Cparasitic
1
1
+
C261 C271
(1)
A series resistor may be used to comply with ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C421) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
spacer
REVISION HISTORY
Changes from Original (June 2012) to Revision A
Page
•
•
•
Deleted 产品预览标题 ........................................................................................................................................................... 1
Changed the Temperature coefficient Unit value From: mV/°C To: / 0.1°C ......................................................................... 8
Changed 图 19 .................................................................................................................................................................... 22
版权 © 2012, Texas Instruments Incorporated
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23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CC2545RGZR
CC2545RGZT
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
CC2545
CC2545
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
CC2545RGZR
CC2545RGZT
RGZ
RGZ
VQFN
VQFN
48
48
2500
250
26 x 10
26 x 10
150
150
315 135.9 7620 11.8
315 135.9 7620 11.8
10
10
10.35
10.35
Pack Materials-Page 1
GENERIC PACKAGE VIEW
RTC 48
7 x 7, 0.5 mm pitch
VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224601/A
www.ti.com
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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