CC2541F256RHAR_技术文档

CC2541

www.ti.com

SWRS110D –JANUARY 2012–REVISED JUNE 2013

2.4-GHz Bluetooth™ low energy and Proprietary System-on-Chip

Check for Samples: CC2541

1

FEATURES

23

•

RF

–

High-Performance and Low-Power 8051

Microcontroller Core With Code Prefetch

–

2.4-GHz Bluetooth low energy Compliant

and Proprietary RF System-on-Chip

In-System-Programmable Flash, 128- or

256-KB

–

Supports 250-kbps, 500-kbps, 1-Mbps, 2-

Mbps Data Rates

8-KB RAM With Retention in All Power

Modes

Excellent Link Budget, Enabling Long-

Range Applications Without External Front

End

–

Hardware Debug Support

Extensive Baseband Automation, Including

Auto-Acknowledgment and Address

Decoding

–

Programmable Output Power up to 0 dBm

Excellent Receiver Sensitivity (–94 dBm at

1 Mbps), Selectivity, and Blocking

Performance

–

Retention of All Relevant Registers in All

Power Modes

–

Suitable for Systems Targeting Compliance

With Worldwide Radio Frequency

Regulations: ETSI EN 300 328 and EN 300

440 Class 2 (Europe), FCC CFR47 Part 15

(US), and ARIB STD-T66 (Japan)

•

Peripherals

–

Powerful Five-Channel DMA

General-Purpose Timers (One 16-Bit, Two

8-Bit)

–

IR Generation Circuitry

•

Layout

32-kHz Sleep Timer With Capture

Accurate Digital RSSI Support

Battery Monitor and Temperature Sensor

–

Few External Components

Reference Design Provided

6-mm × 6-mm QFN-40 Package

12-Bit ADC With Eight Channels and

Configurable Resolution

Pin-Compatible With CC2540 (When Not

Using USB or I²C)

–

AES Security Coprocessor

•

Low Power

Two Powerful USARTs With Support for

Several Serial Protocols

–

Active-Mode RX Down to: 17.9 mA

Active-Mode TX (0 dBm): 18.2 mA

–

23 General-Purpose I/O Pins

(21 × 4 mA, 2 × 20 mA)

Power Mode 1 (4-µs Wake-Up): 270 µA

Power Mode 2 (Sleep Timer On): 1 µA

Power Mode 3 (External Interrupts): 0.5 µA

Wide Supply-Voltage Range (2 V–3.6 V)

–

I²C interface

2 I/O Pins Have LED Driving Capabilities

Watchdog Timer

•

TPS62730 Compatible Low Power in Active

Mode

Integrated High-Performance Comparator

•

Development Tools

–

RX Down to: 14.7 mA (3-V supply)

–

CC2541 Evaluation Module Kit

(CC2541EMK)

TX (0 dBm): 14.3 mA (3-V supply)

White space

–

CC2541 Mini Development Kit (CC2541DK-

MINI)

–

SmartRF™ Software

IAR Embedded Workbench™ Available

White space

•

Microcontroller

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

Bluetooth is a trademark of Bluetooth SIG, Inc..

ZigBee is a registered trademark of ZigBee Alliance.

3

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CC2541

SWRS110D –JANUARY 2012–REVISED JUNE 2013

www.ti.com

SOFTWARE FEATURES

CC2541 WITH TPS62730

•

Bluetooth v4.0 Compliant Protocol Stack for

•

TPS62730 is a 2-MHz Step-Down Converter

Single-Mode BLE Solution

With Bypass Mode

–

Complete Power-Optimized Stack,

Including Controller and Host

•

Extends Battery Lifetime by up to 20%

Reduced Current in All Active Modes

–

GAP – Central, Peripheral, Observer, or

Broadcaster (Including Combination

Roles)

30-nA Bypass Mode Current to Support Low-

Power Modes

•

RF Performance Unchanged

–

ATT / GATT – Client and Server

Small Package Allows for Small Solution Size

CC2541 Controllable

SMP – AES-128 Encryption and

Decryption

–

L2CAP

DESCRIPTION

–

Sample Applications and Profiles

The CC2541 is a power-optimized true system-on-

chip (SoC) solution for both Bluetooth low energy and

proprietary 2.4-GHz applications. It enables robust

network nodes to be built with low total bill-of-material

costs. The CC2541 combines the excellent

performance of a leading RF transceiver with an

industry-standard enhanced 8051 MCU, in-system

programmable flash memory, 8-KB RAM, and many

other powerful supporting features and peripherals.

The CC2541 is highly suited for systems where

ultralow power consumption is required. This is

specified by various operating modes. Short transition

times between operating modes further enable low

power consumption.

–

Generic Applications for GAP Central

and Peripheral Roles

Proximity, Accelerometer, Simple Keys,

and Battery GATT Services

More Applications Supported in BLE

Software Stack

–

Multiple Configuration Options

–

Single-Chip Configuration, Allowing

Applications to Run on CC2541

–

Network Processor Interface for

Applications Running on an External

Microcontroller

The CC2541 is pin-compatible with the CC2540 in

the 6-mm × 6-mm QFN40 package, if the USB is not

used on the CC2540 and the I²C/extra I/O is not used

on the CC2541. Compared to the CC2540, the

CC2541 provides lower RF current consumption. The

CC2541 does not have the USB interface of the

CC2540, and provides lower maximum output power

in TX mode. The CC2541 also adds a HW I²C

interface.

BTool – Windows PC Application for

Evaluation, Development, and Test

APPLICATIONS

•

2.4-GHz Bluetooth low energy Systems

Proprietary 2.4-GHz Systems

Human-Interface Devices (Keyboard, Mouse,

Remote Control)

The CC2541 is pin-compatible with the CC2533

RF4CE-optimized IEEE 802.15.4 SoC.

•

Sports and Leisure Equipment

Mobile Phone Accessories

Consumer Electronics

The CC2541 comes in two different versions:

CC2541F128/F256, with 128 KB and 256 KB of flash

memory, respectively.

For the CC2541 block diagram, see Figure 1.

2

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SWRS110D –JANUARY 2012–REVISED JUNE 2013

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

VDD (2 V–3.6 V)

ON-CHIP VOLTAGE

REGULATOR

DCOUPL

RESET

WATCHDOG TIMER

RESET_N

POWER-ON RESET

BROWN OUT

XOSC_Q2

XOSC_Q1

32-MHZ

CRYSTAL OSC

CLOCK MUX and

CALIBRATION

SLEEP TIMER

32.768-kHz

CRYSTAL OSC

P2_4

P2_3

P2_2

P2_1

P2_0

POWER MGT. CONTROLLER

DEBUG

INTERFACE

HIGH SPEED

RC-OSC

32-kHz

RC-OSC

PDATA

XRAM

IRAM

SFR

RAM

SRAM

P1_7

P1_6

P1_5

P1_4

P1_3

P1_2

P1_1

P1_0

8051 CPU

CORE

MEMORY

ARBITRATOR

FLASH

UNIFIED

DMA

FLASH CTRL

1-KB SRAM

IRQ

CTRL

P0_7

P0_6

P0_5

P0_4

P0_3

P0_2

P0_1

P0_0

ANALOG COMPARATOR

OP-

FIFOCTRL

RADIO

REGISTERS

AES

ENCRYPTION

and

DECRYPTION

DS ADC

AUDIO / DC

Link Layer Engine

DEMODULATOR

MODULATOR

I²C

SDA

SCL

USART 0

USART 1

RECEIVE

TRANSMIT

TIMER 1 (16-Bit)

TIMER 2

(BLE LL TIMER)

TIMER 3 (8-bit)

TIMER 4 (8-bit)

RF_P RF_N

DIGITAL

ANALOG

MIXED

Figure 1. Block Diagram

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SWRS110D –JANUARY 2012–REVISED JUNE 2013

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

MAX

UNIT

V

Supply voltage

All supply pins must have the same voltage

3.9

Voltage on any digital pin

Input RF level

VDD + 0.3 ≤ 3.9

V

10

dBm

°C

Storage temperature range

–40

125

All pins, excluding pins 25 and 26, according to human-body

model, JEDEC STD 22, method A114

2

1

kV

V

All pins, according to human-body model, JEDEC STD 22,

method A114

ESD⁽²⁾

According to charged-device model, JEDEC STD 22, method

C101

500

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) CAUTION: ESD sesnsitive device. Precautions should be used when handling the device in order to prevent permanent damage.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM

MAX

85

UNIT

°C

Operating ambient temperature range, T_A

Operating supply voltage

–40

2

3.6

V

ELECTRICAL CHARACTERISTICS

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C and VDD = 3 V,

1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

RX mode, standard mode, no peripherals active, low MCU

activity

17.9

RX mode, high-gain mode, no peripherals active, low MCU

activity

20.2

mA

TX mode, –20 dBm output power, no peripherals active, low

MCU activity

16.8

TX mode, 0 dBm output power, no peripherals active, low

MCU activity

18.2

270

Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-

MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD and

sleep timer active; RAM and register retention

I_core

Core current consumption

Power mode 2. Digital regulator off; 16-MHz RCOSC and 32-

MHz crystal oscillator off; 32.768-kHz XOSC, POR, and sleep

timer active; RAM and register retention

µA

1

Power mode 3. Digital regulator off; no clocks; POR active;

RAM and register retention

0.5

Low MCU activity: 32-MHz XOSC running. No radio or

peripherals. Limited flash access, no RAM access.

6.7

mA

Timer 1. Timer running, 32-MHz XOSC used

Timer 2. Timer running, 32-MHz XOSC used

Timer 3. Timer running, 32-MHz XOSC used

Timer 4. Timer running, 32-MHz XOSC used

Sleep timer, including 32.753-kHz RCOSC

ADC, when converting

90

Peripheral current consumption

(Adds to core current I_corefor each

peripheral unit activated)

60

μA

I_peri

70

0.6

1.2

mA

4

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SWRS110D –JANUARY 2012–REVISED JUNE 2013

GENERAL CHARACTERISTICS

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C and VDD = 3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

WAKE-UP AND TIMING

Digital regulator on, 16-MHz RCOSC and 32-MHz crystal

oscillator off. Start-up of 16-MHz RCOSC

Power mode 1 → Active

4

120

500

μs

Digital regulator off, 16-MHz RCOSC and 32-MHz crystal

oscillator off. Start-up of regulator and 16-MHz RCOSC

Power mode 2 or 3 → Active

Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC,

with 32-MHz XOSC OFF

μs

Active → TX or RX

With 32-MHz XOSC initially on

Proprietary auto mode

BLE mode

180

130

150

RX/TX turnaround

μs

RADIO PART

RF frequency range

Programmable in 1-MHz steps

2379

2496

MHz

2 Mbps, GFSK, 500-kHz deviation

2 Mbps, GFSK, 320-kHz deviation

1 Mbps, GFSK, 250-kHz deviation

1 Mbps, GFSK, 160-kHz deviation

500 kbps, MSK

Data rate and modulation format

250 kbps, GFSK, 160-kHz deviation

250 kbps, MSK

RF RECEIVE SECTION

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C, VDD = 3 V, f_c= 2440 MHz

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER

Receiver sensitivity

–90

–1

–9

–2

36

41

dBm

dB

Saturation

BER < 0.1%

Co-channel rejection

Wanted signal at –67 dBm

±2 MHz offset, 0.1% BER, wanted signal –67 dBm

±4 MHz offset, 0.1% BER, wanted signal –67 dBm

±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm

In-band blocking rejection

dB

Including both initial tolerance and drift. Sensitivity better than –67dBm,

250 byte payload. BER 0.1%

Frequency error tolerance⁽¹⁾

–300

–120

300

120

kHz

Symbol rate error

tolerance⁽²⁾

Maximum packet length. Sensitivity better than–67dBm, 250 byte

payload. BER 0.1%

ppm

2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER

Receiver sensitivity

–86

–7

dBm

dB

Saturation

BER < 0.1%

Co-channel rejection

Wanted signal at –67 dBm

–12

–1

±2 MHz offset, 0.1% BER, wanted signal –67 dBm

±4 MHz offset, 0.1% BER, wanted signal –67 dBm

±6 MHz or greater offset, 0.1% BER, wanted signal –67 dBm

In-band blocking rejection

34

dB

39

Including both initial tolerance and drift. Sensitivity better than –67 dBm,

250 byte payload. BER 0.1%

Frequency error tolerance⁽¹⁾

–300

–120

300

120

kHz

Symbol rate error

tolerance⁽²⁾

Maximum packet length. Sensitivity better than –67 dBm, 250 byte

payload. BER 0.1%

ppm

(1) Difference between center frequency of the received RF signal and local oscillator frequency

(2) Difference between incoming symbol rate and the internally generated symbol rate

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RF RECEIVE SECTION (continued)

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C, VDD = 3 V, f_c= 2440 MHz

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

1 Mbps, GFSK, 250-kHz Deviation, Bluetooth low energy Mode, 0.1% BER

High-gain mode

Receiver sensitivity⁽³⁾⁽⁴⁾

–94

dBm

–88

Standard mode

Saturation⁽⁴⁾

Co-channel rejection⁽⁴⁾

BER < 0.1%

5

–6

dBm

dB

Wanted signal –67 dBm

±1 MHz offset, 0.1% BER, wanted signal –67 dBm

±2 MHz offset, 0.1% BER, wanted signal –67 dBm

±3 MHz offset, 0.1% BER, wanted signal –67 dBm

>6 MHz offset, 0.1% BER, wanted signal –67 dBm

Minimum interferer level < 2 GHz (Wanted signal –67 dBm)

Minimum interferer level [2 GHz, 3 GHz] (Wanted signal –67 dBm)

Minimum interferer level > 3 GHz (Wanted signal –67 dBm)

Minimum interferer level

–2

26

In-band blocking rejection⁽⁴⁾

dB

34

33

–21

–25

–7

Out-of-band blocking

rejection⁽⁴⁾

dBm

Intermodulation⁽⁴⁾

–36

dBm

kHz

Including both initial tolerance and drift. Sensitivity better than -67dBm,

250 byte payload. BER 0.1%

Frequency error tolerance⁽⁵⁾

–250

–80

250

80

Symbol rate error

tolerance⁽⁶⁾

Maximum packet length. Sensitivity better than –67 dBm, 250 byte

payload. BER 0.1%

ppm

1 Mbps, GFSK, 160-kHz Deviation, 0.1% BER

Receiver sensitivity⁽⁷⁾

–91

0

dBm

dB

Saturation

BER < 0.1%

Co-channel rejection

Wanted signal 10 dB above sensitivity level

±1-MHz offset, 0.1% BER, wanted signal –67 dBm

±2-MHz offset, 0.1% BER, wanted signal –67 dBm

±3-MHz offset, 0.1% BER, wanted signal -–67 dBm

>6-MHz offset, 0.1% BER, wanted signal –67 dBm

–9

2

24

27

32

In-band blocking rejection

dB

Including both initial tolerance and drift. Sensitivity better than –67 dBm,

250-byte payload. BER 0.1%

Frequency error tolerance⁽⁵⁾

–200

–80

200

80

kHz

Symbol rate error

tolerance⁽⁶⁾

Maximum packet length. Sensitivity better than –67 dBm, 250-byte

payload. BER 0.1%

ppm

500 kbps, MSK, 0.1% BER

Receiver sensitivity⁽⁷⁾

Saturation

–99

0

dBm

dB

BER < 0.1%

Co-channel rejection

Wanted signal –67 dBm

–5

20

27

28

±1-MHz offset, 0.1% BER, wanted signal –67 dBm

±2-MHz offset, 0.1% BER, wanted signal –67 dBm

>2-MHz offset, 0.1% BER, wanted signal –67 dBm

In-band blocking rejection

dB

Including both initial tolerance and drift. Sensitivity better than –67 dBm,

250-byte payload. BER 0.1%

Frequency error tolerance

Symbol rate error tolerance

–150

–80

150

80

kHz

Maximum packet length. Sensitivity better than –67 dBm, 250-byte

payload. BER 0.1%

ppm

(3) The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard

mode.

(4) Results based on standard-gain mode.

(5) Difference between center frequency of the received RF signal and local oscillator frequency

(6) Difference between incoming symbol rate and the internally generated symbol rate

(7) Results based on high-gain mode.

6

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SWRS110D –JANUARY 2012–REVISED JUNE 2013

RF RECEIVE SECTION (continued)

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C, VDD = 3 V, f_c= 2440 MHz

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

250 kbps, GFSK, 160 kHz Deviation, 0.1% BER

(8)

Receiver sensitivity

–98

0

dBm

dB

Saturation

BER < 0.1%

Co-channel rejection

Wanted signal -67 dBm

–3

23

28

29

±1-MHz offset, 0.1% BER, wanted signal –67 dBm

±2-MHz offset, 0.1% BER, wanted signal –67 dBm

>2-MHz offset, 0.1% BER, wanted signal –67 dBm

In-band blocking rejection

dB

Including both initial tolerance and drift. Sensitivity better than –67 dBm,

250-byte payload. BER 0.1%

Frequency error tolerance⁽⁹⁾

–150

–80

150

80

kHz

Symbol rate error

tolerance⁽¹⁰⁾

Maximum packet length. Sensitivity better than –67 dBm, 250-byte

payload. BER 0.1%

ppm

250 kbps, MSK, 0.1% BER

(11)

Receiver sensitivity

–99

0

dBm

dB

Saturation

BER < 0.1%

Co-channel rejection

Wanted signal -67 dBm

–5

20

29

30

±1-MHz offset, 0.1% BER, wanted signal –67 dBm

±2-MHz offset, 0.1% BER, wanted signal –67 dBm

>2-MHz offset, 0.1% BER, wanted signal –67 dBm

In-band blocking rejection

Frequency error tolerance

dB

Including both initial tolerance and drift. Sensitivity better than –67 dBm,

250-byte payload. BER 0.1%

–150

–80

150

80

kHz

Maximum packet length. Sensitivity better than –67 dBm, 250-byte

payload. BER 0.1%

Symbol rate error tolerance

ppm

ALL RATES/FORMATS

Spurious emission in RX.

Conducted measurement

f < 1 GHz

f > 1 GHz

–67

–57

dBm

Spurious emission in RX.

Conducted measurement

(8) Results based on standard-gain mode.

(9) Difference between center frequency of the received RF signal and local oscillator frequency

(10) Difference between incoming symbol rate and the internally generated symbol rate

(11) Results based on high-gain mode.

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RF TRANSMIT SECTION

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C, VDD = 3 V and f_c= 2440 MHz

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dBm

dB

Delivered to a single-ended 50-Ω load through a balun using

maximum recommended output power setting

0

Output power

Delivered to a single-ended 50-Ω load through a balun using

minimum recommended output power setting

–23

23

Programmable output power Delivered to a single-ended 50-Ω load through a balun using

range

minimum recommended output power setting

f < 1 GHz

–52

–48

dBm

Spurious emission conducted f > 1 GHz

measurement

Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and

EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)

Differential impedance as seen from the RF port (RF_P and RF_N)

toward the antenna

Optimum load impedance

70 +j30

Ω

Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC

resonator in front of the antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect

both from the signal trace to a good RF ground.

CURRENT CONSUMPTION WITH TPS62730

Measured on Texas Instruments CC2541 TPA62730 EM reference design with T_A= 25°C, VDD = 3 V and f_c= 2440 MHz,

1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy Mode, 1% BER⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RX mode, standard mode, no peripherals active, low MCU activity, MCU

at 1 MHz

14.7

RX mode, high-gain mode, no peripherals active, low MCU activity,

MCU at 1 MHz

16.7

13.1

Current consumption

mA

TX mode, –20 dBm output power, no peripherals active, low MCU activity,

MCU at 1 MHz

TX mode, 0 dBm output power, no peripherals active, low MCU activity,

MCU at 1 MHz

14.3

(1) 0.1% BER maps to 30.8% PER

32-MHz CRYSTAL OSCILLATOR

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C and VDD = 3 V

PARAMETER

Crystal frequency

TEST CONDITIONS

MIN

TYP

MAX UNIT

32

MHz

Crystal frequency accuracy

requirement⁽¹⁾

–40

40 ppm

ESR

C₀

Equivalent series resistance

Crystal shunt capacitance

Crystal load capacitance

Start-up time

6

1

60

7

Ω

pF

ms

C_L

10

16

0.25

The crystal oscillator must be in power down for a guard

time before it is used again. This requirement is valid for

all modes of operation. The need for power-down guard

time can vary with crystal type and load.

Power-down guard time

3

ms

(1) Including aging and temperature dependency, as specified by [1]

8

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SWRS110D –JANUARY 2012–REVISED JUNE 2013

32.768-kHz CRYSTAL OSCILLATOR

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C and VDD = 3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Crystal frequency

32.768

kHz

Crystal frequency accuracy requirement⁽¹⁾

Equivalent series resistance

Crystal shunt capacitance

Crystal load capacitance

Start-up time

–40

40

130

2

ppm

kΩ

pF

s

ESR

C₀

40

0.9

12

C_L

16

0.4

(1) Including aging and temperature dependency, as specified by [1]

32-kHz RC OSCILLATOR

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C and VDD = 3 V.

PARAMETER

Calibrated frequency⁽¹⁾

TEST CONDITIONS

MIN

TYP

32.753

±0.2%

0.4

MAX UNIT

kHz

Frequency accuracy after calibration

Temperature coefficient⁽²⁾

Supply-voltage coefficient⁽³⁾

Calibration time⁽⁴⁾

%/°C

%/V

ms

3

2

(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.

(2) Frequency drift when temperature changes after calibration

(3) Frequency drift when supply voltage changes after calibration

(4) When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator

is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.

16-MHz RC OSCILLATOR

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C and VDD = 3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

16

MAX

UNIT

Frequency⁽¹⁾

MHz

Uncalibrated frequency accuracy

Calibrated frequency accuracy

Start-up time

±18%

±0.6%

10

μs

Initial calibration time⁽²⁾

50

(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.

(2) When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator

is performed while SLEEPCMD.OSC_PD is set to 0.

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RSSI CHARACTERISTICS

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C and VDD = 3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER

Reduced gain by AGC algorithm

64

79

99

±6

1

Useful RSSI range⁽¹⁾

dB

High gain by AGC algorithm

Reduced gain by AGC algorithm

RSSI offset⁽¹⁾

dBm

High gain by AGC algorithm

Absolute uncalibrated accuracy⁽¹⁾

Step size (LSB value)

dB

All Other Rates/Formats

Standard mode

64

98

107

±3

1

Useful RSSI range⁽¹⁾

High-gain mode

dB

Standard mode

RSSI offset⁽¹⁾

dBm

High-gain mode

Absolute uncalibrated accuracy⁽¹⁾

Step size (LSB value)

dB

(1) Assuming CC2541 EM reference design. Other RF designs give an offset from the reported value.

FREQUENCY SYNTHESIZER CHARACTERISTICS

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C, VDD = 3 V and f_c= 2440 MHz

PARAMETER

TEST CONDITIONS

At ±1-MHz offset from carrier

MIN

TYP

–109

–112

–119

MAX

UNIT

Phase noise, unmodulated carrier

At ±3-MHz offset from carrier

At ±5-MHz offset from carrier

dBc/Hz

ANALOG TEMPERATURE SENSOR

Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C and VDD = 3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

12-bit

/ 1°C

0.1 V

°C

Output

1480

4.5

1

Temperature coefficient

Voltage coefficient

Measured using integrated ADC, internal band-gap voltage

reference, and maximum resolution

Initial accuracy without calibration

Accuracy using 1-point calibration

Current consumption when enabled

±10

±5

°C

0.5

mA

COMPARATOR CHARACTERISTICS

T_A= 25°C, VDD = 3 V. All measurement results are obtained using the CC2541 reference designs, post-calibration.

PARAMETER

Common-mode maximum voltage

Common-mode minimum voltage

Input offset voltage

TEST CONDITIONS

MIN

TYP MAX UNIT

VDD

–0.3

1

V

mV

µV/°C

mV/V

nA

Offset vs temperature

Offset vs operating voltage

Supply current

16

4

230

0.15

Hysteresis

mV

10

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ADC CHARACTERISTICS

T_A= 25°C and VDD = 3 V

PARAMETER

TEST CONDITIONS

VDD is voltage on AVDD5 pin

MIN

0

TYP

MAX

VDD

UNIT

V

Input voltage

External reference voltage

0

V

External reference voltage differential VDD is voltage on AVDD5 pin

0

V

Input resistance, signal

Full-scale signal⁽¹⁾

Simulated using 4-MHz clock speed

Peak-to-peak, defines 0 dBFS

197

2.97

5.7

kΩ

V

Single-ended input, 7-bit setting

Single-ended input, 9-bit setting

7.5

Single-ended input, 10-bit setting

Single-ended input, 12-bit setting

Differential input, 7-bit setting

9.3

10.3

6.5

ENOB⁽¹⁾

Effective number of bits

bits

Differential input, 9-bit setting

8.3

Differential input, 10-bit setting

10

Differential input, 12-bit setting

11.5

9.7

10-bit setting, clocked by RCOSC

12-bit setting, clocked by RCOSC

7-bit setting, both single and differential

Single ended input, 12-bit setting, –6 dBFS⁽¹⁾

Differential input, 12-bit setting, –6 dBFS⁽¹⁾

Single-ended input, 12-bit setting⁽¹⁾

Differential input, 12-bit setting⁽¹⁾

Single-ended input, 12-bit setting, –6 dBFS⁽¹⁾

Differential input, 12-bit setting, –6 dBFS⁽¹⁾

10.9

0–20

–75.2

–86.6

70.2

79.3

78.8

88.9

Useful power bandwidth

Total harmonic distortion

kHz

dB

THD

Signal to nonharmonic ratio

dB

Differential input, 12-bit setting, 1-kHz sine

(0 dBFS), limited by ADC resolution

CMRR

Common-mode rejection ratio

Crosstalk

>84

Single ended input, 12-bit setting, 1-kHz sine

(0 dBFS), limited by ADC resolution

dB

Offset

Midscale

–3

0.68%

0.05

0.9

mV

Gain error

12-bit setting, mean⁽¹⁾

12-bit setting, maximum⁽¹⁾

12-bit setting, mean⁽¹⁾

DNL

INL

Differential nonlinearity

Integral nonlinearity

LSB

4.6

12-bit setting, maximum⁽¹⁾

12-bit setting, mean, clocked by RCOSC

12-bit setting, max, clocked by RCOSC

Single ended input, 7-bit setting⁽¹⁾

Single ended input, 9-bit setting⁽¹⁾

Single ended input, 10-bit setting⁽¹⁾

Single ended input, 12-bit setting⁽¹⁾

Differential input, 7-bit setting⁽¹⁾

Differential input, 9-bit setting⁽¹⁾

Differential input, 10-bit setting⁽¹⁾

Differential input, 12-bit setting⁽¹⁾

7-bit setting

13.3

10

29

35.4

46.8

57.5

66.6

40.7

51.6

61.8

70.8

20

SINAD

(–THD+N)

Signal-to-noise-and-distortion

dB

9-bit setting

36

Conversion time

μs

10-bit setting

68

12-bit setting

132

(1) Measured with 300-Hz sine-wave input and VDD as reference.

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ADC CHARACTERISTICS (continued)

T_A= 25°C and VDD = 3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

1.2

4

MAX

UNIT

mA

Power consumption

Internal reference VDD coefficient

mV/V

Internal reference temperature

coefficient

0.4

mV/10°C

V

Internal reference voltage

1.24

CONTROL INPUT AC CHARACTERISTICS

T_A= –40°C to 85°C, VDD = 2 V to 3.6 V

PARAMETER

TEST CONDITIONS

MIN TYP

MAX UNIT

The undivided system clock is 32 MHz when crystal oscillator is used.

The undivided system clock is 16 MHz when calibrated 16-MHz RC

oscillator is used.

System clock, f_SYSCLK

t_SYSCLK= 1/ f_SYSCLK

16

32

MHz

See item 1, Figure 2. This is the shortest pulse that is recognized as

a complete reset pin request. Note that shorter pulses may be

recognized but do not lead to complete reset of all modules within the

chip.

RESET_N low duration

Interrupt pulse duration

1

µs

ns

See item 2, Figure 2.This is the shortest pulse that is recognized as

an interrupt request.

20

RESET_N

1

2

Px.n

T0299-01

Figure 2. Control Input AC Characteristics

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SPI AC CHARACTERISTICS

T_A= –40°C to 85°C, VDD = 2 V to 3.6 V

PARAMETER

TEST CONDITIONS

MIN

250

TYP MAX UNIT

Master, RX and TX

Slave, RX and TX

Master

t₁

SCK period

ns

SCK duty cycle

SSN low to SCK

50%

Master

63

t₂

t₃

ns

Slave

Master

SCK to SSN high

ns

Slave

t₄

t₅

t₆

t₇

MOSI early out

MOSI late out

MISO setup

MISO hold

Master, load = 10 pF

Master

7

ns

10

90

10

Master

SCK duty cycle

MOSI setup

MOSI hold

Slave

50%

t₁₀

t₁₁

t₉

Slave

35

10

Slave

MISO late out

Slave, load = 10 pF

Master, TX only

Master, RX and TX

Slave, RX only

Slave, RX and TX

95

8

4

Operating frequency

MHz

8

4

SCK

t₂

t₃

SSN

t₄

t₅

MOSI

D0

X

D1

t₆

t₇

MISO

X

D0

X

T0478-01

Figure 3. SPI Master AC Characteristics

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SCK

t₂

t₃

SSN

t₈

t₉

MISO

D0

X

D1

t₁₀

t₁₁

MOSI

X

D0

X

T0479-01

Figure 4. SPI Slave AC Characteristics

DEBUG INTERFACE AC CHARACTERISTICS

T_A= –40°C to 85°C, VDD = 2 V to 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

ns

f_{clk_dbg}

Debug clock frequency (see Figure 5)

Allowed high pulse on clock (see Figure 5)

Allowed low pulse on clock (see Figure 5)

12

t₁

t₂

35

ns

EXT_RESET_N low to first falling edge on debug clock (see

Figure 7)

t₃

167

ns

t₄

t₅

t₆

t₇

t₈

Falling edge on clock to EXT_RESET_N high (see Figure 7)

EXT_RESET_N high to first debug command (see Figure 7)

Debug data setup (see Figure 6)

83

2

ns

Debug data hold (see Figure 6)

4

Clock-to-data delay (see Figure 6)

Load = 10 pF

30

Time

DEBUG_CLK

P2_2

t₁

t₂

1/f_{clk_dbg}

T0436-01

Figure 5. Debug Clock – Basic Timing

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Time

DEBUG_CLK

P2_2

RESET_N

t₃

t₄

t₅

T0437-01

Figure 6. Debug Enable Timing

Time

DEBUG_CLK

P2_2

DEBUG_DATA

(to CC2541)

P2_1

DEBUG_DATA

(from CC2541)

P2_1

t₆

t₇

t₈

Figure 7. Data Setup and Hold Timing

TIMER INPUTS AC CHARACTERISTICS

T_A= –40°C to 85°C, VDD = 2 V to 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Synchronizers determine the shortest input pulse that can be

recognized. The synchronizers operate at the current system

clock rate (16 MHz or 32 MHz).

Input capture pulse duration

1.5

t_SYSCLK

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DC CHARACTERISTICS

T_A= 25°C, VDD = 3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Logic-0 input voltage

0.5

Logic-1 input voltage

2.4

–50

V

Logic-0 input current

Input equals 0 V

50

nA

kΩ

V

Logic-1 input current

Input equals VDD

I/O-pin pullup and pulldown resistors

Logic-0 output voltage, 4- mA pins

Logic-1 output voltage, 4-mA pins

Logic-0 output voltage, 20- mA pins

Logic-1 output voltage, 20-mA pins

20

Output load 4 mA

Output load 20 mA

0.5

2.5

V

DEVICE INFORMATION

PIN DESCRIPTIONS

The CC2541 pinout is shown in Figure 8 and a short description of the pins follows.

CC2541

RHA Package

(Top View)

40 39 38 37 36 35 34 33 32 31

GND

SCL

R_BIAS

1

2

30

29

28

27

26

25

24

23

22

21

AVDD4

AVDD1

AVDD2

RF_N

SDA

3

NC

4

P1_5

P1_4

P1_3

P1_2

P1_1

DVDD2

5

GND

Ground Pad

RF_P

6

7

AVDD3

XOSC_Q2

XOSC_Q1

8

9

10

AVDD5

11 12 13 14 15 16 17 18 19 20

NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.

Figure 8. Pinout Top View

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PIN DESCRIPTIONS

PIN NAME

28

27

24

29

21

31

40

39

10

1

PIN TYPE

Power (analog)

Power (digital)

Ground pin

Ground

DESCRIPTION

AVDD1

AVDD2

AVDD3

AVDD4

AVDD5

AVDD6

DCOUPL

DVDD1

DVDD2

GND

2-V–3.6-V analog power-supply connection

1.8-V digital power-supply decoupling. Do not use for supplying external circuits.

2-V–3.6-V digital power-supply connection

Connect to GND

GND

—

4

The ground pad must be connected to a solid ground plane.

NC

Unused pins

Digital I/O

Not connected

P0_0

19

18

17

16

15

14

13

12

11

9

Port 0.0

P0_1

Digital I/O

Port 0.1

P0_2

Digital I/O

Port 0.2

P0_3

Digital I/O

Port 0.3

P0_4

Digital I/O

Port 0.4

P0_5

Digital I/O

Port 0.5

P0_6

Digital I/O

Port 0.6

P0_7

Digital I/O

Port 0.7

P1_0

Digital I/O

Port 1.0 – 20-mA drive capability

Port 1.1 – 20-mA drive capability

Port 1.2

P1_1

Digital I/O

P1_2

8

Digital I/O

P1_3

7

Digital I/O

Port 1.3

P1_4

6

Digital I/O

Port 1.4

P1_5

5

Digital I/O

Port 1.5

P1_6

38

37

36

35

34

33

Digital I/O

Port 1.6

P1_7

Digital I/O

Port 1.7

P2_0

Digital I/O

Port 2.0

P2_1/DD

P2_2/DC

Digital I/O

Port 2.1 / debug data

Port 2.2 / debug clock

Port 2.3/32.768 kHz XOSC

Digital I/O

P2_3/

Digital I/O, Analog I/O

OSC32K_Q2

P2_4/

32

Digital I/O, Analog I/O

Port 2.4/32.768 kHz XOSC

OSC32K_Q1

RBIAS

30

20

26

Analog I/O

Digital input

RF I/O

External precision bias resistor for reference current

Reset, active-low

RESET_N

RF_N

Negative RF input signal to LNA during RX

Negative RF output signal from PA during TX

RF_P

SCL

25

2

RF I/O

Positive RF input signal to LNA during RX

Positive RF output signal from PA during TX

Can be used as I²C clock pin or digital I/O. Leave floating if not used. If grounded

disable pull up

Can be used as I²C data pin or digital I/O. Leave floating if not used. If grounded

disable pull up

I²C clock or digital I/O

SDA

3

XOSC_Q1

XOSC_Q2

22

23

Analog I/O

32-MHz crystal oscillator pin 1 or external clock input

32-MHz crystal oscillator pin 2

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BLOCK DIAGRAM

A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three

categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related

modules. In the following subsections, a short description of each module is given.

VDD (2 V–3.6 V)

ON-CHIP VOLTAGE

REGULATOR

DCOUPL

RESET

WATCHDOG TIMER

RESET_N

POWER-ON RESET

BROWN OUT

XOSC_Q2

XOSC_Q1

32-MHZ

CRYSTAL OSC

CLOCK MUX and

CALIBRATION

SLEEP TIMER

32.768-kHz

CRYSTAL OSC

P2_4

P2_3

P2_2

P2_1

P2_0

POWER MGT. CONTROLLER

DEBUG

INTERFACE

HIGH SPEED

RC-OSC

32-kHz

RC-OSC

PDATA

XRAM

IRAM

SFR

RAM

SRAM

P1_7

P1_6

P1_5

P1_4

P1_3

P1_2

P1_1

P1_0

8051 CPU

CORE

MEMORY

ARBITRATOR

FLASH

UNIFIED

DMA

FLASH CTRL

1-KB SRAM

IRQ

CTRL

P0_7

P0_6

P0_5

P0_4

P0_3

P0_2

P0_1

P0_0

ANALOG COMPARATOR

OP-

FIFOCTRL

RADIO

REGISTERS

AES

ENCRYPTION

and

DECRYPTION

DS ADC

AUDIO / DC

Link Layer Engine

DEMODULATOR

MODULATOR

I²C

SDA

SCL

USART 0

USART 1

RECEIVE

TRANSMIT

TIMER 1 (16-Bit)

TIMER 2

(BLE LL TIMER)

TIMER 3 (8-bit)

TIMER 4 (8-bit)

RF_P RF_N

DIGITAL

ANALOG

MIXED

Figure 9. CC2541 Block Diagram

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BLOCK DESCRIPTIONS

A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three

categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related

modules. In the following subsections, a short description of each module is given.

CPU and Memory

The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,

DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.

The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical

memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access

of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is

responsible for performing arbitration and sequencing between simultaneous memory accesses to the same

physical memory.

The SFR bus is drawn conceptually in Figure 9 as a common bus that connects all hardware peripherals to the

memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio

register bank, even though these are indeed mapped into XDATA memory space.

The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is

an ultralow-power SRAM that retains its contents even when the digital part is powered off (power mode 2 and

mode 3).

The 128/256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and

maps into the CODE and XDATA memory spaces.

Peripherals

Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise

programming. See User Guide for details on the flash controller.

A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory

space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing

mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be

located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers,

ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfers

between a single SFR or XREG address and flash/SRAM.

Each CC2541 contains a unique 48-bit IEEE address that can be used as the public device address for a

Bluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetooth

specfication.

The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which

is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the

device is in a sleep mode (power modes 1 and 2) by bringing the CC2541 back to the active mode.

The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.

Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillators

are enabled, stop and start execution of the user program, execute instructions on the 8051 core, set code

breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform in-

circuit debugging and external flash programming elegantly.

The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral

modules control certain pins or whether they are under software control, and if so, whether each pin is configured

as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects

to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.

The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or an

internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode

3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power mode 1

or mode 2.

A built-in watchdog timer allows the CC2541 to reset itself if the firmware hangs. When enabled by software,

the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.

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Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period

value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of

the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It

can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the

output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.

Timer 2 is a 40-bit timer. It has a 16-bit counter with a configurable timer period and a 24-bit overflow counter

that can be used to keep track of the number of periods that have transpired. A 40-bit capture register is also

used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which

transmission ends. There are two 16-bit output compare registers and two 24-bit overflow compare registers that

can be used to give exact timing for start of RX or TX to the radio or general interrupts.

Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,

an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter

channels can be used as PWM output.

USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide double

buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex

applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free

for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead

of using some oversampling scheme, and are thus well-suited for high data rates.

The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with

128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware

support for CCM.

The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,

respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The

inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a single-

ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can

automate the process of periodic sampling or conversion over a sequence of channels.

The I²C module provides a digital peripheral connection with two pins and supports both master and slave

operation. I²C support is compliant with the NXP I²C specification version 2.1 and supports standard mode (up to

100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit device addressing modes are supported, as well as

master and slave modes.

The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog

signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator

output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin

interrupt.

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TYPICAL CHARACTERISTICS

RX CURRENT

vs

TEMPERATURE

TX CURRENT

vs

TEMPERATURE

19

18.5

18

19.5

1 Mbps GFSK 250 kHz

TX Power Setting = 0 dBm

V_CC= 3 V

Standard Gain Setting

Input = −70 dBm

V_CC= 3 V

19

18.5

18

17.5

17

17.5

17

16.5

−40

−20

0

20

40

60

80

−40

−20

0

20

40

60

80

Temperature (°C)

G001

G002

Figure 10.

Figure 11.

RX SENSITIVITY

vs

TEMPERATURE

TX POWER

vs

TEMPERATURE

−84

−86

−88

−90

−92

4.0

2.0

1 Mbps GFSK 250 kHz

Standard Gain Setting

V_CC= 3 V

TX Power Setting = 0 dBm

V_CC= 3 V

0.0

−2.0

−4.0

−40

−20

0

20

40

60

80

−40

−20

0

20

40

60

80

Temperature (°C)

G003

G004

Figure 12.

Figure 13.

RX CURRENT

vs

SUPPLY VOLTAGE

TX CURRENT

vs

SUPPLY VOLTAGE

20

19.5

19

20

19.5

19

1 Mbps GFSK 250 kHz

Standard Gain Setting

Input = −70 dBm

T_A= 25°C

TX Power Setting = 0 dBm

T_A= 25°C

18.5

18

18.5

18

17.5

17

17.5

17

16.5

16

16.5

16

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

Voltage (V)

G005

G006

Figure 14.

Figure 15.

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TYPICAL CHARACTERISTICS (continued)

RX SENSITIVITY

vs

TX POWER

vs

SUPPLY VOLTAGE

−84

−86

−88

−90

−92

4

2

1 Mbps GFSK 250 kHz

Standard Gain Setting

T_A= 25°C

TX Power Setting = 0 dBm

T_A= 25°C

0

−2

−4

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

Voltage (V)

G007

G008

Figure 16.

Figure 17.

RX SENSITIVITY

vs

FREQUENCY

TX POWER

vs

FREQUENCY

−84

−86

−88

−90

−92

4

2

1 Mbps GFSK 250 kHz

Standard Gain Setting

T_A= 25°C

TX Power Setting = 0 dBm

T_A= 25°C

V_CC= 3 V

0

−2

−4

2400 2410 2420 2430 2440 2450 2460 2470 2480

Frequency (MHz)

2400 2410 2420 2430 2440 2450 2460 2470 2480

Frequency (MHz)

G009

G010

Figure 18.

Figure 19.

Table 1. Output Power⁽¹⁾⁽²⁾

TXPOWER Setting

0xE1

Typical Output Power (dBm)

0

0xD1

–2

0xC1

–4

0xB1

–6

0xA1

–8

0x91

–10

–12

–14

–16

–18

–20

–23

0x81

0x71

0x61

0x51

0x41

0x31

(1) Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C, VDD = 3 V and f_c= 2440 MHz. See SWRU191 for

recommended register settings.

(2) 1 Mbsp, GFSK, 250-kHz deviation, Bluetooth™ low energy mode, 1% BER

22

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SWRS110D –JANUARY 2012–REVISED JUNE 2013

Table 2. Output Power and Current Consumption

Typical Current Consumption

(mA)⁽¹⁾

Typical Current Consumption

With TPS62730 (mA)⁽²⁾

Typical Output Power (dBm)

0

18.2

16.8

14.3

13.1

–20

(1) Measured on Texas Instruments CC2541 EM reference design with T_A= 25°C, VDD = 3 V and f_c=

2440 MHz. See SWRU191 for recommended register settings.

(2) Measured on Texas Instruments CC2541 TPS62730 EM reference design with T_A= 25°C, VDD = 3 V

and f_c= 2440 MHz. See SWRU191 for recommended register settings.

TYPICAL CURRENT SAVINGS WHEN USING TPS62730

Current Consumption TX 0 dBm

0

Current Consumption RX SG

CLKCONMOD 0xBF

25

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

25

20

15

10

5

DC/DC OFF

DC/DC ON

Current Savings

20

15

10

5

Current Savings

0

2.1

2.4

2.7 3

Supply (V)

3.3

3.6

2.1

2.4

2.7 3

Supply (V)

3.3

3.6

Figure 20. Current Savings in TX at Room

Temperature

Figure 21. Current Savings in RX at Room

Temperature

The application note (SWRA365) has information regarding the CC2541 and TPS62730 combo board and the

current savings that can be achieved using the combo board.

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APPLICATION INFORMATION

Few external components are required for the operation of the CC2541. A typical application circuit is shown in

Figure 22.

32-kHz Crystal⁽¹⁾

C331

2-V to 3.6-V Power Supply

C401

C321

R301

RBIAS 30

GND

SCL

1

2

3

4

5

6

7

8

9

AVDD4 29

AVDD1 28

AVDD2 27

Antenna

(50 W)

SDA

NC

RF_N

RF_P

26

25

P1_5

P1_4

P1_3

P1_2

P1_1

CC2541

DIE ATTACH PAD

AVDD3 24

XOSC_Q2

23

22

XOSC_Q1

AVDD5 21

10 DVDD2

XTAL1

C221

C231

Power Supply Decoupling Capacitors are Not Shown

Digital I/O Not Connected

(1) 32-kHz crystal is mandatory when running the BLE protocol stack in low-power modes, except if the link layer is in

the standby state (Vol. 6 Part B Section 1.1 in [1]).

NOTE: Different antenna alternatives will be provided as reference designs.

Figure 22. CC2541 Application Circuit

Table 3. Overview of External Components (Excluding Supply Decoupling Capacitors)

Component

C401

Description

Value

1 µF

Decoupling capacitor for the internal 1.8-V digital voltage regulator

Precision resistor ±1%, used for internal biasing

R301

56 kΩ

Input/Output Matching

When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The

balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2541EM,

for recommended balun.

24

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SWRS110D –JANUARY 2012–REVISED JUNE 2013

Crystal

An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal

oscillator. See 32-MHz CRYSTAL OSCILLATOR for details. The load capacitance seen by the 32-MHz crystal is

given by:

1

C_L=

+ C_parasitic

1

+

C₂₂₁C₂₃₁

(1)

XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHz

crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-current

consumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal is

given by:

1

C_L=

+ C_parasitic

1

+

C₃₂₁C₃₃₁

(2)

A series resistor may be used to comply with the ESR requirement.

On-Chip 1.8-V Voltage Regulator Decoupling

The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor

(C401) for stable operation.

Power-Supply Decoupling and Filtering

Proper power-supply decoupling must be used for optimum performance. The placement and size of the

decoupling capacitors and the power supply filtering are very important to achieve the best performance in an

application. TI provides a compact reference design that should be followed very closely.

References

1. Bluetooth® Core Technical Specification document, version 4.0

http://www.bluetooth.com/SiteCollectionDocuments/Core_V40.zip

2. CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee^®Applications/CC2541 System-on-

Chip Solution for 2.4-GHz Bluetooth low energy Applications (SWRU191)

3. Current Savings in CC254x Using the TPS62730 (SWRA365).

Additional Information

Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and standard-

based wireless applications for use in industrial and consumer applications. Our selection includes RF

transceivers, RF transmitters, RF front ends, and System-on-Chips as well as various software solutions for the

sub-1- and 2.4-GHz frequency bands.

In addition, Texas Instruments provides a large selection of support collateral such as development tools,

technical documentation, reference designs, application expertise, customer support, third-party and university

programs.

The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the chance

to interact with fellow engineers from all over the world.

With a broad selection of product solutions, end application possibilities, and a range of technical support, Texas

Instruments offers the broadest low-power RF portfolio. We make RF easy!

The following subsections point to where to find more information.

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Texas Instruments Low-Power RF Web Site

•

Forums, videos, and blogs

RF design help

E2E interaction

Join us today at www.ti.com/lprf-forum.

Texas Instruments Low-Power RF Developer Network

Texas Instruments has launched an extensive network of low-power RF development partners to help customers

speed up their application development. The network consists of recommended companies, RF consultants, and

independent design houses that provide a series of hardware module products and design services, including:

•

RF circuit, low-power RF, and ZigBee^®design services

Low-power RF and ZigBee module solutions and development tools

RF certification services and RF circuit manufacturing

Need help with modules, engineering services or development tools?

Search the Low-Power RF Developer Network tool to find a suitable partner.

www.ti.com/lprfnetwork

Low-Power RF eNewsletter

The Low-Power RF eNewsletter keeps you up-to-date on new products, news releases, developers’ news, and

other news and events associated with low-power RF products from TI. The Low-Power RF eNewsletter articles

include links to get more online information.

Sign up today on

www.ti.com/lprfnewsletter

Spacer

REVISION HISTORY

Changes from Original (January 2012) to Revision A

Page

•

Changed data sheet status from Product Preview to Production Data ................................................................................ 1

Changes from Revision A (February 2012) to Revision B

Page

•

Changed the Temperature coefficient Unit value From: mV/°C To: / 0.1°C ....................................................................... 10

Changed Figure 22 text From: Optional 32-kHz Crystal To: 32-kHz Crystal ..................................................................... 24

Changes from Revision B (August 2012) to Revision C

Page

•

Changed the "Internal reference voltage" TYP value From 1.15 V To: 1.24 V .................................................................. 12

Changed pin XOSC_Q1 Pin Type From Analog O To: Analog I/O, and changed the Pin Description .............................. 17

Changed pin XOSC_Q2 Pin Type From Analog O To: Analog I/O .................................................................................... 17

Changes from Revision C (November 2012) to Revision D

Page

•

Changed the RF TRANSMIT SECTION, Output power TYP value From: –20 To: –23 ....................................................... 8

Changed the RF TRANSMIT SECTION, Programmable output power range TYP value From: 20 To: 23 ........................ 8

Added row 0x31 to Table 1 ................................................................................................................................................. 22

26

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型号：	CC2541F256RHAR
厂家：	TEXAS INSTRUMENTS
描述：	2.4-GHz Bluetoothâ¢ low energy and Proprietary System-on-Chip 2.4 - GHz的Bluetoothâ ?? ¢低能量和专有系统级芯片微控制器和处理器外围集成电路 uCs集成电路 uPs集成电路
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CC2541F256RHAR [TI]

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