BQ3285ESSNTR [TI]
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| 型号： | BQ3285ESSNTR |
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TEXAS INSTRUMENTS |
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bq3285
Real-Time Clock (RTC)
General Description
Features
➤ Calendar in day of the week, day
of the month, months, and years,
with automatic leap-year adjust-
ment
➤ Direct clock/calendar replace-
ment for IBM® AT-compatible
computers and other applications
The CMOS bq3285 is a low-power
microprocessor peripheral providing
a time-of-day clock and 100-year cal-
endar with alarm features and bat-
tery operation. Other features in-
clude three maskable interrupt
sources, square wave output, and 114
bytes of general nonvolatile storage.
➤ Time of day in seconds, minutes,
➤ Functionally compatible with the
and hours
DS1285
- 12- or 24-hour format
- Optional daylight saving
- Closely matches MC146818A
pin configuration
adjustment
The bq3285 write-protects the clock,
calendar, and storage registers during
power failure. A backup battery
then maintains data and operates the
clock and calendar.
➤ 114 bytes of general nonvolatile
➤ Programmable square wave out-
storage
put
➤ 160ns cycle time allows fast bus
➤ Three individually maskable in-
operation
terrupt event flags:
➤ Selectable Intel or Motorola bus
- Periodic rates from 122µs to
The bq3285 is a fully compatible
real-time clock for IBM AT com-
patible computers and other appli-
cations. The only external compo-
nents are a 32.768kHz crystal and
a backup battery
timing
500ms
➤ Less than 0.5µA load under bat-
- Time-of-day alarm once per
tery operation
second to once per day
- End-of-clock update cycle
➤ 24-pin plastic DIP or SOIC
➤ 14 bytes for clock/calendar and
control
➤ BCD or binary format for clock
and calendar data
Pin Names
Pin Connections
AD0–AD7
Multiplexed address/data
input/output
MOT
CS
Bus type select input
Chip select input
Address strobe input
Data strobe input
Read/write input
MOT
24
1
V
CC
SQW
NC
X1
X2
23
22
2
3
AS
4
RCL
BC
DS
AD
AD
AD
AD
AD
AD
AD
21
20
19
18
17
16
15
14
13
0
1
2
3
4
5
6
5
6
AD
AD
25
24
RCL
BC
0
1
5
R/W
INT
6
INT
RST
DS
7
8
9
10
11
Interrupt request
output
AD
AD
AD
AD
23
22
21
20
19
INT
RST
DS
2
3
4
5
7
8
9
RST
SQW
RCL
BC
Reset input
V
SS
V
NC
R/W
SS
Square wave output
RAM clear input
3V backup cell input
Crystal inputs
No connect
10
11
12
R/W
AS
CS
AD
7
V
SS
X1–X2
NC
28-Pin PLCC
PN328501.eps
24-Pin DIP or SOIC
PN328501.eps
VCC
VSS
+5V supply
Ground
Jan. 1999 E
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bq3285
Block Diagram
AD0–AD7 Multiplexed address/data input/
output
Pin Descriptions
MOT
Bus type select input
The bq3285 bus cycle consists of two
phases: the address phase and the data-
transfer phase. The address phase pre-
cedes the data-transfer phase. During the
address phase, an address placed on
AD0–AD7 is latched into the bq3285 on the
falling edge of the AS signal. During the
data-transfer phase of the bus cycle, the
AD0–AD7 pins serve as a bidirectional data
bus.
MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to VCC for Motorola timing or to VSS for
Intel timing (see Table 1). The setting
should not be changed during system opera-
tion. MOT is internally pulled low by a
30KΩ resistor.
Table 1. Bus Setup
AS
Address strobe input
Bus
Type
MOT
DS
R/W
AS
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD0–AD7. This demultiplexing pro-
cess is independent of the CS signal. For
DIP, SOIC, and PLCC packages with MOT =
VCC, the AS input is provided a signal simi-
lar to ALE in an Intel-based system.
Level Equivalent Equivalent Equivalent
DS, E, or
VCC
VSS
Motorola
R/W
WR,
AS
Φ2
RD,
Intel
MEMR, or MEMW, or ALE
I/OR
I/OW
Jan. 1999 E
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bq3285
DS
Data strobe input
RCL
RAM clear input
When MOT = VCC, DS controls data trans-
fer during a bq3285 bus cycle. During a
read cycle, the bq3285 drives the bus after
the rising edge on DS. During a write cycle,
the falling edge on DS is used to latch write
data into the chip.
A low level on the RCL pin causes the con-
tents of each of the 114 storage bytes to be
set to FF(hex). The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of VCC when
the oscillator is running. Using RAM clear
does not affect the battery load. This pin is
connected internally to a 30KΩ pull-up re-
sistor.
When MOT = VSS, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
Read/write input
R/W
BC
3V backup cell input
When MOT = VCC, the level on R/W identi-
fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
BC should be connected to a 3V backup cell
for RTC operation and storage register non-
volatility in the absence of power. When
VCC slews down past VBC (3V typical), the
integral control circuitry switches the
power source to BC. When VCC returns
above VBC, the power source is switched to
When MOT = VSS, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel-
based system. The rising edge on R/W
latches data into the bq3285.
VCC
.
Upon power-up, a voltage within the VBC
range must be present on the BC pin for
the oscillator to start up.
CS
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq3285.
RST
Reset input
The bq3285 is reset when RST is pulled low.
When reset, INT becomes high-impedance,
and the bq3285 is not accessible. Table 4 in
the Control/Status Registers section lists
the register bits that are cleared by a reset.
INT
Interrupt request output
INT is an open-drain output. INT is as-
serted low when any event flag is set and
the corresponding event enable bit is also
set. INT becomes high-impedance whenever
register C is read (see the Control/Status
Registers section).
Reset may be disabled by connecting RST
to VCC. This allows the control bits to re-
tain their states through power-
down/power-up cycles.
SQW
Square-wave output
X1–X2
Crystal inputs
SQW may output a programmable fre-
quency square-wave signal during normal
(VCC valid) system operation. Any one of
the 13 specific frequencies may be selected
through register A. This pin is held low
when the square-wave enable bit (SQWE)
in register B is 0 (see the Control/Status
Registers section).
The X1–X2 inputs are provided for an ex-
ternal 32.768Khz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci-
tance. A trimming capacitor may be neces-
sary for extremely precise time-base gen-
eration.
In the absence of a crystal, an oscillated
output of 32.768kHz can be fed into the X1
input.
Jan. 1999 E
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bq3285
date period (see Figure 2). The alarm flag bit may also
be set during the update cycle.
Functional Description
The bq3285 copies the local register updates into the
user buffer accessed by the host processor. When a 1 is
written to the update transfer inhibit bit (UTI) in regis-
ter B, the user copy of the clock and calendar bytes re-
mains unchanged, while the local copy of the same bytes
continues to be updated every second.
Address Map
The bq3285 provides 14 bytes of clock and control/status
registers and 114 bytes of general nonvolatile storage.
Figure 1 illustrates the address map for the bq3285.
The update-in-progress bit (UIP) in register A is set
tBUC time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.
Update Period
The update period for the bq3285 is one second. The
bq3285 updates the contents of the clock and calendar
locations during the update cycle at the end of each up-
0
00
0
1
2
3
Seconds
Seconds Alarm
Minutes
00
01
Clock and
Control Status
Registers
14
Bytes
13
14
0D
0E
02
03
Minutes Alarm
Hours
04
05
4
5
BCD or
Binary
Format
Hours Alarm
6
7
8
Day of Week
Day of Month
Month
06
07
08
114
Bytes
Storage
Registers
Year
09
0A
0B
9
10
11
Register A
Register B
12
13
Register C
Register D
0C
0D
127
7F
Figure 1. Address Map
Update Period
(1s)
UIP
t
(Update Cycle)
UC
tBUC
Figure 2. Update Period Timing and UIP
Jan. 1999 E
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bq3285
c.
Write the appropriate value to the hour
format (HF) bit.
Programming the RTC
The time-of-day, alarm, and calendar bytes can be writ-
ten in either the BCD or binary format (see Table 2).
2. Write new values to all the time, alarm, and
calendar locations.
3. Clear the UTI bit to allow update transfers.
These steps may be followed to program the time, alarm,
and calendar:
On the next update cycle, the RTC updates all 10 bytes
in the selected format.
1. Modify the contents of register B:
a. Write a 1 to the UTI bit to prevent trans-
fers between RTC bytes and user buffer.
b. Write the appropriate value to the data
format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.
Table 2. Time, Alarm, and Calendar Formats
Range
Decimal
0–59
Binary
Binary-Coded Decimal
00H–59H
Address
RTC Bytes
0
1
2
3
Seconds
00H–3BH
00H–3BH
00H–3BH
00H–3BH
Seconds alarm
Minutes
0–59
00H–59H
0–59
00H–59H
Minutes alarm
0–59
00H–59H
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
Hours, 12-hour format
Hours, 24-hour format
Hours alarm, 12-hour format
1–12
0–23
4
5
00H–17H
00H–23H
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
1–12
Hours alarm, 24-hour format
Day of week (1=Sunday)
Day of month
0–23
1–7
00H–17H
01H–07H
01H–1FH
01H–0CH
00H–63H
00H–23H
01H–07H
01H–31H
01H–12H
00H–99H
6
7
8
9
1–31
1–12
0–99
Month
Year
Jan. 1999 E
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bq3285
n
The update-ended interrupt, which occurs at the end
of each update cycle
Square-Wave Output
The bq3285 divides the 32.768kHz oscillator frequency
to produce the 1Hz update frequency for the clock and
calendar. Thirteen taps from the frequency divider are
fed to a 16:1 multiplexer circuit. The output of this mux
is fed to the SQW output and periodic interrupt genera-
tion circuitry. The four least-significant bits of register
A, RS0–RS3, select among the 13 taps (see Table 3). The
square-wave output is enabled by writing a 1 to the
square-wave enable bit (SQWE) in register B.
Each of the three interrupt events is enabled by an indi-
vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre-
sponding event enable bit is also set, then an interrupt
request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT high-impedance.
Two methods can be used to process bq3285 interrupt
events:
Interrupts
n
n
Enable interrupt events and use the interrupt request
output to invoke an interrupt service routine.
The bq3285 allows three individually selected interrupt
events to generate an interrupt request. These three in-
terrupt events are:
Do not enable the interrupts and use a polling routine
to periodically check the status of the flag bits.
n
n
The periodic interrupt, programmable to occur once
The individual interrupt sources are described in detail
in the following sections.
every 122µs to 500ms
The alarm interrupt, programmable to occur once per
second to once per day
Table 3. Square-Wave Frequency/Periodic Interrupt Rate
Register A Bits
RS2 RS1
Square Wave
Periodic Interrupt
RS3
0
RS0
0
Frequency
None
256
128
8.192
Units
Period
None
Units
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
Hz
Hz
3.90625
7.8125
122.070
244.141
488.281
976.5625
1.95315
3.90625
7.8125
15.625
31.25
ms
ms
µs
0
0
0
1
kHz
kHz
kHz
kHz
Hz
0
0
4.096
2.048
1.024
µs
0
1
µs
0
0
µs
0
1
512
ms
ms
ms
ms
ms
ms
ms
ms
ms
1
0
256
128
64
32
16
8
Hz
1
1
Hz
1
0
Hz
1
1
Hz
1
0
Hz
62.5
1
1
Hz
125
1
0
4
Hz
250
1
1
2
Hz
500
Jan. 1999 E
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bq3285
Periodic Interrupt
Update Cycle Interrupt
The mux output used to drive the SQW output also
drives the interrupt-generation circuitry. If the periodic
interrupt event is enabled by writing a 1 to the periodic
interrupt enable bit (PIE) in register C, an interrupt re-
quest is generated once every 122µs to 500ms. The pe-
riod between interrupts is selected by the same bits in
register A that select the square wave frequency (see Ta-
ble 3).
The update cycle ended flag bit (UF) in register C is set
to a 1 at the end of an update cycle. If the update inter-
rupt enable bit (UIE) of register B is 1, and the update
transfer inhibit bit (UTI) in register B is 0, then an in-
terrupt request is generated at the end of each update
cycle.
Accessing RTC bytes
Alarm Interrupt
Time and calendar bytes read during an update cycle
may be in error. Three methods to access the time and
calendar bytes without ambiguity are:
During each update cycle, the RTC compares the hours,
minutes, and seconds bytes with the three corresponding
alarm bytes. If a match of all bytes is found, the alarm
interrupt event flag bit, AF in register C, is set to 1. If
the alarm event is enabled, an interrupt request is gen-
erated.
n
Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).
An alarm byte may be removed from the comparison by
setting it to a “don’t care” state. An alarm byte is set to
a “don’t care” state by writing a 1 to each of its two
most-significant bits. A “don’t care” state may be used to
select the frequency of alarm interrupt events as follows:
n
n
Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of tBUC
time to access the clock bytes (see Figure 3).
Use the periodic interrupt event to generate
interrupt requests every tPI time, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler has a minimum of tPI/2 + tBUC
time to access the clock bytes (see Figure 3).
n
n
n
n
If none of the three alarm bytes is “don’t care,” the
frequency is once per day, when hours, minutes, and
seconds match.
If only the hour alarm byte is “don’t care,” the
frequency is once per hour, when minutes and
seconds match.
Oscillator Control
If only the hour and minute alarm bytes are “don’t
care,” the frequency is once per minute, when seconds
match.
When power is first applied to the bq3285 and VCC is
above VPFD, the internal oscillator and frequency divider
are turned on by writing a 010 pattern to bits 4 through
6 of register A. A pattern of 11X turns the oscillator on,
but keeps the frequency divider disabled. Any other pat-
tern to these bits keeps the oscillator off.
If the hour, minute, and second alarm bytes are
“don’t care,” the frequency is once per second.
Figure 3. Update-Ended/Periodic Interrupt Relationship
Jan. 1999 E
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bq3285
RS0–RS3 - Frequency Select
Power-Down/Power-Up Cycle
7
-
6
-
5
-
4
-
3
2
1
0
The bq3285 continuously monitors VCC for out-of-
tolerance. During a power failure, when VCC falls below
VPFD (4.17V typical), the bq3285 write-protects the clock
and storage registers. When VCC is below VBC (3V typi-
cal), the power source is switched to BC. RTC operation
and storage data are sustained by a valid backup energy
RS3 RS2 RS1 RS0
These bits select one of the 13 frequencies for the SQW out-
put and the periodic interrupt rate, as shown in Table 3.
OS0–OS2 - Oscillator Control
source. When VCC is above VBC, the power source is VCC
Write-protection continues for tCSR time after VCC rises
above VPFD
.
7
-
6
5
4
3
-
2
-
1
-
0
-
.
OS2 OS1 OS0
Control/Status Registers
These three bits control the state of the oscillator and
divider stages. A pattern of 010 enables RTC operation
by turning on the oscillator and enabling the frequency
divider. A pattern of 11X turns the oscillator on, but
keeps the frequency divider disabled. When 010 is writ-
ten, the RTC begins its first update after 500ms.
The four control/status registers of the bq3285 are acces-
sible regardless of the status of the update cycle (see Ta-
ble 4).
Register A
UIP - Update Cycle Status
Register A Bits
7
6
5
4
3
2
1
0
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UIP OS2 OS1 OS0
RS3
RS2 RS1 RS0
UIP
Register A programs:
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
n
n
The frequency of the square-wave and the periodic
event rate.
Oscillator operation.
Register A provides:
n
Status of the update cycle.
Table 4. Control/Status Registers
Bit Name and State on Reset
Loc.
Reg. (Hex) Read Write 7 (MSB)
6
5
4
3
2
1
0 (LSB)
A
B
C
D
0A
0B
0C
0D
Yes Yes1 UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na
Yes
Yes
Yes
Yes UTI na PIE
0
0
0
AIE
AF
-
0
0
0
UIE
UF
-
0
0
0
SQWE
0
0
0
DF na HF na DSE na
No INTF
0
PF
-
-
-
-
-
0
0
-
-
0
0
-
-
0
0
No VRT na
Notes:
1. Except bit 7.
2. na = not affected
Jan. 1999 E
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bq3285
SQWE - Square-Wave Enable
Register B
7
-
6
-
5
-
4
-
3
2
-
1
-
0
-
Register B Bits
SQWE
7
6
5
4
3
2
1
0
UTI PIE AIE UIE SQWE DF
HF DSE
This bit enables the square-wave output:
1 = Enabled
Register B enables:
0 = Disabled and held low
n
n
n
n
Update cycle transfer operation
Square-wave output
UIE - Update Cycle Interrupt Enable
Interrupt events
7
-
6
-
5
-
4
3
-
2
-
1
-
0
-
Daylight saving adjustment
UIE
Register B selects:
Clock and calendar data formats
This bit enables an interrupt request due to an update
ended interrupt event:
n
All bits of register B are read/write.
1 = Enabled
0 = Disabled
DSE - Daylight Saving Enable
The UIE bit is automatically cleared when the UTI bit
equals 1.
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
DSE
AIE - Alarm Interrupt Enable
This bit enables daylight-saving time adjustments when
written to 1:
This bit enables an interrupt request due to an alarm
7
6
5
4
3
2
1
0
n
On the last Sunday in October, the first time the
bq3285 increments past 1:59:59 AM, the time falls
back to 1:00:00 AM.
-
-
AIE
-
-
-
-
-
interrupt event:
1 = Enabled
n
On the first Sunday in April, the time springs
forward from 2:00:00 AM to 3:00:00 AM.
0 = Disabled
HF - Hour Format
PIE - Periodic Interrupt Enable
This bit enables an interrupt request due to a periodic
7
-
6
-
5
-
4
-
3
-
2
-
1
0
-
HF
7
-
6
5
-
4
-
3
-
2
-
1
-
0
-
This bit selects the time-of-day and alarm hour format:
1 = 24-hour format
PIE
0 = 12-hour format
interrupt event:
1 = Enabled
DF - Data Format
0 = Disabled
7
-
6
-
5
-
4
-
3
-
2
1
-
0
-
DF
This bit selects the numeric format in which the time,
alarm, and calendar bytes are represented:
1 = Binary
0 = BCD
Jan. 1999 E
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bq3285
UTI - Update Transfer Inhibit
This bit is set to a 1 every tPI time, where tPI is the time
period selected by the settings of RS0–RS3 in register A.
Reading register C clears this bit.
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UTI
INTF - Interrupt Request Flag
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
This bit inhibits the transfer of RTC bytes to the user
buffer:
INTF
1 = Inhibits transfer and clears UIE
0 = Allows transfer
This flag is set to a 1 when any of the following is true:
AIE = 1 and AF = 1
PIE = 1 and PF = 1
Register C
UIE = 1 and UF = 1
Register C Bits
Reading register C clears this bit.
7
6
5
4
3
0
2
0
1
0
0
0
INTF PF
AF
UF
Register D
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register C is the read-only event status register.
VRT
Bits 0–3 - Unused Bits
Register D is the read-only data integrity status regis-
ter.
7
-
6
-
5
-
4
-
3
0
2
0
1
0
0
0
Bits 0–6 - Unused Bits
These bits are always set to 0.
7
-
6
0
5
0
4
0
3
0
2
0
1
0
0
0
UF - Update Event Flag
7
-
6
-
5
-
4
3
-
2
-
1
-
0
-
These bits are always set to 0.
UF
VRT - Valid RAM and Time
This bit is set to a 1 at the end of the update cycle.
Reading register C clears this bit.
Register D Bits
AF - Alarm Event Flag
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
VRT
7
-
6
-
5
4
-
3
-
2
-
1
-
0
-
AF
1 = Valid backup energy source
0 = Backup energy source is depleted
This bit is set to a 1 when an alarm event occurs. Read-
ing register C clears this bit.
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.
PF - Periodic Event Flag
7
-
6
5
-
4
-
3
-
2
-
1
-
0
-
PF
Jan. 1999 E
10
bq3285
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
V
T ≤ VCC + 0.3
-0.3 to 7.0
V
TOPR
TSTG
TBIAS
Operating temperature
Storage temperature
Temperature under bias
0 to +70
-55 to +125
-40 to +85
260
°C
°C
°C
°C
Commercial
TSOLDER Soldering temperature
For 10 seconds
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (TA = TOPR
)
Symbol
VCC
Parameter
Supply voltage
Minimum
Typical
Maximum
Unit
V
4.5
0
5.0
5.5
0
VSS
VIL
VIH
VBC
Supply voltage
0
-
V
Input low voltage
Input high voltage
Backup cell voltage
-0.3
2.2
2.5
0.8
V
-
VCC + 0.3
4.0
V
-
V
Note:
Typical values indicate operation at TA = 25°C.
Jan. 1999 E
11
bq3285
DC Electrical Characteristics (TA = TOPR, VCC = 5V ± 10%)
Symbol
Parameter
Minimum Typical Maximum
Unit
Conditions/Notes
VIN = VSS to VCC
ILI
Input leakage current
-
-
± 1
µA
AD0–AD7, INT, and SQW
in high impedance,
VOUT = VSS to VCC
µA
ILO
Output leakage current
-
-
± 1
VOH
VOL
Output high voltage
Output low voltage
2.4
-
-
-
-
V
V
IOH = -2.0 mA
0.4
IOL = 4.0 mA
Min. cycle, duty = 100%,
ICC
Operating supply current
-
7
15
mA
I
OH = 0mA, IOL = 0mA
VSO
Supply switch-over voltage
Battery operation current
Power-fail-detect voltage
Input current when RCL = VSS
-
VBC
0.3
4.17
-
-
V
µA
V
ICCB
VPFD
IRCL
IMOTH
-
4.0
-
0.5
VBC = 3V, TA = 25°C
4.35
185
-185
.
µA
µA
Internal 30K pull-up
Input current when MOT = VCC
-
-
Internal 30K pull-down
Notes:
Typical values indicate operation at TA = 25°C, VCC = 5V or VBC = 3V.
Crystal Specifications (DT-26 or Equivalent)
Symbol
Parameter
Oscillation frequency
Minimum
Typical
Maximum
Unit
fO
-
32.768
-
kHz
pF
CL
TP
Load capacitance
-
6
-
30
-0.042
-
Temperature turnover point
Parabolic curvature constant
Quality factor
20
25
°C
k
-
-
ppm/°C
Q
40,000
70,000
R1
Series resistance
-
-
-
-
-
-
1.1
430
-
45
1.8
600
1
KΩ
C0
Shunt capacitance
Capacitance ratio
pF
C0/C1
DL
∆f/fO
Drive level
µW
Aging (first year at 25°C)
1
-
ppm
Jan. 1999 E
12
bq3285
Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
CI/O
CIN
Parameter
Input/output capacitance
Input capacitance
Minimum
Typical
Maximum
Unit
pF
Conditions
VOUT = 0V
VIN = 0V
-
-
-
-
7
5
pF
AC Test Conditions
Parameter
Test Conditions
0 to 3.0 V
5 ns
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figures 4 and 5
Figure 4. Output Load A
Figure 5. Output Load B
Jan. 1999 E
13
bq3285
Read/Write Timing (TA = TOPR, VCC = 5V ± 10%)
Symbol
tCYC
tDSL
tDSH
tRWH
tRWS
tCS
Parameter
Minimum
Typical
Maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle time
160
80
55
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS low or RD/WR high time
DS high or RD/WR low time
R/W hold time
-
-
R/W setup time
10
5
-
Chip select setup time
Chip select hold time
Read data hold time
Write data hold time
Address setup time
Address hold time
-
tCH
0
-
tDHR
tDHW
tAS
0
25
-
0
20
5
-
tAH
-
tDAS
tASW
Delay time, DS to AS rise
Pulse width, AS high
10
30
-
-
Delay time, AS to DS rise (RD/WR
fall)
tASD
tOD
35
-
-
-
-
ns
ns
Output data delay time from DS rise
(RD fall)
50
tDW
tBUC
tPI
Write data setup time
30
-
-
244
-
-
-
-
-
ns
µs
-
Delay time before update cycle
Periodic interrupt time interval
Time of update cycle
-
See Table 3
tUC
-
1
µs
Jan. 1999 E
14
bq3285
Motorola Bus Read/Write Timing
Jan. 1999 E
15
bq3285
Intel Bus Read Timing
Intel Bus Write Timing
Jan. 1999 E
16
bq3285
Power-Down/Power-Up Timing (TA = TOPR
)
Symbol
Parameter
Minimum
300
Typical
Maximum
Unit
µs
Conditions
tF
tR
VCC slew from 4.5V to 0V
VCC slew from 0V to 4.5V
-
-
-
-
100
µs
Internal write-protection
period after VCC passes VPFD
on power-up.
tCSR
CS at VIH after power-up
20
-
200
ms
Power-Down/Power-Up Timing
Jan. 1999 E
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bq3285
Interrupt Delay Timing (TA = TOPR
)
Symbol
tRSW
Parameter
Reset pulse width
Minimum
Typical
Maximum
Unit
µs
5
-
-
-
-
-
tIRR
INT release from RST
2
2
µs
tIRD
INT release from DS (RD)
-
µs
Interrupt Delay Timing
Jan. 1999 E
18
bq3285
24-Pin DIP (P)
24-Pin DIP (P)
Dimension
Minimum
0.160
0.015
0.015
0.045
0.008
1.240
0.600
0.530
0.600
0.090
0.115
0.070
Maximum
0.190
0.040
0.022
0.065
0.013
1.280
0.625
0.570
0.670
0.110
0.150
0.090
A
A1
B
B1
C
D
E
E1
e
G
L
S
All dimensions are in inches.
24-Pin SOIC (S)
24-Pin SOIC (S)
Dimension
Minimum
0.095
0.004
0.013
0.008
0.600
0.290
0.045
0.395
0.020
Maximum
0.105
0.012
0.020
0.013
0.615
0.305
0.055
0.415
0.040
A
A1
B
C
D
E
e
H
L
All dimensions are in inches.
Jan. 1999 E
19
bq3285
28-Pin Quad PLCC (Q)
28-Pin Quad PLCC (Q)
Dimension
Minimum
0.165
0.020
0.012
0.025
0.008
0.485
0.445
0.390
0.485
0.445
0.390
0.045
Maximum
0.180
-
A
A1
B
0.021
0.033
0.012
0.495
0.455
0.430
0.495
0.455
0.430
0.055
B1
C
D
D1
D2
E
E1
E2
e
All dimensions are in inches.
Data Sheet Revision History
Change No.
Page No.
Description
Address strobe input
Nature of Change
Clarification
1
1
2
11
Backup cell voltage VBC
Was 2.0 min; is 2.5 min
Was 4.1 min, 4.25 max;
is 4.0 min, 4.35 max
Power-fail detect voltage VPFD
1
12
2
3
3, 12
12
Crystal type Daiwa DT-26 (not DT-26S)
Changed value in first table
Clarification
IRCL max. was 275; is now 185
I
MOTH max. was -275; is now
3
12
Changed value in first table
-185
3
4
12
Changed values for conditions of IRCL, IMOTH
PLCC last time buy and Reg A update
Was 20K; is now 30K
Reg A labeling corrected
1, 8, 20
Notes:
Change 1 = Nov. 1992 B changes from June 1991 A.
Change 2 = Nov. 1993 C changes from Nov. 1992 B.
Change 3 = Sept. 1996 D changes from Nov. 1993 C
Change 4 = Jan. 1999 E changes from Sept. 1996 D
Jan. 1999 E
20
bq3285
Ordering Information
bq3285
-
Temperature:
blank = Commercial (0 to +70°C)
Package Option:
P = 24-pin plastic DIP (0.600)
S = 24-pin SOIC (0.300)
Q = 28-pin quad PLCC—Last time buy
Device:
bq3285 Real-Time Clock with 114 bytes of
general storage
Jan. 1999 E
21
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Copyright 1999, Texas Instruments Incorporated
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