BQ3285L [TI]
Y2K-Enhanced Real-Time Clock (RTC); Y2K增强型实时时钟（ RTC ）
| 型号： | BQ3285L |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Y2K-Enhanced Real-Time Clock (RTC) |
| 文件： | 总22页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq3285LF
Y2K-Enhanced
(
)
Real-Time Clock RTC
General Description
The bq3285LF write-protects the
clock, calendar, and storage registers
during power failure. A backup
battery then maintains data and oper-
ates the clock and calendar.
Features
The CMOS bq3285LF is a low-power
microprocessor peripheral providing
a time-of-day clock and 100-year cal-
endar with alarm features and bat-
tery operation. The architecture is
based on the bq3285 RTC with added
features: century bit, low-voltage op-
eration, 32.768kHz output, 126 addi-
tional bytes of CMOS, two shadow
registers of last address used, and a
day-of-month alarm to be compliant
with the ACPI RTC specification.
➤ ACPI-compliant day-of-month
alarm
➤ Y2K century bit
The bq3285LF is a fully compatible
real-time clock for IBM AT-
compatible computers and other ap-
plications. The only external compo-
nents are a 32.768kHz crystal and a
backup battery.
➤ Direct clock/calendar replace-
ment for IBM® AT-compatible
computers and other applications
➤ 2 index shadow registers
➤ 2.7–5.5V operation
The bq3285LF is intended for use in
3V systems; however, it may also op-
erate at 5V and then go into a 3V
power-down state, write-protecting
as if in a 3V system.
➤ 240 bytes of general nonvolatile
storage
A 32.768kHz output is available for
sustaining power-management ac-
tivities. The bq3285LF 32kHz out-
put is always on whenever VCC is
valid. In VCC standby mode, the
32kHz is active, and the bq3285LF
typically draws 100µA. Wake-up ca-
pability is provided by an alarm in-
terrupt, which is active in battery-
backup mode. In battery-backup
mode, current drain is less than
550nA.
➤ Dedicated 32.768kHz output pin
➤ System wake-up capability—
alarm interrupt output active in
battery-backup mode
➤ Less than 0.55µA load under bat-
tery operation
➤ Selectable Intel or Motorola bus
timing
➤ 24-pin plastic SSOP
Pin Connections
Pin Names
AD0–AD7 Multiplexed address/
data input/output
32K
32.768kHz output
EXTRAM Extended RAM enable
MOT
CS
Bus type select input
Chip select input
Address strobe input
Data strobe input
Read/write input
Interrupt request output
Reset input
MOT
24
1
V
CC
32k
EXTRAM
RCL
BC
RAM clear input
3V backup cell input
Crystal inputs
X1
X2
23
22
2
3
4
RCL
BC
AD
AD
AD
AD
AD
AD
AD
21
20
19
18
17
16
15
14
13
0
1
2
3
4
5
6
AS
5
X1–X2
VCC
6
INT
RST
DS
DS
7
Supply voltage input
Ground
8
9
R/W
INT
RST
V
SS
VSS
10
11
12
R/W
AS
CS
AD
7
V
SS
24-Pin SSOP
PN3285ED/LD.eps
6/99 B
1
bq3285LF
Block Diagram
X
X
1
Time-
Base
Oscillator
÷ 8
÷ 64
÷ 64
2
3
4
16 1 MUX
:
32K
INT
RST
32K
Driver
Control/Status
Registers
MOT
CS
Interupt
Generator
R/W
AS
AD –AD
0
Clock/Calendar, Alarm
and Control Bytes
µ
Bus
I/F
P
7
User Buffer
(14 Bytes)
DS
MUX
Control/Calendar
Update
EXTRAM
Storage Registers
(114 Bytes)
RCL
Storage Registers
(126 Bytes)
CS
Index Registers
(2 Bytes)
V
V
Power-
Fail
Control
CC
OUT
BC
Write
Protect
BD3285ID.eps
AD0–AD7 Multiplexed address/data
input/output
Pin Descriptions
MOT
Bus type select input
The bq3285LF bus cycle consists of two
phases: the address phase and the
data-transfer phase. The address phase
precedes the data-transfer phase. During
the address phase, an address placed on
AD0–AD7 is latched into the bq3285LF on
the falling edge of the AS signal. During
the data-transfer phase of the bus cycle, the
AD0–AD7 pins serve as a bidirectional data
bus.
MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to VCC for Motorola timing or to VSS for
Intel timing (see Table 1). The setting
should not be changed during system opera-
tion. MOT is internally pulled low by a 30K
Ω resistor.
Table 1. Bus Setup
AS
Address strobe input
Bus
Type
MOT
DS
R/W
AS
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD0–AD7. This demultiplexing pro-
cess is independent of the CS signal. For
Level Equivalent Equivalent Equivalent
DS, E, or
VCC
VSS
Motorola
R/W
WR,
AS
Φ2
DIP and SOIC packages with MOT = VSS
,
the AS input is provided a signal similar to
ALE in an Intel-based system.
RD,
Intel
MEMR, or MEMW, or ALE
I/OR
I/OW
2
bq3285LF
A low input on EXTRAM during the falling
edge of AS latches the address into
standard bank address latch. A high input
on the EXTRAM input during the falling
edge of AS latches the address into the
extended bank address latch. The contents
of the address latches are copied into the
standard bank index and the extended bank
index registers respectively. EXTRAM is not
latched.
INT
Interrupt request output
INT is an open-drain output. This allows
alarm INT to be valid in battery-backup
mode. To use this feature, connect INT
through a resistor to a power supply other
than VCC. INT is asserted low when any
event flag is set and the corresponding event
enable bit is also set. INT becomes
high-impedance whenever register C is read
(see the Control/Status Registers section).
DS
Data strobe input
32K
32.768 kHz output
When MOT = VCC, DS controls data trans-
fer during a bq3285LF bus cycle. During a
read cycle, the bq3285LF drives the bus af-
ter the rising edge on DS. During a write
cycle, the falling edge on DS is used to latch
write data into the chip.
32K provides a buffered 32.768 kHz output.
The frequency remains on and fixed at
32.768kHz as long as VCC is valid.
EXTRAM Extended RAM enable
Enables 128 bytes of additional nonvolatile
When MOT = VSS, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
SRAM. It is connected internally to a 30kΩ
pull-down resistor. To access the RTC reg-
isters, EXTRAM must be low.
The input on this pin also selects the latch
to be used in the data transfer. A low value
selects the standard bank latch. A high
value selects the extended the bank latch.
EXTRAM should be valid for complete ad-
dress, read or write cycle.
The state of the EXTRAM input selects the
address latch used during data access. A
low input on EXTRAM selects the standard
bank latch and the location in the standard
bank pointed to by the value in this latch. A
high input on the EXTRAM selects the ex-
tended bank latch and the location in the
extended bank pointed to by the value in
this latch.
RCL
RAM clear input
A low level on the RCL pin causes the con-
tents of each of the 240 storage bytes to be
set to FF(hex). RCL clears the shadow in-
dex registers to 00(hex). The contents of the
clock and control registers are unaffected.
This pin should be used as a user-interface
input (pushbutton to ground) and not con-
nected to the output of any active compo-
nent. RCL input is only recognized when
held low for at least 125ms in the presence
of VCC. Using RAM clear does not affect the
battery load. This pin is connected inter-
nally to a 30kΩ pull-up resistor.
Read/write input
R/W
When MOT = VCC, the level on R/W identi-
fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
When MOT = VSS, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel-
based system. The rising edge on R/W
latches data into the bq3285LF.
BC
3V backup cell input
CS
Chip select input
BC should be connected to a 3V backup cell
for RTC operation and storage register
nonvolatility in the absence of system power.
When VCC slews down past VBC (3V typical),
the integral control circuitry switches the
power source to BC. When VCC returns above
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq3285LF.
VBC, the power source is switched to VCC
.
On power-up, a voltage within the VBC
range must be present on the BC pin for
the oscillator to start up.
3
bq3285LF
RST
Reset input
Functional Description
The bq3285LF is reset when RST is pulled
low. When reset, INT becomes high impedance,
and the bq3285LF is not accessible. Table 4 in
the Control/Status Registers section lists the
register bits that are cleared by a reset.
Address Map
The bq3285LF provides 14 bytes of clock and con-
trol/status registers and 242 bytes of general nonvolatile
storage. Figure 1 illustrates the address map for the
bq3285LF.
Reset may be disabled by connecting RST to
VCC. This allows the control bits to retain
their states through power-down/power-up
cycles.
Update Period
X1–X2
Crystal inputs
The update period for the bq3285LF is one second. The
bq3285LF updates the contents of the clock and calen-
dar locations during the update cycle at the end of each
update period (see Figure 2). The alarm flag bit may
also be set during the update cycle.
The X1–X2 inputs are provided for an exter-
nal 32.768kHz quartz crystal, Daiwa DT-26
or equivalent, with 6pF load capacitance. A
trimming capacitor may be necessary for
extremely precise time-base generation.
The bq3285LF copies the local register updates into the
user buffer accessed by the host processor. When a 1 is
written to the update transfer inhibit bit (UTI) in regis-
ter B, the user copy of the clock and calendar bytes re-
In the absence of a crystal, a 32.768kHz
waveform can be fed into the X1 input.
0
00
0
1
00
Seconds Alarm 01
Seconds
Clock and
Control Status
Registers
14 Bytes
13
14
0D
0E
Minutes
Minutes Alarm
Hours
2
02
03
04
05
3
Storage
Registers
with
BCD
or
Binary
Format
114
Bytes
4
Hours Alarm
5
EXTRAM = 0
6
Day of Week 06
Date of Month 07
127
0
7F
00
7
8
08
09
0A
0B
0C
0D
Month
Year
Storage
Registers
with
9
126
Bytes
10
11
12
13
Register A
EXTRAM = 1
Register B
Register C
Day of Month
Alarm
125
126
127
7D
7E
7F
Index
Registers
2
Standard Index Register
Bytes
Extended Index Register
plus Century bit
FG3285ID.eps
Figure 1. Address Map
Update Period
(1 sec.)
UIP
tUC
(Update Cycle)
tBUC
TD3285e1.eps
Figure 2. Update Period Timing and UIP
4
bq3285LF
a. Write a 1 to the UTI bit to prevent trans-
mains unchanged, while the local copy of the same bytes
continues to be updated every second.
fers between RTC bytes and user buffer.
b. Write the appropriate value to the data
format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.
The update-in-progress bit (UIP) in register A is set tBUC
time before the beginning of an update cycle (see Figure
2). This bit is cleared and the update-complete flag (UF)
is set at the end of the update cycle.
c.
Write the appropriate value to the hour
format (HF) bit.
Programming the RTC
2. Write new values to all the time, alarm, and
calendar locations.
The time-of-day, alarm, and calendar bytes can be writ-
ten in either the BCD or binary format (see Table 2).
3. The CENT bit in location 7Fh (bit 7) of the ex-
tended SRAM bank is read only. Writing year
in location 09h automatically updates CENT.
These steps may be followed to program the time, alarm,
and calendar:
4. Clear the UTI bit to allow update transfers.
1. Modify the contents of register B:
Table 2. Time, Alarm, Calendar, and Index Formats
Range
Binary-Coded
Decimal
Decimal
0–59
Binary
Address
RTC Bytes
0
1
2
3
Seconds
00H–3BH
00H–3BH
00H–3BH
00H–3BH
00H–59H
00H–59H
00H–59H
00H–59H
Seconds alarm
Minutes
0–59
0–59
Minutes alarm
0–59
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
Hours, 12-hour format
Hours, 24-hour format
1–12
0–23
4
5
00H–17H
00H–23H
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
Hours alarm, 12-hour format
1–12
Hours alarm, 24-hour format
Day of week (1=Sunday)
Day of month
0–23
1–7
00H–17H
01H–07H
01H–1FH
01H–0CH
00H–63H
01H-1FH
00H–23H
01H–07H
01H–31H
01H–12H
00H–99H
01–31H
6
7
1–31
1–12
0–99
1–31
8
Month
9
Year (see note)
D
Day of month alarm
Note:
Century for “Year” is shown in location 7Fh (Extended Index Register, bit 7) .
5
bq3285LF
On the next update cycle, the RTC updates all 10 bytes
in the selected format.
Each of the three interrupt events is enabled by an indi-
vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre-
sponding event enable bit is also set, then an interrupt
request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT high-impedance.
32kHz Output
The bq3285LF provides for a 32.768kHz output, and the
output is always active whenever VCC is valid (VPFD
+
tCSR). The bq3285LF output is not affected by the bit
settings in Register A. Time-keeping aspects, however,
still require setting OS0-OS2.
Two methods can be used to process bq3285LF interrupt
events:
n
n
Enable interrupt events and use the interrupt
request output to invoke an interrupt service routine.
Interrupts
Do not enable the interrupts and use a polling routine
to periodically check the status of the flag bits.
The bq3285LF allows three individually selected inter-
rupt events to generate an interrupt request. These
three interrupt events are:
The individual interrupt sources are described in detail
in the following sections.
n
n
The periodic interrupt, programmable to occur once
every 122µs to 500ms.
Periodic Interrupt
The alarm interrupt, programmable to occur once per
second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.
If the periodic interrupt event is enabled by writing a 1
to the periodic interrupt enable bit (PIE) in register C,
an interrupt request is generated once every 122µs to
500ms. The period between interrupts is selected with
bits RS3-RS0 in register A (see Table 3).
n
The update-ended interrupt, which occurs at the end
of each update cycle.
Table 3. Periodic Interrupt Rate
Register A Bits
Periodic Interrupt
Period Units
None
3.90625
OSC2
OSC1
OSC0
RS3
0
RS2
0
RS1
0
RS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
ms
ms
µs
0
0
1
0
7.8125
122.070
244.141
488.281
976.5625
1.95315
3.90625
7.8125
15.625
31.25
0
0
1
1
0
1
0
0
µs
0
1
0
1
µs
0
1
1
0
µs
0
1
1
1
ms
ms
ms
ms
ms
ms
ms
ms
ms
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
62.5
1
1
0
1
125
1
1
1
0
250
1
1
1
1
500
same as above defined
by RS3–RS0
0
1
1
X
X
X
X
6
bq3285LF
inhibit bit (UTI) in register B is 0, then an interrupt re-
quest is generated at the end of each update cycle.
Alarm Interrupt
The alarm interrupt is active in battery-backup mode,
providing a “wake-up” capability. During each update
cycle, the RTC compares the day-of-the-month, hours,
minutes, and seconds bytes with the four corresponding
alarm bytes. If a match of all bytes is found, the alarm
interrupt event flag bit, AF in register C, is set to 1. If
the alarm event is enabled, an interrupt request is gen-
erated.
Accessing RTC bytes
The EXTRAM pin must be low to access the RTC regis-
ters. Time and calendar bytes read during an update
cycle may be in error. Three methods to access the time
and calendar bytes without ambiguity are:
n
Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).
An alarm byte may be removed from the comparison by
setting it to a “don't care” state. The seconds, minutes,
and hours alarm bytes are set to a “don't care” state by
writing a 1 to each of its two most-significant bits. The
day-of-the-month alarm byte is set to a “don’t care” state
by setting DA5–DA0, in register D, to all zeros. A “don't
care” state may be used to select the frequency of alarm
interrupt events as follows:
n
n
Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of tBUC
time to access the clock bytes (see Figure 3).
n
n
n
n
n
If none of the four alarm bytes is “don't care,” the
frequency is once per month, when day-of-the-month,
hours, minutes, and seconds match.
Use the periodic interrupt event to generate
interrupt requests every tPI time, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler has a minimum of tPI/2 + tBUC
time to access the clock bytes (see Figure 3).
If only the day-of-the-month alarm byte is “don’t
care”, the frequency is once per day, when hours,
minutes, and seconds match.
Oscillator Control
If only the day-of-the-month and hour alarm byte is
“don't care,” the frequency is once per hour, when
minutes and seconds match.
When power is first applied to the bq3285LF and VCC is
above VPFD, the internal oscillator and frequency divider
are turned on by writing a 010 pattern to bits 4 through
6 of register A. A pattern of 11X turns the oscillator on
but keeps the frequency divider disabled. Any other pat-
tern to these bits keeps the oscillator off. A pattern of
010 must be set for the bq3285LF to keep time in bat-
tery backup mode.
If only the day-of-the-month, hour and minute alarm
bytes are “don't care,” the frequency is once per
minute, when seconds match.
If the day-of-the-month, hour, minute, and second
alarm bytes are “don't care,” the frequency is once per
second.
Update Cycle Interrupt
Power-Down/Power-Up Cycle
The update cycle ended flag bit (UF) in register C is set to
a 1 at the end of an update cycle. If the update interrupt
enable bit (UIE) of register B is 1, and the update transfer
The bq3285LF continuously monitors VCC for out-of-
tolerance. During a power failure, when VCC falls below
1 Sec.
UIP
t
UC
(t )/2
Pl
(t )/2
Pl
t
t
BUC
Pl
PF
UF
T3285L02.eps
Figure 3. Update-Ended/Periodic Interrupt Relationship
7
bq3285LF
VPFD (2.53V typical), the bq3285LF write-protects the RS0–RS3 - Frequency Select
clock and storage registers. The power source is switched
to BC when VCC is less than VPFD and BC is greater than
VPFD, or when VCC is less than VBC and VBC is less than
VPFD. RTC operation and storage data are sustained by a
valid backup energy source. When VCC is above VPFD, the
power source is VCC. Write-protection continues for tCSR
7
-
6
-
5
-
4
-
3
2
1
0
RS3 RS2 RS1 RS0
These bits select the periodic interrupt rate, as shown in
Table 3.
time after VCC rises above VPFD
.
OS0–OS2 - Oscillator Control
Control/Status Registers
7
-
6
5
4
3
-
2
-
1
-
0
-
The four control/status registers of the bq3285LF are ac-
cessible regardless of the status of the update cycle (see
Table 4).
OS2 OS1 OS0
These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC op-
eration by turning on the oscillator and enabling the fre-
quency divider. This pattern must be set to turn the os-
cillator on and to ensure that the bq3285LF keeps time
in battery-backup mode. A pattern of 11X turns the os-
cillator on, but keeps the frequency divider disabled.
When 010 is written, the RTC begins its first update af-
ter 500ms.
Register A
Register A Bits
7
6
5
4
3
2
1
0
UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0
Register A programs:
UIP - Update Cycle Status
n
n
n
The frequency of the periodic event rate.
Oscillator operation.
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UIP
Time-keeping
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
Register A provides:
n
Status of the update cycle.
Table 4. Control/Status/Index Registers
Bit Name and State on Reset
Loc.
Reg. (Hex) Read Write
7 (MSB)
6
5
4
3
2
1
0 (LSB)
A
B
0A
0B
0C
0D
7E
7F
Yes Yes1 UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na
Yes Yes UTI na PIE
0
0
0
0
0
AIE
AF
0
0
UIE
UF
0
0
-
-
0
0
DF na HF na DSE na
na
C
Yes No INTF
Yes Yes2 VRT na
0
PF
-
-
-
0
-
0
D
DA5 na DA4 na DA3 na DA2 na DA1 na DA0 na
SI
EI
Yes No NMI
Yes No CENT
0
0
SI6
EI6
SI5
EI5
0
0
SI4
EI4
0
0
SI3
EI3
0
0
SI2
EI2
0
0
SI1
EI1
0
0
SI0
EI0
0
0
Notes:
na = not affected.
x = unknown
1. Except bit 7.
2. Except bits 6 and 7.
8
bq3285LF
Register B
UIE - Update Cycle Interrupt Enable
Register B Bits
7
-
6
-
5
-
4
3
-
2
-
1
-
0
-
7
6
5
4
3
-
2
1
0
UIE
UTI PIE AIE UIE
DF
HF DSE
This bit enables an interrupt request due to an update
ended interrupt event:
Register B enables:
n
n
n
Update cycle transfer operation
Interrupt events
1 = Enabled
0 = Disabled
Daylight saving adjustment
The UIE bit is automatically cleared when the UTI bit
equals 1.
Register B selects:
Clock and calendar data formats
AIE - Alarm Interrupt Enable
n
All bits of register B are read/write.
7
-
6
-
5
4
-
3
-
2
-
1
-
0
-
AIE
Bit 3 is unused.
This bit enables an interrupt request due to an alarm
interrupt event:
DSE - Daylight Saving Enable
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
1 = Enabled
0 = Disabled
DSE
This bit enables daylight-saving time adjustments when
written to 1:
PIE - Periodic Interrupt Enable
n
On the last Sunday in October, the first time the
bq3285LF increments past 1:59:59 AM, the time falls
back to 1:00:00 AM.
7
-
6
5
-
4
-
3
-
2
-
1
-
0
-
PIE
This bit enables an interrupt request due to a periodic
interrupt event:
n
On the first Sunday in April, the time springs
forward from 2:00:00 AM to 3:00:00 AM.
1 = Enabled
0 = Disabled
HF - Hour Format
7
-
6
-
5
-
4
-
3
-
2
-
1
0
-
UTI - Update Transfer Inhibit
HF
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
This bit selects the time-of-day and alarm hour format:
UTI
1 = 24-hour format
0 = 12-hour format
This bit inhibits the transfer of RTC bytes to the user
buffer:
DF - Data Format
1 = Inhibits transfer and clears UIE
0 = Allows transfer
7
-
6
-
5
-
4
-
3
-
2
1
-
0
-
DF
Register C
This bit selects the numeric format in which the time,
alarm, and calendar bytes are represented:
Register C Bits
7
6
5
4
3
0
2
-
1
0
0
0
1 = Binary
0 = BCD
INTF PF
AF
UF
Register C is the read-only event status register.
9
bq3285LF
Bits 0, 1, 2, 3 - Unused Bits
Bits 6 - Unused Bit
7
-
6
-
5
-
4
-
3
0
2
-
1
0
0
0
7
-
6
0
5
-
4
-
3
-
2
-
1
-
0
-
These bits are always set to 0.
This bit is always set to 0.
UF - Update Event Flag
VRT - Valid RAM and Time
7
-
6
-
5
-
4
3
-
2
-
1
-
0
-
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UF
VRT
This bit is set to a 1 at the end of the update cycle.
Reading register C clears this bit.
1 = Valid backup energy source
0 = Backup energy source is depleted
AF - Alarm Event Flag
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.
7
-
6
-
5
4
-
3
-
2
-
1
-
0
-
AF
DA0–DA5
This bit is set to a 1 when an alarm event occurs. Read-
ing register C clears this bit.
7
-
6
-
5
4
3
2
1
0
DA5 DA4 DA3 DA2 DA1 DA0
PF - Periodic Event Flag
These bits store the value for the day-of-the-month
alarm. If DA0–DA5 are set to zero, then the day-of-the-
month alarm is disabled . These bits are not affected by
a reset.
7
-
6
5
-
4
-
3
-
2
-
1
-
0
-
PF
This bit is set to a 1 every tPI time, where tPI is the time
period selected by the settings of RS0–RS3 in register A.
Reading register C clears this bit.
Standard Bank Index
7
6
5
4
3
2
1
0
INTF - Interrupt Request Flag
NMI SI6
SI5
SI4
SI3
SI2
SI1
SI0
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
This register contains a copy of the last index value used
for the standard bank of SRAM, and non-maskable in-
terrupt, and is read only.
INTF
This flag is set to a 1 when any of the following is true:
AIE = 1 and AF = 1
Extended Bank Index
PIE = 1 and PF = 1
7
6
5
4
3
2
1
0
CENT EI6 EI5 EI4
EI3
EI2 EI1 EI0
UIE = 1 and UF = 1
This register contains a copy of the last index value used
for the extended bank of SRAM and century bit. For
years 80–90, set CENT = 1. For years 00–79, set CENT
= 0.
Reading register C clears this bit.
Register D
Register D Bits
7
6
0
5
4
3
2
1
0
VRT
DA5 DA4 DA3 DA2 DA1 DA0
Register D provides for the read-only data integrity
status bit, and the day-of-the-month alarm.
10
bq3285LF
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
V
T ≤ VCC + 0.3
-0.3 to 7.0
V
TOPR
TSTG
TBIAS
Operating temperature
Storage temperature
Temperature under bias
0 to +70
-55 to +125
-40 to +85
260
°C
°C
°C
°C
Commercial
TSOLDER Soldering temperature
For 10 seconds
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (TA = TOPR, VCC = 3V unless otherwise noted)
Symbol
Parameter
Supply voltage
Minimum
2.7
Typical
Maximum
Unit
V
Notes
VCC
VSS
VIL
3.0
5.5
0
Supply voltage
0
0
-
V
Input low voltage
-0.3
2.2
0.6
V
-
VCC + 0.3
V
VIH
Input high voltage
Backup cell voltage
2.8
-
VCC + 0.3
4.0
V
VCC = 5V
VBC
2.4
-
V
Note:
Typical values indicate operation at TA = 25°C.
Crystal Specifications (DT-26 or Equivalent)
Symbol
Parameter
Oscillation frequency
Minimum
Typical
Maximum
Unit
kHz
pF
fO
-
32.768
-
CL
TP
Load capacitance
-
6
-
30
-0.042
-
Temperature turnover point
Parabolic curvature constant
Quality factor
20
25
°C
k
-
-
ppm/°C
Q
40,000
70,000
R1
Series resistance
-
-
-
-
-
-
1.1
430
-
45
1.8
600
1
KΩ
C0
Shunt capacitance
Capacitance ratio
pF
C0/C1
DL
∆f/fO
Drive level
µW
Aging (first year at 25°C)
1
-
ppm
11
bq3285LF
DC Electrical Characteristics (TA = TOPR, VCC = 3V)
Symbol
ILI
Parameter
Minimum Typical1 Maximum Unit
Conditions/Notes
Input leakage current
-
-
-
-
± 1
± 1
µA VIN = VSS to VCC
AD0–AD7 and INT in high
impedance,
VOUT = VSS to VCC
µA
ILO
Output leakage current
VOH
VOL
Output high voltage
Output low voltage
2.2
-
-
-
-
V
V
IOH = -1.0 mA
0.4
IOL = 2.0 mA
Min. cycle, duty = 100%,
OH = 0mA, IOL = 0mA
ICC
Operating supply current
Standby supply current
-
-
52
9
-
mA
I
V
IN = VSS or VCC
,
1003
µA
ICCSB
CS ≥ VCC - 0.2
VBC > VPFD
VBC < VPFD
-
-
VPFD
VBC
-
-
V
V
VSO
Supply switch-over voltage
VBC = 3V, TA = 25°C,
VCC < VBC
µA
ICCB
Battery operation current
Power-fail-detect voltage
-
0.4
0.55
VPFD
IRCL
2.4
2.53
2.65
120
-120
0
V
Input current when RCL = VSS
Input current when MOT = VCC
Input current when MOT = VSS
Input current when EXTRAM = VCC
Input current when EXTRAM = VSS
.
-
-
-
-
-
-
-
-
-
-
µA Internal 30K pull-up
µA Internal 30K pull-down
µA Internal 30K pull-down
µA Internal 30K pull-down
µA Internal 30K pull-down
IMOTH
-120
0
IXTRAM
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 3V.
2. 7mA at VCC = 5V
3. 300µA at VCC = 5V
12
bq3285LF
Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
CI/O
Parameter
Minimum
Typical
Maximum
Unit
pF
Conditions
Input/output capacitance
Input capacitance
-
-
-
-
7
5
VOUT = 0V
VIN = 0V
CIN
pF
Note:
This parameter is sampled and not 100% tested. It does not include the X1 or X2 pin.
AC Test Conditions
Parameter
Test Conditions
0 to 2.3 V, VCC = 3V
5 ns
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
1.2 V (unless otherwise specified)
See Figures 6 and 7
+3.3V
+3.3V
1238
1.45k
For all outputs
except INT
INT
130pF
1164
50pF
Figure 6. Output Load
Figure 7. Output Load B
13
bq3285LF
Read/Write Timing (TA = TOPR, VCC = 3V)
Symbol
tCYC
tDSL
tDSH
tRWH
tRWS
tCS
Parameter
Minimum
Typical
Maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle time
285
135
90
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS low or RD/WR high time
DS high or RD/WR low time
R/W hold time
-
-
R/W setup time
15
8
-
Chip select setup time
Chip select hold time
Read data hold time
-
tCH
0
-
tDHR
tDHW
tAS
0
40
-
Write data hold time
Address setup time
0
30
15
30
50
55
-
tAH
Address hold time
-
tDAS
tASW
tASD
Delay time, DS to AS rise
Pulse width, AS high
Delay time, AS to DS rise (RD/WR fall)
-
-
-
Output data delay time from DS rise
(RD fall)
tOD
-
-
100
ns
tDW
tBUC
tPI
Write data setup time
50
-
-
-
-
-
-
-
ns
µs
-
Delay time before update cycle
Periodic interrupt time interval
Time of update cycle
244
-
-
1
-
See Table 3
tUC
-
µs
ns
tEXT
EXTRAM input setup and hold time
15
14
bq3285LF
Motorola Bus Read/Write Timing
EXTRAM
tEXT
tEXT
tASW
AS
tDAS
tASD
tCYC
DS
tDSL
tDSH
tRWS
tRWH
R/W
tCS
tCH
CS
tAH
tAS
tDW
tDHW
AD0 -AD7
(WRITE)
tOD
tAS
tDHR
tAH
AD0 -AD7
(READ)
T3285LF3.eps
15
bq3285LF
Intel Bus Read Timing
tCYC
EXTRAM
AS (ALE)
tEXT
tASW
tASD
tEXT
DS (RD)
tDSH
tDSL
R/W (WR)
CS
tCS
tOD
tCH
tDAS
tAS
tAH
tDHR
AD0 -AD7
T3285LF4.eps
Intel Bus Write Timing
tCYC
EXTRAM
AS (ALE)
tEXT
tEXT
tASW
tASD
tDAS
DS (RD)
R/W (WR)
CS
tDSL
tDSH
tCS
tCH
tAS
tAH
AD0 -AD
tDW
tDHW
T3285LF5.eps
16
bq3285LF
Power-Down/Power-Up Timing (TA = TOPR
)
Symbol
Parameter
Minimum
300
Typical
Maximum
Unit
µs
Conditions
tF
tR
VCC slew from 2.7V to 0V
VCC slew from 0V to 2.7V
-
-
-
-
100
µs
Internal write-protection
period after VCC passes VPFD
on power-up.
tCSR
CS at VIH after power-up
20
-
200
ms
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
tF
tR
2.7
VPFD
2.7
VPFD
VCC
VSO
VSO
tCSR
CS
INT
(Alarm)
T3285L06.eps
17
bq3285LF
Interrupt Delay Timing (TA = TOPR
)
Symbol
tRSW
Parameter
Reset pulse width
Minimum
Typical
Maximum
Unit
µs
5
-
-
-
-
-
tIRR
INT release from RST
INT release from DS
2
2
µs
tIRD
-
µs
Interrupt Delay Timing
RD (Intel)
DS (Mot)
tRSW
RST
INT
tIRD
tIRR
T3285L07.eps
18
bq3285LF
24-Pin SSOP (SS)
(
)
24-Pin SS 0.150" SSOP
Inches
Millimeters
Min.
0.061
0.004
0.008
0.007
0.337
0.150
Max.
0.068
0.010
0.012
0.010
0.344
0.157
Min.
1.55
0.10
0.20
0.18
8.56
3.81
Max.
1.73
0.25
0.30
0.25
8.74
3.99
Dimension
A
A1
B
C
D
E
e
.025 BSC
0.64 BSC
H
L
0.230
0.016
0.244
0.035
5.84
0.41
6.20
0.89
Data Sheet Revision History
ChangeNo.
Page No.
Description of Change
“Final” changes from “Preliminary”
1
All
Notes:
Change 1 = June 1999 B “Final” changes from April 1999 “Preliminary.”
Ordering Information
bq3285LF
-
Temperature:
blank = Commercial (0 to +70°C)
Package Option:
SS= 24-pin SSOP (0.150)
Device:
bq3285LF Real-Time Clock with 240
bytes of general storage
19
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jul-2005
PACKAGING INFORMATION
Orderable Device
BQ3285LFSS-A1
BQ3285LFSS-A1TR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
24
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
DBQ
24
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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