BQ3285ESSTR_技术文档

bq3285E/L

Real-Time Clock (RTC)

➤ BCD or binary format for clock

Features

General Description

and calendar data

➤ Direct clock/calendar replace-

ment for IBM^®AT-compatible

computers and other applications

Th e CMOS bq3285E /L is a low-

power m icr opr ocessor per iph er a l

providing a time-of-day clock and

100-year calendar with alarm fea-

t ures a nd ba t t ery opera t ion . Th e

b q3 28 5 L s u p p or t s 3 V s ys t e m s.

Other bq3285E/L features include

three maskable interrupt sources,

square-wave output, and 242 bytes

of general nonvolatile storage.

➤ Calendar in day of the week, day

of the month, months, and years,

with automatic leap-year adjust-

ment

➤ Functionally compatible with the

DS1285

➤ Time of day in seconds, minutes,

and hours

- ^{Closely matches MC146818A}

pin configuration

- ^{12- or 24-hour format}

- ^{Optional daylight saving}

➤ 2.7–3.6V operation (bq3285L);

adjustment

4.5–5.5V operation (bq3285E)

A 32.768kHz output is available for

sustaining power-management ac-

tivities. Wake-up capability is pro-

vided by an alarm interrupt, which

is active in battery-backup mode.

➤ Programmable square wave out-

➤ 242 bytes of general nonvolatile

put

storage

➤ Three individually maskable in-

➤ 32.768kHz output for power man-

terrupt event flags:

agement

- ^{Periodic rates from 122}^µ^{s to}

The bq3285E/L write-protects the

clock, calendar, and storage registers

du r in g power fa ilu r e. A ba cku p

battery then maintains data and oper-

ates the clock and calendar.

➤ System wake-up capability—

alarm interrupt output active in

battery-backup mode

500ms

- ^{Time-of-day alarm once per}

second to once per day

➤ Less than 0.5µA load under bat-

- End-of-clock update cycle

➤ 24-pin plastic DIP, SOIC, or

tery operation

The bq3285E/L is a fully compatible

real-time clock for IBM AT-compatible

computers and other applications.

The only external components are a

32.768kHz crystal and a backup bat-

tery.

➤ Selectable Intel or Motorola bus

SSOP

timing

➤ 14 bytes for clock/calendar and

control

Pin Connections

Pin Names

AD₀–AD₇Multiplexed address/

data input/output

RST

Reset input

SQW

Square wave output

MOT

24

1

V

CC

SQW

EXTRAM

MOT

CS

Bus type select input

Chip select input

Address strobe input

Data strobe input

Read/write input

Interrupt request

output

EXTRAM Extended RAM enable

X1

X2

23

22

2

3

RCL

BC

RAM clear input

3V backup cell input

Crystal inputs

Power supply

Ground

4

RCL

BC

AD

0

AD

1

AD

2

AD

3

AD

4

AD

5

AD

6

21

20

19

18

AS

5

6

INT

RST

DS

X1–X2

V_CC

7

R/W

INT

8

9

17 DS

16

15

V

SS

R/W

V_SS

10

11

12

AD

7

14 AS

13 CS

V

SS

24-Pin DIP or SOIC/SSOP

PN3285E1.eps

SLUS004A -DECEMBER 1993 - REVISED MAY 2004

1

bq3285E/L

Block Diagram

AD₀–AD₇Mu ltiplexed addr ess/data in pu t/

Pin Descriptions

ou tpu t

MOT

Bu s typ e select in p u t

The bq3285E/L bus cycle consists of two

phases: the address phase and the data-

transfer phase. The address phase pre-

cedes the data-transfer phase. During the

a d d r es s p h a s e, a n a d d r es s p la ced on

AD₀–AD₇and EXTRAM is latched into the

bq3285E/L on the falling edge of the AS sig-

nal. During the data-transfer phase of the

bus cycle, the AD₀–AD₇pins serve as a bidi-

rectional data bus.

MOT selects bus timing for either Motorola

or Intel architecture. This pin should be

tied to V_CCfor Motorola timing or to V_SSfor

Intel timing (see Table 1). The setting

should not be changed during system opera-

tion. MOT is internally pulled low by a

30KΩ resistor.

Table 1. Bus Setup

AS

Ad d r ess str obe in p u t

Bus

Type

MOT

DS

R/W

AS

AS serves to demultiplex the address/data

bus. The falling edge of AS latches the ad-

dress on AD₀–AD₇and EXTRAM. This de-

multiplexing process is independent of the

CS signal. For DIP and SOIC packages with

MOT = V_SS, the AS input is provided a signal

similar to ALE in an Intel-based system.

Level Equivalent Equivalent Equivalent

DS, E, or

V_CC

Motorola

R/W

WR,

AS

Φ2

RD,

V_SS

Intel

MEMR, or MEMW, or ALE

I/OR I/OW

2

bq3285E/L

DS

Da ta str obe in p u t

EXTRAM Exten d ed RAM en a ble

When MOT = V_CC, DS controls data trans-

fer during a bq3285E/L bus cycle. During a

read cycle, the bq3285E/L drives the bus af-

ter the rising edge on DS. During a write

cycle, the falling edge on DS is used to latch

write data into the chip.

Enables 128 bytes of additional nonvolatile

SRAM. It is connected internally to a 30K

Ω pull-down resistor. To access the RTC

registers, EXTRAM must be low.

RCL

RAM clea r in p u t

A low level on the RCL pin causes the con-

tents of each of the 242 storage bytes to be

set to FF(hex). The contents of the clock

and control registers are unaffected. This

pin should be used as a user-interface input

(pushbutton to ground) and not connected

to the output of any active component. RCL

input is only recognized when held low for

at least 125ms in the presence of V_CC. Us-

ing RAM clear does not affect the battery

load. This pin is connected internally to a

30KΩ pull-up resistor.

When MOT = V_SS, the DS input is provided

a signal similar to RD, MEMR, or I/OR in

an Intel-based system. The falling edge on

DS is used to enable the outputs during a

read cycle.

Read/wr ite in pu t

R/W

When MOT = V_CC, the level on R/W identi-

fies the direction of data transfer. A high

level on R/W indicates a read bus cycle,

whereas a low on this pin indicates a write

bus cycle.

BC

3V ba ck u p cell in p u t

When MOT = V_SS, R/W is provided a sig-

nal similar to WR, MEMW, or I/OW in an

Intel-based system. The rising edge on

R/W latches data into the bq3285E/L.

BC should be connected to a 3V backup cell

for RTC operation and storage register non-

volatility in the absence of system power.

When V_CCslews down past V_BC(3V typical),

the integral control circuitry switches the

power source to BC. When V_CCreturns

above V_BC, the power source is switched to

CS

Ch ip select in p u t

CS should be driven low and held stable

during the data-transfer phase of a bus cy-

cle accessing the bq3285E/L.

V_CC

.

Upon power-up, a voltage within the V_BC

range must be present on the BC pin for

the oscillator to start up.

INT

In ter r u p t r equ est ou tp u t

INT is an open-drain output. This allows

alarm INT to be valid in battery-backup

mode. To use this feature, INT must be con-

RST

Reset in p u t

nected to a power supply other than V_CC

.

The bq3285E/L is reset when RST is pulled

low. When reset, INT becomes high imped-

ance, and the bq3285E/L is not accessible.

Table 4 in the Control/Status Registers sec-

tion lists the register bits that are cleared

by a reset.

INT is asserted low when any event flag is

set and the corresponding event enable bit

is also set. INT becomes high-impedance

whenever register C is read (see the Con-

trol/Status Registers section).

SQW

Squ a r e-w a ve ou tp u t

Reset may be disabled by connecting RST

to V_CC

. This allows the control bits to re-

SQW m a y ou t pu t a pr ogr a m m a ble fr e-

quency square-wave signal during normal

(V_CCvalid) system operation. Any one of

the 13 specific frequencies may be selected

through register A. This pin is held low

when the square-wave enable bit (SQWE)

in register B is 0 (see the Control/Status

Registers section).

t a in t h e ir s t a t e s t h r ou gh p ow e r -

down/power-up cycles.

X1–X2

Cr ysta l in p u ts

The X1–X2 inputs are provided for an exter-

nal 32.768kHz quartz crystal, Daiwa DT-26

or equivalent, with 6pF load capacitance. A

trimming capacitor may be necessary for ex-

tremely precise time-base generation.

A 32.768kHz output is enabled by setting

the SQWE bit in register B to 1 and the

32KE bit in register C to 1 after setting

OSC2–OSC0 in register A to 011 (binary).

In the absence of a crystal, a 32.768kHz

waveform can be fed into the X1 input.

3

bq3285E/L

dar locations during the update cycle at the end of each

update period (see Figure 2). The alarm flag bit may

also be set during the update cycle.

Functional Description

Address Map

The bq3285E/L copies the local register updates into the

user buffer accessed by the host processor. When a 1 is

written to the update transfer inhibit bit (UTI) in regis-

ter B, the user copy of the clock and calendar bytes re-

mains unchanged, while the local copy of the same bytes

continues to be updated every second.

The bq3285E/L provides 14 bytes of clock and con-

trol/status registers and 242 bytes of general nonvolatile

storage. Figure 1 illustrates the address map for the

bq3285E/L.

The update-in-progress bit (UIP) in register A is set

t_BUCtime before the beginning of an update cycle (see

Figure 2). This bit is cleared and the update-complete

flag (UF) is set at the end of the update cycle.

Update Period

The update period for the bq3285E/L is one second. The

bq3285E/L updates the contents of the clock and calen-

Figure 1. Address Map

Figure 2. Update Period Timing and UIP

4

bq3285E/L

c.

Write the appropriate value to the hour

format (HF) bit.

Programming the RTC

The time-of-day, alarm, and calendar bytes can be writ-

ten in either the BCD or binary format (see Table 2).

2. Write new values to all the time, alarm, and

calendar locations.

3. Clear the UTI bit to allow update transfers.

These steps may be followed to program the time, alarm,

and calendar:

On the next update cycle, the RTC updates all 10 bytes

in the selected format.

1. Modify the contents of register B:

a. Write a 1 to the UTI bit to prevent trans-

fers between RTC bytes and user buffer.

b. Write the appropriate value to the data

format (DF) bit to select BCD or binary

format for all time, alarm, and calendar

bytes.

Table 2. Time, Alarm, and Calendar Formats

Range

Binary-Coded

Decimal

0–59

Binary

Address

RTC Bytes

0

1

2

3

Seconds

00H–3BH

00H–59H

Seconds alarm

Minutes

0–59

Minutes alarm

0–59

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours, 12-hour format

Hours, 24-hour format

Hours alarm, 12-hour format

1–12

0–23

4

5

00H–17H

00H–23H

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

1–12

Hours alarm, 24-hour format

Day of week (1=Sunday)

Day of month

0–23

1–7

00H–17H

01H–07H

01H–1FH

01H–0CH

00H–63H

00H–23H

01H–07H

01H–31H

01H–12H

00H–99H

6

7

8

9

1–31

1–12

0–99

Month

Year

5

bq3285E/L

n

The alarm interrupt, programmable to occur once per

second to once per day, is active in battery-backup

mode, providing a “wake-up” feature.

Square-Wave Output

The bq3285E/L divides the 32.768kHz oscillator fre-

quency to produce the 1Hz update frequency for the

clock and calendar. Thirteen taps from the frequency di-

vider are fed to a 16:1 multiplexer circuit. The output of

this mux is fed to the SQW output and periodic inter-

rupt generation circuitry. The four least-significant bits

of register A, RS0–RS3, select among the 13 taps (see

Table 3). The square-wave output is enabled by writing

a 1 to the square-wave enable bit (SQWE) in register B.

A 32.768k H z ou t p u t m a y be s elect ed by s et t in g

OSC2–OSC0 in register A to 011 while SQWE = 1 and

32KE = 1.

The update-ended interrupt, which occurs at the end

of each update cycle.

Each of the three interrupt events is enabled by an indi-

vidual interrupt-enable bit in register B. When an event

occurs, its event flag bit in register C is set. If the corre-

sponding event enable bit is also set, then an interrupt

request is generated. The interrupt request flag bit

(INTF) of register C is set with every interrupt request.

Reading register C clears all flag bits, including INTF,

and makes INT high-impedance.

Two methods can be used to process bq3285E/L interrupt

events:

Interrupts

n

Enable interrupt events and use the interrupt request

output to invoke an interrupt service routine.

The bq3285E/L allows three individually selected inter-

rupt events to generate an interrupt request. These

three interrupt events are:

Do not enable the interrupts and use a polling routine

to periodically check the status of the flag bits.

n

The periodic interrupt, programmable to occur once

every 122µs to 500ms.

The individual interrupt sources are described in detail

in the following sections.

Table 3. Square-Wave Frequency/Periodic Interrupt Rate

Register A Bits

Square Wave

Periodic Interrupt

OSC2 OSC1 OSC0

RS3

0

RS2

RS1

0

RS0

0

Frequency

None

256

128

8.192

Units

Period

Units

0

1

0

1

0

1

None

0

1

Hz

3.90625

ms

µs

0

1

0

7.8125

122.070

244.141

488.281

976.5625

1.95315

3.90625

7.8125

15.625

31.25

0

1

kHz

Hz

0

4.096

2.048

1.024

µs

0

1

µs

0

1

0

µs

0

1

512

ms

1

0

256

128

64

32

16

8

Hz

1

0

1

Hz

1

0

Hz

1

Hz

1

0

Hz

62.5

1

0

1

Hz

125

1

0

4

Hz

250

1

2

Hz

500

32.768

same as above defined

by RS3–RS0

0

1

X

kHz

6

bq3285E/L

Periodic Interrupt

Update Cycle Interrupt

The mux output used to drive the SQW output also

drives the interrupt-generation circuitry. If the periodic

interrupt event is enabled by writing a 1 to the periodic

interrupt enable bit (PIE) in register C, an interrupt re-

quest is generated once every 122µs to 500ms. The pe-

riod between interrupts is selected by the same bits in

register A that select the square wave frequency (see Ta-

ble 3). Setting OSC2–OSC0 in register A to 011 does not

affect the periodic interrupt timing.

The update cycle ended flag bit (UF) in register C is set to

a 1 at the end of an update cycle. If the update interrupt

enable bit (UIE) of register B is 1, and the update transfer

inhibit bit (UTI) in register B is 0, then an interrupt request

is generated at the end of each update cycle.

Accessing RTC bytes

The EXTRAM pin must be low to access the RTC regis-

ters. Time and calendar bytes read during an update

cycle may be in error. Three methods to access the time

and calendar bytes without ambiguity are:

Alarm Interrupt

The alarm interrupt is active in battery-backup mode,

providing a “wake-up” capability. During each update

cycle, the RTC compares the hours, minutes, and sec-

onds bytes with the three corresponding alarm bytes. If

a match of all bytes is found, the alarm interrupt event

flag bit, AF in register C, is set to 1. If the alarm event

is enabled, an interrupt request is generated.

n

Enable the update interrupt event to generate

interrupt requests at the end of the update cycle. The

interrupt handler has a maximum of 999ms to access

the clock bytes before the next update cycle begins (see

Figure 3).

n

Poll the update-in-progress bit (UIP) in register A. If

UIP = 0, the polling routine has a minimum of t_BUC

time to access the clock bytes (see Figure 3).

An alarm byte may be removed from the comparison by

setting it to a “don’t care” state. An alarm byte is set to

a “don’t care” state by writing a 1 to each of its two

most-significant bits. A “don’t care” state may be used to

select the frequency of alarm interrupt events as follows:

Use the periodic interrupt event to generate

interrupt requests every t_PItime, such that UIP = 1

always occurs between the periodic interrupts. The

interrupt handler has a minimum of t_PI/2 + t_BUC

time to access the clock bytes (see Figure 3).

n

If none of the three alarm bytes is “don’t care,” the

frequency is once per day, when hours, minutes, and

seconds match.

If only the hour alarm byte is “don’t care,” the

frequency is once per hour, when minutes and

seconds match.

Oscillator Control

When power is first applied to the bq3285E/L and V_CCis

above V_PFD, the internal oscillator and frequency divider

are turned on by writing a 010 pattern to bits 4 through 6

of register A. A pattern of 011 behaves as 010 but addition-

ally transforms register C into a read/write register. This

allows the 32.768kHz output on the square wave pin to be

turned on. A pattern of 11X turns the oscillator on, but

keeps the frequency divider disabled. Any other pattern to

these bits keeps the oscillator off.

If only the hour and minute alarm bytes are “don’t

care,” the frequency is once per minute, when seconds

match.

If the hour, minute, and second alarm bytes are

“don’t care,” the frequency is once per second.

Figure 3. Update-Ended/Periodic Interrupt Relationship

7

bq3285E/L

Register A provides:

Status of the update cycle.

Power-Down/Power-Up Cycle

n

The bq3285E and bq3285L power-up/power-down cycles are

different. The bq3285L continuously monitors V_CCfor out-of-

tolerance. During a power failure, when V_CCfalls below V_PFD

(2.53V typical), the bq3285L write-protects the clock and stor-

age registers. The power source is switched to BC when V_CCis

less than V_PFDand BC is greater than V_PFD, or when V_CCis

less than V_BCand V_BCis less than V_PFD. RTC operation and

storage data are sustained by a valid backup energy source.

When V_CCis above V_PFD, the power source is V_CC. Write-

RS0–RS3 - Frequency Select

7

-

6

-

5

-

4

-

3

2

1

0

RS3 RS2 RS1 RS0

These bits select one of the 13 frequencies for the SQW out-

put and the periodic interrupt rate, as shown in Table 3.

protection continues for t_CSRtime after V_CCrises above V_PFD

.

OS0–OS2 - Oscillator Control

The bq3285E continuously monitors V_CCfor out-of-tolerance.

During a power failure, when V_CCfalls below V_PFD(4.17V

typical), the bq3285E write-protects the clock and storage

registers. When V_CCis below V_BC(3V typical), the power

source is switched to BC. RTC operation and storage data

are sustained by a valid backup energy source. When V_CCis

above V_BC, the power source is V_CC. Write-protection contin-

7

-

6

5

4

3

-

2

-

1

-

0

-

OS2 OS1 OS0

These three bits control the state of the oscillator and

divider stages. A pattern of 010 enables RTC operation

by turning on the oscillator and enabling the frequency

divider. A pattern of 011 behaves as 010 but additionally

transforms register C into a read/write register. This al-

lows the 32.768kHz output on the square wave pin to be

turned on. A pattern of 11X turns the oscillator on, but

keeps the frequency divider disabled. When 010 is writ-

ten, the RTC begins its first update after 500ms.

ues for t_CSRtime after V_CCrises above V_PFD

.

Control/Status Registers

The four control/status registers of the bq3285E/L are

accessible regardless of the status of the update cycle

(see Table 4).

UIP - Update Cycle Status

Register A

7

6

-

5

-

4

-

3

-

2

-

1

-

0

-

UIP

Register A Bits

7

6

5

4

3

2

1

0

This read-only bit is set prior to the update cycle. When

UIP equals 1, an RTC update cycle may be in progress.

UIP is cleared at the end of each update cycle. This bit

is also cleared when the update transfer inhibit (UTI)

bit in register B is 1.

UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0

Register A programs:

n

The frequency of the square-wave and the periodic

event rate.

Oscillator operation.

Table 4. Control/Status Registers

Bit Name and State on Reset

Loc.

7 (MSB)

6

5

4

3

2

1

0 (LSB)

Reg. (Hex) Rea d Wr ite

A

0A

0B

0C

0D

Yes Yes¹UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na

B

C

Yes

Yes No²INTF

Yes No VRT na

Yes UTI na PIE

0

AIE

AF

-

0

UIE

UF

-

0

SQWE

0

DF na HF na DSE na

0

PF

-

32KE na

-

0

-

0

D

-

0

Notes:

na = not affected.

1. Except bit 7.

2. Read/write only when OSC2–OSC0 in register A is 011 (binary).

8

bq3285E/L

SQWE - Square-Wave Enable

Register B

7

-

6

-

5

-

4

-

3

2

-

1

-

0

-

Register B Bits

SQWE

7

6

5

4

3

2

1

0

UTI PIE

AIE UIE SQWE DF

HF

DSE

This bit enables the square-wave output:

1 = Enabled

Register B enables:

n

Update cycle transfer operation

Square-wave output

0 = Disabled and held low

UIE - Update Cycle Interrupt Enable

Interrupt events

7

-

6

-

5

-

4

3

-

2

-

1

-

0

-

Daylight saving adjustment

UIE

Register B selects:

Clock and calendar data formats

This bit enables an interrupt request due to an update

ended interrupt event:

n

All bits of register B are read/write.

1 = Enabled

0 = Disabled

DSE - Daylight Saving Enable

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

The UIE bit is automatically cleared when the UTI bit

equals 1.

DSE

AIE - Alarm Interrupt Enable

This bit enables daylight-saving time adjustments when

written to 1:

7

-

6

-

5

4

-

3

-

2

-

1

-

0

-

AIE

n

On the last Sunday in October, the first time the

bq3285E/L increments past 1:59:59 AM, the time

falls back to 1:00:00 AM.

This bit enables an interrupt request due to an alarm

interrupt event:

n

On the first Sunday in April, the time springs

forward from 2:00:00 AM to 3:00:00 AM.

1 = Enabled

0 = Disabled

HF - Hour Format

7

-

6

-

5

-

4

-

3

-

2

-

1

0

-

PIE - Periodic Interrupt Enable

HF

7

-

6

5

-

4

-

3

-

2

-

1

-

0

-

PIE

This bit selects the time-of-day and alarm hour format:

1 = 24-hour format

This bit enables an interrupt request due to a periodic

interrupt event:

0 = 12-hour format

1 = Enabled

0 = Disabled

DF - Data Format

7

-

6

-

5

-

4

-

3

-

2

1

-

0

-

DF

This bit selects the numeric format in which the time,

alarm, and calendar bytes are represented:

1 = Binary

0 = BCD

9

bq3285E/L

UTI - Update Transfer Inhibit

PF - Periodic Event Flag

This bit is set to a 1 every t_PItime, where t_PIis the time

period selected by the settings of RS0–RS3 in register A.

Reading register C clears this bit.

7

6

-

5

-

4

-

3

-

2

-

1

-

0

-

UTI

7

-

6

5

-

4

-

3

-

2

-

1

-

0

-

This bit inhibits the transfer of RTC bytes to the user

buffer:

PF

1 = Inhibits transfer and clears UIE

0 = Allows transfer

INTF - Interrupt Request Flag

This flag is set to a 1 when any of the following is true:

AIE = 1 and AF = 1

Register C

PIE = 1 and PF = 1

Register C is the read-only event status register.

7

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Register C Bits

INTF

7

6

5

4

3

0

2

1

0

INTF PF

AF

UF

32KE

UIE = 1 and UF = 1

Reading register C clears this bit.

Bits 0, 1, 3 - Unused Bits

These bits are always set to 0.

Register D

Register D is the read-only data integrity status register.

7

-

6

-

5

-

4

-

3

0

2

-

1

0

Bits 0–6 - Unused Bits

These bits are always set to 0.

32KE - 32kHz Enable Output

VRT - Valid RAM and Time

Register D Bits

This bit may be set to a 1 only when the OSC2–OSC0

bits in register A are set to 011. Setting OSC2–OSC0 to

7

6

0

5

0

4

0

3

0

2

0

1

0

7

-

6

-

5

-

4

-

3

-

2

1

-

0

-

VRT

32KE

1 = Valid backup energy source

0 = Backup energy source is depleted

anything other than 011 clears this bit. If SQWE in reg-

ister B and 32KE are set, a 32.768kHz waveform is out-

put on the square wave pin.

7

-

6

0

5

0

4

0

3

0

2

0

1

0

UF - Update Event Flag

This bit is set to a 1 at the end of the update cycle.

When the backup energy source is depleted (VRT = 0),

data integrity of the RTC and storage registers is not

guaranteed.

7

-

6

-

5

-

4

3

-

2

-

1

-

0

-

UF

7

6

-

5

-

4

-

3

-

2

-

1

-

0

-

VRT

Reading register C clears this bit.

AF - Alarm Event Flag

This bit is set to a 1 when an alarm event occurs. Read-

ing register C clears this bit.

7

-

6

-

5

4

-

3

-

2

-

1

-

0

-

AF

10

bq3285E/L

Absolute Maximum Ratings—bq3285E

Symbol

Parameter

Value

Unit

Conditions

V_CC

DC voltage applied on V_CCrelative to V_SS

-0.3 to 7.0

V

DC voltage applied on any pin excluding V_CC

relative to V_SS

V_T

V_T≤ V_CC+ 0.3

-0.3 to 7.0

0 to +70

V

°C

Commercial

T_OPR

Operating temperature

T_STG

Storage temperature

-55 to +125

-40 to +85

260

°C

T_BIAS

Temperature under bias

T_SOLDERSoldering temperature

For 10 seconds

Note:

Permanent device damage may occur if Absolu te Ma xim u m Ra tin gs are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-

sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

Absolute Maximum Ratings—bq3285L

Symbol

Parameter

Value

Unit

Conditions

V_CC

DC voltage applied on V_CCrelative to V_SS

-0.3 to 6.0

V

DC voltage applied on any pin excluding V_CC

relative to V_SS

V_T

V_T≤ V_CC+ 0.3

-0.3 to 6.0

V

T_OPR

T_STG

T_BIAS

Operating temperature

Storage temperature

Temperature under bias

0 to +70

-55 to +125

-40 to +85

260

°C

Commercial

T_SOLDERSoldering temperature

For 10 seconds

Note:

Permanent device damage may occur if Absolu te Ma xim u m Ra tin gs are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-

sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

11

bq3285E/L

Recommended DC Operating Conditions—bq3285E (T_A= T_OPR

)

Symbol

V_CC

Parameter

Supply voltage

Minimum

Typical

Maximum

Unit

V

4.5

0

5.0

5.5

V_SS

V_IL

V_IH

V_BC

Supply voltage

0

-

0

0.8

V

Input low voltage

Input high voltage

Backup cell voltage

-0.3

2.2

2.5

V

-

V_CC+ 0.3

4.0

V

-

V

Note:

Typical values indicate operation at T_A= 25°C.

Recommended DC Operating Conditions—bq3285L (T_A= T_OPR

)

Symbol

V_CC

Parameter

Supply voltage

Minimum

Typical

Maximum

Unit

V

2.7

0

3.15

3.6

V_SS

V_IL

V_IH

V_BC

Supply voltage

0

-

0

0.6

V

Input low voltage

Input high voltage

Backup cell voltage

-0.3

2.2

2.4

V

-

V_CC+ 0.3

4.0

V

-

V

Note:

Typical values indicate operation at T_A= 25°C.

Crystal Specifications—bq3285E/L (DT-26 or Equivalent)

Symbol

Parameter

Oscillation frequency

Minimum

Typical

Maximum

Unit

f_O

-

32.768

-

kHz

pF

C_L

T_P

Load capacitance

-

6

-

30

Temperature turnover point

Parabolic curvature constant

Quality factor

20

25

°C

k

-

-0.042

-

ppm/°C

Q

40,000

70,000

R₁

Series resistance

-

1.1

430

-

45

KΩ

C₀

Shunt capacitance

Capacitance ratio

1.8

600

1

pF

C₀/C₁

D_L

∆f/f_O

Drive level

µW

Aging (first year at 25°C)

1

-

ppm

12

bq3285E/L

DC Electrical Characteristics—bq3285E (T_A= T_OPR, V_CC= 5V ± 10%)

Symbol

I_LI

Parameter

Minimum Typical Maximum Unit

Conditions/Notes

Input leakage current

-

± 1

µA V_IN= V_SSto V_CC

AD₀–AD₇, INT, and SQW

in high impedance,

V_OUT= V_SSto V_CC

µA

I_LO

Output leakage current

V_OH

V_OL

Output high voltage

Output low voltage

2.4

-

V

I_OH= -2.0 mA

I_OL= 4.0 mA

0.4

Min. cycle, duty = 100%,

I_OH= 0mA, I_OL= 0mA

I_CC

Operating supply current

Standby supply current

-

7

15

-

mA

V_IN= V_SSor V_CC

,

µA

I_CCSB

300

CS ≥ V_CC- 0.2

V_SO

Supply switch-over voltage

Battery operation current

Power-fail-detect voltage

Input current when RCL = V_SS

-

V_BC

-

V

I_CCB

V_PFD

I_RCL

-

4.0

-

0.3

0.5

4.35

185

-185

0

µA V_BC= 3V, T_A= 25°C

V

4.17

.

-

µA Internal 30K pull-up

µA Internal 30K pull-down

Input current when MOT = V_CC

Input current when MOT = V_SS

-

I_MOTH

-

Input current when EXTRAM =

V_CC

µA

-

-185

0

Internal 30K pull-down

I_XTRAM

Input current when EXTRAM =

V_SS

Note:

Typical values indicate operation at T_A= 25°C, V_CC= 5V or V_BC= 3V.

13

bq3285E/L

DC Electrical Characteristics—bq3285L (T_A= T_OPR, V_CC= 3.15V ±0.45V)

Symbol

I_LI

Parameter

Minimum Typical Maximum Unit

Conditions/Notes

Input leakage current

-

± 1

µA V_IN= V_SSto V_CC

AD₀–AD₇and INT in high

impedance,

µA

I_LO

Output leakage current

V_OUT= V_SSto V_CC

V_OH

V_OL

Output high voltage

Output low voltage

2.2

-

V

I_OH= -1.0 mA

I_OL= 2.0 mA

0.4

Min. cycle, duty = 100%, I_OH

= 0mA, I_OL= 0mA

I_CC

Operating supply current

Standby supply current

-

5

9

-

mA

V_IN= V_SSor V_CC

,

µA

I_CCSB

100

CS ≥ V_CC- 0.2

-

V_PFD

V_BC

-

V

V_BC> V_PFD

V_BC< V_PFD

V_SO

Supply switch-over voltage

Battery operation current

V_BC= 3V, T_A= 25°C,

V_CC< V_BC

µA

I_CCB

-

0.3

0.5

V_PFD

I_RCL

Power-fail-detect voltage

2.4

2.53

2.65

120

-120

0

V

Input current when RCL = V_SS

.

-

µA Internal 30K pull-up

µA Internal 30K pull-down

Input current when MOT = V_CC

Input current when MOT = V_SS

I_MOTH

Input current when EXTRAM =

V_CC

µA

-

-120

0

Internal 30K pull-down

I_XTRAM

Input current when EXTRAM =

V_SS

Note:

Typical values indicate operation at T_A= 25°C, V_CC= 3V.

14

bq3285E/L

Capacitance—bq3285E/L (T_A= 25°C, F = 1MHz, V_CC= 5.0V)

Symbol

C_I/O

Parameter

Input/output capacitance

Input capacitance

Minimum

Typical

Maximum

Unit

pF

Conditions

-

7

5

V_OUT= 0V

V_IN= 0V

C_IN

pF

Note:

This parameter is sampled and not 100% tested. It does not include the X1 or X2 pin.

AC Test Conditions—bq3285E

Parameter

Input pulse levels

Test Conditions

0 to 3.0 V

Input rise and fall times

5 ns

Input and output timing reference levels

Output load (including scope and jig)

1.5 V (unless otherwise specified)

See Figures 4 and 5

Figure 4. Output Load A—bq3285E

Figure 5. Output Load B—bq3285E

15

bq3285E/L

AC Test Conditions—bq3285L

Parameter

Input pulse levels

Test Conditions

0 to 2.3 V

Input rise and fall times

5 ns

Input and output timing reference levels

Output load (including scope and jig)

1.2 V (unless otherwise specified)

See Figures 6 and 7

Figure 6. Output Load A—bq3285L

Figure 7. Output Load B—bq3285L

16

bq3285E/L

Read/Write Timing—bq3285E (T_A= T_OPR, V_CC= 5V ± 10%)

Symbol

t_CYC

t_DSL

t_DSH

t_RWH

t_RWS

t_CS

Parameter

Minimum

Typical

Maximum

Unit

Notes

Cycle time

160

80

55

0

-

ns

DS low or RD/WR high time

DS high or RD/WR low time

R/W hold time

-

R/W setup time

10

5

-

Chip select setup time

Chip select hold time

Read data hold time

Write data hold time

Address setup time

Address hold time

-

t_CH

0

-

t_DHR

t_DHW

t_AS

0

25

-

0

20

5

-

t_AH

-

t_DAS

t_ASW

Delay time, DS to AS rise

Pulse width, AS high

10

30

-

Delay time, AS to DS rise (RD/WR

fall)

t_ASD

35

-

ns

Output data delay time from DS rise

(RD fall)

t_OD

50

t_DW

t_BUC

t_PI

Write data setup time

30

-

244

-

ns

µs

-

Delay time before update cycle

Periodic interrupt time interval

Time of update cycle

-

See Table 3

t_UC

-

1

µs

17

bq3285E/L

Read/Write Timing—bq3285L (T_A= T_OPR, V_CC= 3.15V ± 0.45V)

Symbol

t_CYC

t_DSL

t_DSH

t_RWH

t_RWS

t_CS

Parameter

Minimum

Typical

Maximum

Unit

ns

Notes

Cycle time

270

135

90

0

-

DS low or RD/WR high time

DS high or RD/WR low time

R/W hold time

-

R/W setup time

15

8

-

Chip select setup time

Chip select hold time

Read data hold time

Write data hold time

Address setup time

Address hold time

-

t_CH

0

-

t_DHR

t_DHW

t_AS

0

40

-

0

30

15

50

-

t_AH

-

t_DAS

t_ASW

Delay time, DS to AS rise

Pulse width, AS high

-

Delay time, AS to DS rise (RD/WR

fall)

t_ASD

t_OD

55

-

ns

Output data delay time from DS rise

(RD fall)

100

t_DW

t_BUC

t_PI

Write data setup time

50

-

244

-

ns

µs

-

Delay time before update cycle

Periodic interrupt time interval

Time of update cycle

-

See Table 3

t_UC

-

1

µs

18

bq3285E/L

Motorola Bus Read/Write Timing—bq3285E/L

19

bq3285E/L

Intel Bus Read Timing—bq3285E/L

Intel Bus Write Timing—bq3285E/L

20

bq3285E/L

Power-Down/Power-Up Timing—bq3285E (T_A= T_OPR

)

Symbol

Parameter

Minimum

300

Typical

Maximum

Unit

µs

Conditions

t_F

V_CCslew from 4.5V to 0V

V_CCslew from 0V to 4.5V

-

t_R

100

µs

Internal write-protection

period after V_CCpasses V_PFD

on power-up.

t_CSR

CS at V_IHafter power-up

20

-

200

ms

Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e

m a y a ffect d a ta in tegr ity.

Power-Down/Power-Up Timing—bq3285E

21

bq3285E/L

Power-Down/Power-Up Timing—bq3285L (T_A= T_OPR

)

Symbol

Parameter

Minimum

300

Typical

Maximum

Unit

µs

Conditions

t_F

V_CCslew from 2.7V to 0V

V_CCslew from 0V to 2.7V

-

t_R

100

µs

Internal write-protection

period after V_CCpasses V_PFD

on power-up.

t_CSR

CS at V_IHafter power-up

20

-

200

ms

Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e

m a y a ffect d a ta in tegr ity.

Power-Down/Power-Up Timing—bq3285L

22

bq3285E/L

Interrupt Delay Timing—bq3285E/L ^(T_A= T_OPR

)

Symbol

t_RSW

Parameter

Reset pulse width

Minimum

Typical

Maximum

Unit

µs

5

-

2

t_IRR

INT release from RST

INT release from DS

µs

t_IRD

-

µs

Interrupt Delay Timing—bq3285E/L

23

bq3285E/L

(

24-Pin DIP P)

(

)

24-Pin DIP 0.600" DIP

Inches

Millimeters

Min.

Max.

Min.

Max.

Dimension

A

A1

B

0.160

0.015

0.045

0.008

1.240

0.600

0.530

0.600

0.090

0.115

0.070

0.190

0.040

0.022

0.065

0.013

1.280

0.625

0.570

0.670

0.110

0.150

0.090

4.06

0.38

4.83

1.02

0.38

0.56

B1

C

1.14

1.65

0.20

0.33

D

31.50

15.24

13.46

15.24

2.29

32.51

15.88

14.48

17.02

2.79

E

E1

e

G

L

2.92

3.81

S

1.78

2.29

24-Pin SOIC (S)

(

)

24-Pin S 0.300" SOIC

Inches

Millimeters

Min.

Max.

Min.

Max.

Dimension

B

e

A

A1

B

0.095

0.004

0.013

0.008

0.600

0.290

0.045

0.395

0.020

0.105

0.012

0.020

0.013

0.615

0.305

0.055

0.415

0.040

2.41

0.10

0.33

0.20

15.24

7.37

1.14

10.03

0.51

2.67

0.30

0.51

0.33

15.62

7.75

1.40

10.54

1.02

D

C

D

E

H

e

H

L

A

C

.004

A1

L

24

bq3285E/L

24-Pin SSOP (SS)

(

)

24-Pin SS 0.150" SSOP

Inches

Millimeters

Min.

0.061

0.004

0.008

0.007

0.337

0.150

Max.

0.068

0.010

0.012

0.010

0.344

0.157

Min.

1.55

0.10

0.20

0.18

8.56

3.81

Max.

1.73

0.25

0.30

0.25

8.74

3.99

Dimension

A

A1

B

C

D

E

e

.025 BSC

0.64 BSC

H

L

0.230

0.016

0.244

0.035

5.84

0.41

6.20

0.89

25

bq3285E/L

Data Sheet Revision History

Change

No.

Page

No.

Description

Nature of Change

Was 0; is na (not affected)

1

2

3

4

8

Register C, bit 2

Output data delay time t

18

Was 80 ns max; is 100 ns max

OD

1, 24, 26 Package option change

Lst time buy for some package options.

Removed PLCC and added industrial SSOP package options

Industrial package option removed

1, 11

Package option change

Note: Change 1 = Jan. 1995 B “Final” changes from Dec. 1993 A “Preliminary”.

Change 2 = Jan. 1999 C changes from Jan. 1995 B

Change 3 = Apr. 1999 D changes from Jan. 1999 C.

Change 4 = May 2004 (SLUS004A) changes from Apr. 1999 D

26

bq3285E/L

Ordering Information

bq3285E/L

-

Tem p er a tu r e:

blank = Commercial (0 to +70°C)

Pa ck a ge Op tion :

P = 24-pin plastic DIP (0.600)

S = 24-pin SOIC (0.300)

SS= 24-pin SSOP (0.150)

Device:

bq3285E Real-Time Clock with 242

bytes of general storage

or

bq3285L Real-Time Clock with 242

bytes of general storage

(3V operation)

bq3285L only available in 24-pin SSOP (0.150).

27

PACKAGE OPTION ADDENDUM

www.ti.com

18-Feb-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

PDIP

SOIC

Drawing

BQ3285EP

BQ3285ES

BQ3285ESS

ACTIVE

N

24

15

25

50

None

A42 SNPB

CU SNPB

Level-NA-NA-NA

DW

Level-1-220C-UNLIM

SSOP/

QSOP

DBQ

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

BQ3285ESSTR

ACTIVE

SSOP/

QSOP

DBQ

24

2500

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

BQ3285ESTR

BQ3285LSS

ACTIVE

SOIC

DW

24

None

CU SNPB

Call TI

Level-1-220C-UNLIM

Call TI

OBSOLETE

SSOP/

QSOP

DBQ

BQ3285LSSTR

OBSOLETE

SSOP

DB

24

None

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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型号：	BQ3285ESSTR
厂家：	TEXAS INSTRUMENTS
描述：	Real-Time Clock RTC 实时时钟RTC 外围集成电路光电二极管时钟
文件：	总29页 (文件大小：1049K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ3285ESSTR [TI]

相关型号：

BQ3285ESSTRG4

BQ3285ESTR

BQ3285ESTRG4

BQ3285E_15

BQ3285L

BQ3285LC

BQ3285LCS

BQ3285LCSS

BQ3285LCSS-

BQ3285LCSSTR

BQ3285LD

BQ3285LDSS