ADS5541IPAP [TI]
14-Bit, 105MSPS Analog-To-Digital Converter;
| 型号： | ADS5541IPAP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-Bit, 105MSPS Analog-To-Digital Converter 转换器 |
| 文件： | 总37页 (文件大小：1536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Production Data
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SBAS307C–MAY 2004–REVISED FEBRUARY 2007
14-Bit, 105MSPS
Analog-To-Digital Converter
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
14-Bit Resolution
The ADS5541 is
a
high-performance, 14-bit,
105MSPS analog-to-digital converter (ADC). To
provide a complete converter solution, it includes a
high-bandwidth linear sample-and-hold stage (S&H)
and internal reference. Designed for applications
demanding the highest speed and highest dynamic
performance in a small space, the ADS5541 has
excellent analog power dissipation of 571mW at 3.3V
single-supply voltage. This allows an even higher
system integration density. The provided internal
reference simplifies system design requirements.
The parallel CMOS compatible outputs ensure
seamless interfacing with common logic.
105MSPS Sample Rate
High SNR: 72dBFS at 100MHz fIN
High SFDR: 86dBc at 100MHz fIN
2.3VPP Differential Input Voltage
Internal Voltage Reference
3.3V Single-Supply Voltage
Analog Power Dissipation: 571mW
Serial Programming Interface
TQFP-64 PowerPAD™ Package
Pin-Compatible With:
The ADS5541 is available in a TQFP-64 PowerPAD
package over the industrial temperature range.
–
–
–
–
–
ADS5500 (14-Bit, 125MSPS)
ADS5542 (14-Bit, 80MSPS)
ADS5520 (12-Bit, 125MSPS)
ADS5521 (12-Bit, 105MSPS)
ADS5522 (12-Bit, 80MSPS)
ADS5500 PRODUCT FAMILY
80MSPS
ADS5522
ADS5542
105MSPS
ADS5521
ADS5541
125MSPS
ADS5542
ADS5500
12-Bit
14-Bit
•
Recommended Op Amps:
–
OPA695, OPA847, THS3202, THS3201,
THS4503, THS4509, THS9001
AV
DD
DRV
DD
CLK+
CLK−
Timing Circuitry
CLKOUT
APPLICATIONS
CM
•
Wireless Communication
14-Bit
Pipeline
ADC
D0
Digital
Error
Correction
V
IN+
.
.
.
Output
Control
–
–
Communication Receivers
Base Station Infrastructure
S&H
V
IN−
D13
Core
OVR
DFS
•
•
•
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Communication Instrumentation
Internal
Reference
Control Logic
Serial Programming Register
ADS5541
A
GND
SEN
SDATA SCLK
DR
GND
–
Radar, Infrared
•
•
•
Video and Imaging
Medical Equipment
Military Equipment
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
Production Data
ADS5541
www.ti.com
SBAS307C–MAY 2004–REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT PACKAGE-LEAD(2) DESIGNATOR
ADS5541IPAP
Tray, 160
HTQFP-64
PowerPAD
ADS5541
PAP
–40°C to +85°C
ADS5541I
ADS5541IPAPR
Tape and Reel, 1000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Thermal pad size: 3.5mm × 3.5mm (min), 4mm × 4mm (max). θJA = 21.47°C/W and θJC = 2.99°C/W, when used with 2 oz. copper trace
and pad soldered directly to a JEDEC standard, four-layer, 3in × 3in PCB.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
ADS5541
UNIT
V
AVDD to AGND, DRVDD to DRGND
AGND to DRGND
–0.3 to 3.7
Supply Voltage
±0.1
–0.3 to minimum (AVDD + 0.3, +3.6)
–0.3 to DRVDD
–0.3 to DRVDD
–40 to 85
V
(2)(3)
Analog input to AGND
Logic input to DRGND
V
V
Digital data output to DRGND
Operating temperature range
Junction temperature
V
°C
°C
°C
105
Storage temperature range
–65 to 150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) If the input signal can exceed 3.6V, then a resistor greater than or equal to 25Ω should be added in series with each of the analog input
pins to support input voltages up to 3.8V. For input voltages above 3.8V, the device can only handle transients and the duty cycle of the
overshoot should be limited to less than 5% for inputs up to 3.9V.
(3) The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as a
percentage. The total time of overshoot is the integrated time of all overshoot occurences over the lifetime of the device.
2
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RECOMMENDED OPERATING CONDITIONS
ADS5541
MIN
TYP
MAX
UNIT
Supplies
Analog supply voltage, AVDD
Output driver supply voltage, DRVDD
Analog Input
3
3
3.3
3.3
3.6
3.6
V
V
Differential input range
2.3
VPP
V
(1)
Input common-mode voltage, VCM
1.45
1.55
1.65
Digital Output
Maximum output load
Clock Input
10
pF
DLL ON
ADCLK input sample rate (sine wave) 1/tC
DLL OFF
60
2
105
80
MSPS
VPP
Clock amplitude, sine wave, differential(2)
Clock duty cycle(3)
1
3
50%
Open free-air temperature range
–40
85
°C
(1) Input common-mode should be connected to CM.
(2) See Figure 49 for more information.
(3) See Figure 48 for more information.
ELECTRICAL CHARACTERISTICS
At TA = +25°C, min and max specified over the full temperature range of –40°C to +85°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS,
50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted.
ADS5541
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
Bits
Analog Inputs
Differential input range
2.3
6.6
4
VPP
Differential input impedance
Differential input capacitance
Analog input common-mode current (per input)
Analog input bandwidth
See Figure 39
See Figure 39
kΩ
pF
250
750
4
µA
Source impedance = 50Ω
MHz
Voltage overload recovery time
Internal Reference Voltages
Reference bottom voltage, VREFM
Reference top voltage, VREFP
Reference error
Clock cycles
0.95
2.1
V
V
–4
±0.9
1.55
4
%
V
Common-mode voltage output, VCM
Dynamic DC Characteristics and Accuracy
No missing codes
1.5
1.6
Tested
±0.25
±2.5
Differential nonlinearity error, DNL
Integral nonlinearity error, INL
Offset error
fIN = 55 MHz
fIN = 55 MHz
–0.9
–5
1.1
5
LSB
LSB
–11
±1.5
11
mV
Offset temperature coefficient
DC power-supply rejection ratio, DC PSRR
Gain error(1)
0.02
mV/°C
mV/V
%FS
∆%/°C
∆offset error/∆AVDD from AVDD = 3 V to AVDD = 3.6V
0.25
–2
±0.3
2
Gain temperature coefficient
–0.02
(1) Gain error is specified by design and characterization; it is not tested in production.
3
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ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, min and max specified over the full temperature range of –40°C to +85°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS,
50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted.
ADS5541
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic AC Characteristics
fIN = 10MHz
fIN = 55MHz
73.6
72.7
71.9
72.5
72
+25°C to +85°C
71.7
70.5
Full temperature range
Signal-to-noise ratio. SNR
fIN = 70MHz
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
dBFS
LSB
dBc
71
69
RMS idle channel noise
Input tied to common-mode
fIN = 10MHz
1.03
84
+25°C
78.3
76.3
86
fIN = 55MHz
Full temperature range
85
Spurious-free dynamic range, SFDR
fIN = 70MHz
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
fIN = 10MHz
82
86
75
72
90
+25°C
78.3
76.3
86
fIN = 55MHz
Full temperature range
85
Second-harmonic, HD2
fIN = 70MHz
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
fIN = 10MHz
82
dBc
88
75
72
84
+25°C
78.3
76.3
89
fIN = 55MHz
Full temperature range
88
Third-harmonic, HD3
fIN = 70MHz
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
fIN = 55MHz
fIN = 10MHz
82
dBc
dBc
86
80
78
Worst-harmonic/spur (other than HD2 and HD3)
Signal-to-noise + distortion, SINAD
87
72.6
72
+25°C
70.7
69.5
fIN = 55MHz
Full temperature range
71
fIN = 70MHz
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
fIN = 10MHz
71.8
71.2
70
dBFS
67
80
+25°C
76.5
74.5
83
fIN = 55MHz
Full temperature range
82
Total harmonic distortion, THD
Effective number of bits, ENOB
fIN = 70MHz
fIN = 100MHz
fIN = 150MHz
fIN = 220MHz
fIN = 55MHz
79
dBc
Bits
84
74
70.5
11.7
4
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ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, min and max specified over the full temperature range of –40°C to +85°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS,
50% clock duty cycle, DLL On, 3VPP differential clock, and –1dBFS differential input, unless otherwise noted.
ADS5541
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic AC Characteristics (continued)
f = 10.1MHz, 15.1MHz (–7dBFS each tone)
f = 50.1MHz, 55.1MHz (–7dBFS each tone)
f = 150.1MHz, 155.1MHz (–7dBFS each tone)
94
96
Two-tone intermodulation distortion, IMD
dBFS
84.7
Power Supply
Total supply current, ICC
Analog supply current, IAVDD
Output buffer supply current, IDRVDD
fIN = 55MHz
fIN = 55MHz
fIN = 55MHz
Analog only
224
173
51
250
185
65
mA
mA
mA
571
611
Power dissipation
Standby power
mW
mW
Output buffer power with 10pF load
on digital output to ground
168
180
215
250
With Clocks running
DIGITAL CHARACTERISTICS
Valid over full temperature range of TMIN = –40°C to TMAX = +85°C, and AVDD = DRVDD = 3.3V, unless otherwise noted.
ADS5541
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
VIH
VIL
IIH
High-level input voltage
Low-level input voltage
2.4
V
0.8
10
10
V
High-level input current
Low-level input current
Input current for RESET
Input capacitance
µA
µA
µA
pF
IIL
–20
4
Digital Outputs
VOL
VOH
Low-level output voltage
CLOAD = 10pF
0.3
3
0.4
V
V
High-level output voltage
Output capacitance
CLOAD = 10pF
2.8
3
pF
5
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N + 3
N + 4
N + 2
Sample
N
Analog
Input
Signal
N + 1
N + 17
N + 16
N + 14
N + 15
t
A
Input Clock
t
START
t
PDI
Output Clock
t
su
Data Out
(D0−D13)
N − 17
N − 16
N − 15
N − 14
N − 13
N − 3
N − 2
N − 1
N
Data Invalid
t
t
END
h
17.5 Clock Cycles
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above
timing matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS(1)(2)
At TA = +25°C, min and max specified over the full temperature range of –40°C to +85°C, sampling rate = 105MSPS, 50%
clock duty cycle, AVDD = DRVDD = 3.3V, and 3VPP differential clock, unless otherwise noted.
ADS5541
PARAMETER
Switching Specification
DESCRIPTION
MIN
TYP MAX
UNIT
tA
Aperture delay
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
Data valid(3) to 50% of CLKOUT rising edge
50% of CLKOUT rising edge to data becoming invalid(3)
1
300
2.8
ns
fs
Aperture jitter (uncertainty)
Data setup time
tSU
2.2
2.2
ns
ns
tH
Data hold time
2.5
(4)(5)
tSTART
Input clock to output data
valid start
Input clock rising edge to data valid start delay
Input clock rising edge to data valid end delay
1.9
7.3
2.8
ns
ns
(4)(5)
tEND
Input clock to output data
valid end
5.8
tJIT
Output clock jitter
Uncertainty in CLKOUT rising edge, peak-to-peak
Rise time of CLKOUT from 20% to 80% of DRVDD
Fall time of CLKOUT from 80% to 20% of DRVDD
175
2
250
2.2
1.8
5.5
ps
ns
ns
ns
tRISE
tFALL
tPDI
Output clock rise time
Output clock fall time
1.7
4.7
Input clock to output clock
delay
Input clock rising edge, zero crossing, to output clock
rising edge 50%
4
tR
tF
Data rise time
Data fall time
Data rise time measured from 20% to 80% of DRVDD
Data fall time measured from 80% to 20% of DRVDD
4.4
3.3
5.1
3.8
ns
ns
Output enable(OE) to data
output delay
Time required for outputs to have stable timings with
regard to input clock(6) after OE is activated
Clock
cycles
1000
1000
Time to valid data after coming out of software power
down and stopping and restarting the clock
Clock
cycles
Wakeup time
Latency
Clock
cycles
Time for a sample to propagate to the ADC outputs
17.5
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) See Table 5 through Table 8 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2V for LOGIC high and 0.8V for LOGIC low.
(4) See the Output Information section for details on using the input clock for data capture.
(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
(6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
6
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Power Supply
(AV , DRV
)
DD
DD
t . 10 ms
1
t . 2 ms
2
t . 2 ms
3
SEN Active
RESET (Pin 35)
Figure 2. Reset Timing Diagram
RESET TIMING CHARACTERISTICS
Typical values given at TA = +25°C, min and max specified over the full temperature range of –40°C to +85°C, AVDD = DRVDD = 3.3V, and
3VPP differential clock, unless otherwise noted.
ADS5541
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
t1
t2
t3
Power-on delay
Reset pulse width
Register write delay
Power-up time
Delay from power-on of AVDD and DRVDD to RESET pulse
Pulse width of active RESET signal
10
2
ms
µs
Delay from RESET disable to SEN active
2
µs
Delay from power-up of AVDD and DRVDD to output stable
40
ms
7
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SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The ADS5541 has a three-wire serial interface. The device latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
•
•
•
•
•
•
Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.
Minimum width of data stream for a valid loading is 16 clocks.
Data is loaded at every 16th SCLK falling edge while SEN is low.
In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
Data can be loaded in multiples of 16-bit words within a single active SEN pulse.
The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
A3
A2
A1
A0
D11
D10
D9
D0
SDATA
ADDRESS
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
t
SLOADS
t
SEN
SLOADH
t
t
t
SCLK
WSCLK WSCLK
SCLK
t
t
h(D)
su(D)
SDATA
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
ADS5541
TYP(1)
SYMBOL
tSCLK
PARAMETER
SCLK period
MIN(1)
MAX(1)
UNIT
ns
50
25
8
tWSCLK
tSLOADS
tSLOADH
tSY(D)
SCLK duty cycle
SEN to SCLK setup time
SCLK to SEN hold time
Data setup time
50
75
%
ns
6
ns
8
ns
tH(D)
Data hold time
6
ns
(1) Values are characterized, but not production tested.
8
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Table 2. Serial Register Table(1)
A3 A2 A1 A0 D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
D1
D0
DESCRIPTION
DLL
CTRL
Clock DLL
Internal DLL is on; recommended for 60MSPS to 105MSPS
clock speeds.
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Internal DLL is off; recommended for 2MSPS to 80MSPS
clock speeds.
TP<1> TP<0>
Test Mode
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
Normal mode of operation
All outputs forced to 0
All outputs forced to 1
0
(2)(3)
0
Each output bit toggles between 0 and 1.
PDN
0
Power Down
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
0
Normal mode of operation
1
Device is put in power-down (low-current) mode.
(1) The register contents default to the appropriate setting for normal operation up on RESET.
(2) The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode
outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section.
(3) While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0–D13. For
example, when D0 is a 1, D1 is not assured to be a 0, and vice-versa.
Table 3. Data Format Select (DFS) Table
DFS-PIN VOLTAGE (VDFS
)
DATA FORMAT
CLOCK OUTPUT POLARITY
2
12
V
AV
AV
V
t
AV
DD
Straight Binary
Data valid on rising edge
DFS
DD
5
12
4
12
t V
t V
t
AV
AV
Two's Complement
Straight Binary
Data valid on rising edge
Data valid on falling edge
Data valid on falling edge
DD
DFS
8
12
7
12
t
DD
DD
DFS
10
12
u
AV
DD
Two's Complement
DFS
9
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PIN CONFIGURATION
PAP PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DRGND
SCLK
SDATA
SEN
DRGND
D3
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D2
3
D1
4
AVDD
AGND
AVDD
AGND
AVDD
CLKP
CLKM
AGND
AGND
AGND
AVDD
AGND
D0 (LSB)
CLKOUT
DRGND
OE
5
6
7
ADS5541
PowerPAD
8
DFS
(Connected to Analog Ground)
9
AVDD
AGND
AVDD
AGND
RESET
AVDD
AVDD
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
10
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PIN CONFIGURATION (continued)
PIN ASSIGNMENTS(1)
TERMINAL
NO. OF
NAME
NO.
PINS
I/O
DESCRIPTION
AVDD
5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39
12
I
Analog power supply
6, 8, 12–14, 16, 18, 21, 23, 25, 27, 32,
36, 38
AGND
14
I
Analog ground (PowerPAD must be connected to analog ground).
DRVDD
DRGND
INP
49, 58
2
6
1
1
I
I
I
I
Output driver power supply
Output driver ground
1, 42, 48, 50, 57, 59
19
20
Differential analog input (positive)
Differential analog input (negative)
INM
Reference voltage (positive); 1µF capacitor in series with a 1Ω
resistor to GND.
REFP
REFM
29
30
1
1
O
O
Reference voltage (negative); 1µF capacitor in series with a 1Ω
resistor to GND.
IREF
CM
31
1
1
I
O
I
Current set; 56kΩ resistor to GND; do not connect capacitors.
17
Common-mode output voltage
(2)
RESET
OE
35
1
Reset (active high); Internal 200kΩ resistor to AVDD
.
41
1
I
Output enable (active high)(3)
DFS
40
1
I
Data format and clock out polarity select(4)(3)
Data converter differential input clock (positive)
Data converter differential input clock (negative)
Serial interface chip select(3)
CLKP
10
1
I
CLKM
11
1
I
SEN
4
1
I
SDATA
SCLK
3
1
I
Serial interface data(3)
2
1
I
Serial interface clock(3)
D0 (LSB)–D13 (MSB)
OVR
44–47, 51–56, 60–63
12
1
O
O
O
Parallel data output
64
43
Over-range indicator bit
CLKOUT
1
CMOS clock out in sync with data
(1) PowerPAD is connected to analog ground.
(2) If RESET pin is unused, it must be tied to AGND and serial interface should be used to reset the device. See the serial programming
interface section for details.
(3) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins must
also run off the same supply voltage as DRVDD
.
(4) Table 3 defines the voltage levels for each mode selectable via the DFS pin.
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DEFINITION OF SPECIFICATIONS
Offset Error
Analog Bandwidth
The offset error is the difference, given in number of
LSBs, between the ADC actual average idle channel
output code and the ideal average idle channel
output code. This quantity is often mapped into mV.
The analog input frequency at which the power of the
fundamental is reduced by 3dB with respect to the
low frequency value.
Aperture Delay
Temperature Drift
The delay in time between the falling edge of the
input sampling clock and the actual time at which the
sampling occurs.
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per
degree Celsius of the parameter from TMIN to TMAX. It
is calculated by dividing the maximum deviation of
the parameter across the TMIN to TMAX range by the
difference (TMAX – TMIN).
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
Signal-to-Noise Ratio (SNR)
The duty cycle of a clock signal is the ratio of the
time the clock signal remains at a logic high (clock
pulse width) to the period of the clock signal. Duty
cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50%
duty cycle.
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and the first eight harmonics.
PS
10 PN
SNR + 10Log
(1)
Maximum Conversion Rate
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to Full-Scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
Signal-to-Noise and Distortion (SINAD)
The minimum sampling rate at which the ADC
functions.
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral
components including noise (PN) and distortion (PD),
but excluding dc.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog
input values spaced exactly 1LSB apart. The DNL is
the deviation of any single step from this ideal value,
measured in units of LSBs.
PS
SINAD + 10Log
10 PN ) PD
(2)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Integral Nonlinearity (INL)
The INL is the deviation of the ADC transfer function
from a best fit line determined by a least squares
curve fit of that transfer function, measured in units
of LSBs.
Effective Number of Bits (ENOB)
Gain Error
The ENOB is
a
measure of
a
converter's
performance as compared to the theoretical limit
based on quantization noise.
The gain error is the deviation of the ADC actual
input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input
full-scale range. Gain error does not account for
variations in the internal reference voltages (see the
Electrical Characteristics section for limits on the
variation of VREFP and VREFM).
SINAD * 1.76
ENOB +
6.02
(3)
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Total Harmonic Distortion (THD)
Reference Error
THD is the ratio of the power of the fundamental (PS)
to the power of the first eight harmonics (PD).
The reference error is the variation of the actual
reference voltage (VREFP – VREFM) from its ideal
value. The reference error is typically given as a
percentage.
PS
10 PD
THD + 10Log
(4)
Voltage Overload Recovery Time
THD is typically given in units of dBc (dB to carrier).
The voltage overload recovery time is defined as the
time required for the ADC to recover to within 1% of
the full-scale range in response to an input voltage
overload of 10% beyond the full-scale range.
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc
(dB to carrier).
AC Power-Supply Rejection Ratio (AC PSRR)
The ratio of output spectral power at a given
frequency with respect to the injected ac-power on
AVDD at that frequency. The rejected ac-input
Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at
frequencies f1 and f2) to the power of the worst
spectral component at either frequency 2f1 – f2 or 2f2
– f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to full scale)
when the power of the fundamental is extrapolated to
the converter full-scale range.
amplitude should be limited to less than 100mVPP
The PSRR is typically given in units of dB.
.
DC Power-Supply Rejection Ration (DC PSRR)
The DC PSSR is the ratio of the change in offset
error to a change in analog supply voltage. The DC
PSRR is typically given in units of mV/V.
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TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and
–1dBFS differential input, unless otherwise noted.
SPECTRAL PERFORMANCE
(FFT for 4MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 16MHz Input Signal)
0
-20
0
-20
SFDR = 87.3dBc
SFDR = 91.6dBc
SNR = 73.9dBFS
THD = 85.7dBc
SNR = 74.3dBFS
THD = 87.5dBc
SINAD = 73.7dBFS
SINAD = 74.1dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
0
0
10
20
30
40
50
0
0
0
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 5.
Figure 6.
SPECTRAL PERFORMANCE
(FFT for 55MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 70MHz Input Signal)
0
-20
0
-20
SFDR = 80.9dBc
SFDR = 88.2dBc
SNR = 73.1dBFS
THD = 79.1dBc
SNR = 73.5dBFS
THD = 84.2dBc
SINAD = 72.3dBFS
SINAD = 73.2dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
10
20
30
40
50
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 7.
Figure 8.
SPECTRAL PERFORMANCE
(FFT for 100MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 125MHz Input Signal)
0
-20
0
-20
SFDR = 85.2dBc
SFDR = 82.8dBc
SNR = 72.3dBFS
THD = 82.4dBc
SNR = 72.1dBFS
THD = 80.8dBc
SINAD = 71.9dBFS
SINAD = 71.7dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
10
20
30
40
50
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and
–1dBFS differential input, unless otherwise noted.
SPECTRAL PERFORMANCE
(FFT for 150MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 220MHz Input Signal)
0
-20
0
-20
SFDR = 74.3dBc
SFDR = 73.1dBc
SNR = 71.5dBFS
THD = 74.1dBc
SNR = 69.5dBFS
THD = 72.5dBc
SINAD = 68dBFS
SINAD = 69.9dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
10
20
30
40
50
0
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 11.
Figure 12.
SPECTRAL PERFORMANCE
(FFT for 300MHz Input Signal)
TWO-TONE INTERMODULATION
0
-20
0
-20
SFDR = 65.1dBc
f1 = 10.1MHz, 7dBFS
f2 = 15.1MHz, 7dBFS
IMD3 = 94.6dBFS
SNR = 67.8dBFS
THD = 64.3dBc
SINAD = 63.4dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
10
20
30
40
50
0
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 13.
Figure 14.
TWO-TONE INTERMODULATION
TWO-TONE INTERMODULATION
0
-20
0
-20
f1 = 150.1MHz, 7dBFS
f2 = 155.1MHz, 7dBFS
IMD = 84.7dBFS
f1 = 50.1MHz, 7dBFS
f2 = 55.1MHz, 7dBFS
IMD = 96.6dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
10
20
30
40
50
0
10
20
30
40
50
Frequency (MHz)
Frequency (MHz)
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and
–1dBFS differential input, unless otherwise noted.
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
2.0
1.5
1.0
0.8
f
A
= 10 MHz
f
A
= 10 MHz
IN
IN
= −0.5 dBFS
= −0.5 dBFS
IN
IN
0.6
1.0
0.4
0.5
0.2
0.0
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−0.5
−1.0
−1.5
−2.0
0
2048 4096 6144 8192 10240 12288 14336 16384
0
2048 4096 6144 8192 10240 12288 14336 16384
Code
Code
Figure 17.
Figure 18.
SPURIOUS-FREE DYNAMIC RANGE vs
INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO vs
INPUT FREQUENCY
95
90
85
80
75
70
65
60
75
74
73
72
71
70
69
68
67
66
65
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Input Frequency (MHz)
Input Frequency (MHz)
Figure 19.
Figure 20.
AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE
AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE
90
76
88
86
84
82
80
78
76
74
72
70
f
IN
= 70 MHz
f
IN
= 150 MHz
75
74
73
72
71
70
SFDR
SFDR
SNR
SNR
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Analog Supply Voltage (V)
Analog Supply Voltage (V)
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and
–1dBFS differential input, unless otherwise noted.
AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE
AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE
90
80
f
IN
= 150MHz
f
IN
= 70 MHz
88
86
84
82
80
78
76
74
72
70
78
76
74
72
70
68
66
64
62
60
SFDR
SNR
SFDR
SNR
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Digital Supply Voltage (V)
Digital Supply Voltage (V)
Figure 23.
Figure 24.
POWER DISSIPATION vs SAMPLE RATE
POWER DISSIPATION vs SAMPLE RATE
600
500
400
300
200
100
0
600
500
400
300
200
100
0
f
IN
= 70MHz
f
IN
= 150MHz
Analog (DLL On)
Analog (DLL On)
Analog (DLL Off)
Analog (DLL Off)
I/O (DLL On)
I/O (DLL On)
I/O (DLL Off)
I/O (DLL Off)
0
10 20 30 40 50 60 70 80 90 100 110
Sample Rate (MSPS)
0
10 20 30 40 50 60 70 80 90 100 110
Sample Rate (MSPS)
Figure 25.
Figure 26.
AC PERFORMANCE vs FREE-AIR TEMPERATURE
AC PERFORMANCE vs INPUT AMPLITUDE
90
88
86
84
82
80
78
76
74
72
70
100
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
f
IN
= 70MHz
f
IN
= 70MHz
SNR (dBFS)
SFDR
SFDR (dBc)
SNR (dBc)
SNR
−40
−15
10
35
60
85
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Free-Air Temperature (°C)
Input Amplitude (dBFS)
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and
–1dBFS differential input, unless otherwise noted.
AC PERFORMANCE vs INPUT AMPLITUDE
AC PERFORMANCE vs INPUT AMPLITUDE
100
90
80
100
90
80
f
IN
= 150MHz
f
IN
= 220MHz
SNR (dBFS)
SNR (dBFS)
70
70
60
60
50
40
50
40
SFDR (dBc)
SFDR (dBc)
30
30
SNR (dBc)
SNR (dBc)
20
20
10
10
0
0
−10
−20
−30
−10
−20
−30
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 29.
Figure 30.
AC PERFORMANCE vs DIFFERENTIAL CLOCK
AMPLITUDE
OUTPUT NOISE HISTOGRAM
45
95
90
85
80
75
70
65
39.24
f
IN
= 70MHz
40
35
30
25
20
15
10
5
SFDR
SNR
0
8195 8196 8197 8198 8199 8200 8201 8201 8203
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Code
Differential Clock Amplitude (V)
Figure 31.
Figure 32.
WCDMA CARRIER
AC PERFORMANCE vs CLOCK DUTY CYCLE
0
−20
95
90
85
80
75
70
65
SFDR
f
IN
= 20MHz
−40
−60
−80
−100
−120
−140
SNR
0
5
10 15 20 25 30 35 40 45 50
Frequency (MHz)
40
45
50
55
60
Clock Duty Cycle (%)
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and
–1dBFS differential input, unless otherwise noted.
125
69
67
70
120
115
110
105
100
95
66
70
69
70
69
68
67
68
67
66
90
66
85
70
80
75
68
70
69
67
65
70
80
66
60
20
40
60
100
120
140
160
180
200
220
Input Frequency (MHz)
Figure 35. SIGNAL-TO-NOISE RATIO (SNR) (DLL On)
125
120
115
110
105
100
95
64
67
67
68
66
67
70
65
68
68
69
69
68
67
69
66
70
67
90
69
70
68
85
66
65
64
80
75
70
66
70
69
65
67
68
60
20
40
60
80
100
120
140
160
180
200
220
Input Frequency (MHz)
Figure 36. SIGNAL-TO-NOISE RATIO (SNR) (DLL Off)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = DRVDD = 3.3V, sampling rate = 105MSPS, 50% clock duty cycle, DLL On, 3VPP differential clock, and
–1dBFS differential input, unless otherwise noted.
125
86
84
80
84
78
120
115
110
105
100
95
84
84
88
86
84
82
80
78
76
74
72
82
76
76
74
82
82
82
82
82
80
86
86
78
84
84
74
84
90
86
82
85
80
84
78
76
80
84
75
74
86
84
86
70
88
65
88
84
86
82
84
82
80
140
Input Frequency (MHz)
76
78
84
100
60
20
40
60
80
120
160
180
200
220
Figure 37. SPURIOUS-FREE DYNAMIC RANGE (SFDR) (DLL On)
125
120
115
76
76
74
80
82
78
1
88
86
84
82
80
78
76
74
72
78
78
110 1
105
80
82
76
84
74
84
100 1
95
86
80
84
72
82
78
90
85
76
88
84
74
80
75
80
88
82
84
84
84
86
86
78
70
65
86
84
82
76
60
20
40
60
80
100
120
140
160
180
200
220
Input Frequency (MHz)
Figure 38. SPURIOUS-FREE DYNAMIC RANGE (SFDR) (DLL Off)
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APPLICATION INFORMATION
clock cycle. This process results in a data latency of
17.5 clock cycles, after which the output data is
available as a 14-bit parallel word, coded in either
straight offset binary or binary two’s complement
format.
THEORY OF OPERATION
The ADS5541 is a low-power, 14-bit, 105MSPS,
CMOS, switched capacitor, pipeline ADC that
operates from a single 3.3V supply. The conversion
process is initiated by a falling edge of the external
input clock. Once the signal is captured by the input
S&H, the input sample is sequentially converted by a
series of small resolution stages, with the outputs
combined in a digital correction logic block. Both the
rising and the falling clock edges are used to
propagate the sample through the pipeline every half
INPUT CONFIGURATION
The analog input for the ADS5541 consists of a
differential
sample-and-hold
architecture
implemented using the switched capacitor technique
shown in Figure 39.
S
3a
L1
R1a
C1a
INP
S
S
1a
CP1
CP3
S
2
R3
CA
L2
R1b
C1b
VINCM
1V
1b
INM
CP2
CP4
S
3b
L , L : 6 nH − 10 nH effective
1
2
R
1a
, R : 5W − 8W
1b
C , C : 2.2 pF − 2.6 pF
1a 1b
CP , CP : 2.5 pF − 3.5 pF
1
2
CP , CP : 1.2 pF − 1.8 pF
3
4
C : 0.8 pF − 1.2 pF
A
R : 80 W − 120 W
3
Swithches: S , S
On Resistance: 35 W − 50 W
1a 1b:
S : On Resistance: 7.5 W − 15 W
2
S
, S : On Resistance: 40 W − 60 W
3a 3b
All switches OFF Resistance: 10 GW
NOTE: All Switches are ON in sampling phase, which is approximately one-half of a clock period.
Figure 39. Analog Input Stage
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This differential input topology produces a high level
of ac performance for high sampling rates. It also
results in a very high usable input bandwidth,
especially important for high intermediate-frequency
(IF) or undersampling applications. The ADS5541
requires each of the analog inputs (INP, INM) to be
externally biased around the common-mode level of
the internal circuitry (CM, pin 17). For a full-scale
differential input, each of the differential lines of the
input signal (pins 19 and 20) swing symmetrically
between CM + 0.575V and CM – 0.575V. This
means that each input is driven with a signal of up to
CM ± 0.575V, so that each input has a maximum
differential signal of 1.15VPP for a total differential
input signal swing of 2.3VPP. The maximum swing is
determined by the two reference voltages, the top
reference (REFP, pin 29) and the bottom reference
(REFM, pin 30).
The single-ended signal is fed to the primary winding
of an RF transformer. Placing a 25Ω resistor in
series with INP and INM is recommended to dampen
ringing because of ADC kickback. Since the input
signal must be biased around the common-mode
voltage of the internal circuitry, the common-mode
voltage (VCM) from the ADS5541 is connected to the
center-tap of the secondary winding. To ensure a
steady low-noise VCM reference, best performance is
attained when the CM output (pin 17) is filtered to
ground with a 10Ω series resistor and parallel 0.1µF
and 0.001µF low-inductance capacitors as illustrated
in Figure 39.
Output VCM (pin 17) is designed to directly drive the
ADC input. When providing a custom CM level, be
aware that the input structure of the ADC sinks a
common-mode current in the order of 500µA (250µA
per input) at 105MSPS. Equation 5 describes the
dependency of the common-mode current and the
sampling frequency:
The ADS5541 gives optimum performance when the
analog inputs are driven differentially. The circuit
shown in Figure 40 illustrates one possible
configuration using an RF transformer.
500mA fS (in MSPS)
105 MSPS
Where:
fS > 2MSPS.
(5)
This equation helps to design the output capability
and impedance of the driving circuit accordingly.
R0
Z0
Ω
50
Ω
25
Ω
50
INP
1:1
R
50
AC Signal
Source
ADS5541
Ω
25
Ω
INM
CM
ADT1−1WT
Ω
10
µ
0.1 F
1nF
Figure 40. Transformer Input to Convert Single-Ended Signal to Differential Signal
22
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When it is necessary to buffer or apply a gain to the
incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF
transformer, or to use a differential input/output
amplifier without a transformer, to drive the input of
the ADS5541. Texas Instruments offers a wide
selection of single-ended operational amplifiers
(including the THS3201, THS3202, OPA847, and
OPA695) that can be selected depending on the
application. An RF gain block amplifier, such as
Texas Instruments THS9001, can also be used with
an RF transformer for high input frequency
Figure 41 illustrates how RIN and CIN can be placed
to isolate the signal source from the switching inputs
of the ADC and to implement a low-pass RC filter to
limit the input noise in the ADC. It is recommended
that these components be included in the ADS5541
circuit layout when any of the amplifier circuits
discussed previously are used. The components
allow fine-tuning of the circuit performance. Any
mismatch between the differential lines of the
ADS5541 input produces
a
degradation in
performance at high input frequencies, mainly
characterized by an increase in the even-order
harmonics. In this case, special care should be taken
to keep as much electrical symmetry as possible
between both inputs.
applications. The THS4503 is
a recommended
differential input/output amplifier. Table 4 lists the
recommended amplifiers.
When using single-ended operational amplifiers
(such as the THS3201, THS3202, OPA847, or
OPA695) to provide gain, a three-amplifier circuit is
recommended with one amplifier driving the primary
of an RF transformer and one amplifier in each of the
legs of the secondary driving the two differential
inputs of the ADS5520. These three amplifier circuits
minimize even-order harmonics. For high frequency
inputs, an RF gain block amplifier can be used to
Another possible configuration for lower-frequency
signals is the use of differential input/output
amplifiers that can simplify the driver circuit for
applications requiring dc-coupling of the input.
Flexible in their configurations (see Figure 42), such
amplifiers can be used for single-ended-to-differential
conversion signal amplification.
drive
a transformer primary; in this case, the
transformer secondary connections can drive the
input of the ADS5541 directly, as shown in
Figure 40, or with the addition of the filter circuit
shown in Figure 41.
Table 4. Recommended Amplifiers to Drive the Input of the ADS5520
INPUT SIGNAL FREQUENCY
RECOMMENDED AMPLIFIER
THS4503
TYPE OF AMPLIFIER
Differential In/Out Amp
USE WITH TRANSFORMER
DC to 20MHz
DC to 50MHz
No
OPA847
OPA695
THS3201
THS3202
THS9001
Operational Amp
Operational Amp
Operational Amp
Operational Amp
RF Gain Block
Yes
Yes
Yes
Yes
Yes
10MHz to 120MHz
Over 100MHz
−
+5V 5V
RS
RIN
Ω
100
µ
0.1 F
VIN
1:1
INP
INM
OPA695
RT
100
CIN
1000pF
ADS5541
RIN
Ω
R1
Ω
400
CM
Ω
10
AV = 8V/V
(18dB)
R2
57.5
Ω
µ
0.1 F
Figure 41. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
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RS
RG
RF
+5V
RT
+3.3V
µ
µ
0.1 F
10 F
RIN
RIN
INP
ADS5541
VOCM
14-Bit / 105MSPS
INM
µ
1 F
THS4503
CM
µ
µ
0.1 F
10 F
Ω
10
−
5V
RG
RF
µ
0.1 F
Figure 42. Using the THS4503 with the ADS5520
Using the serial interface PDN bit to power down the
device places the outputs in a high-impedance state
and only the internal reference remains on to reduce
the power-up time. The power-down mode reduces
power dissipation to approximately 180mW.
POWER-SUPPLY SEQUENCE
The preferred mode of power-supply sequencing is
to power up AVDD first, followed by DRVDD. Raising
both supplies simultaneously is also
a
valid
power-supply sequence. In the event that DRVDD
powers up before AVDD in the system, AVDD must
power up within 10ms of DRVDD. Optionally, it is
recommended to put a 2kΩ resistor from REFP (pin
29) to AVDD as shown in Figure 43. This
configuration helps to make the device more robust
to power supply ramp-up timings.
REFERENCE CIRCUIT
The ADS5541 has built-in internal reference
generation, requiring no external circuitry on the
printed circuit board (PCB). For optimum
performance, it is best to connect both REFP and
REFM to ground with a 1µF decoupling capacitor
(the 1Ω resistor shown in Figure 44 is optional). In
addition, an external 56kΩ resistor should be
connected from IREF (pin 31) to AGND to set the
proper current for the operation of the ADC, as
shown in Figure 44. No capacitor should be
connected between pin 31 and ground; only the
56kΩ resistor should be used.
28
29
AVDD
2kΩ
REFP
1Ω
1µF
1Ω
REFP
REFM
IREF
29
30
31
1µF
1µF
1Ω
Figure 43.
POWER-DOWN
The device enters power-down in one of two ways:
either by reducing the clock speed or by setting the
PDN bit via the serial programming interface. Using
the reduced clock speed, power-down may be
initiated for clock frequency below 2MSPS. The
exact frequency at which the power-down occurs
varies from device to device.
56kΩ
Figure 44. REFP, REFM, and IREF Connections
for Optimum Performance
24
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CLOCK INPUT
The ADS5541 clock input can also be driven
differentially, reducing susceptibility to
common-mode noise. In this case, it is best to
connect both clock inputs to the differential input
clock signal with 0.01µF capacitors, as shown in
Figure 47.
The ADS5541 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between
both configurations. The common-mode voltage of
the clock inputs is set internally to CM (pin 17) using
internal 5kΩ resistors that connect CLKP (pin 10)
and CLKM (pin 11) to CM (pin 17), as shown in
Figure 45.
µ
0.01 F
CLKP
ADS5541
CLKM
Differential Square Wave
or Sine Wave
(3VPP
)
CM
CM
µ
0.01 F
5 kW
5 kW
Figure 47. AC-Coupled, Differential Clock Input
For high-input frequency sampling, it is
CLKM
CLKP
recommended to use a clock source with low jitter.
Additionally, the internal ADC core uses both edges
of the clock for the conversion process. This means
that, ideally, a 50% duty cycle should be provided.
Figure 48 shows the performance variation of the
ADC versus clock duty cycle.
6 pF
95
f
IN
= 20MHz
SFDR
3 pF
3 pF
90
85
80
75
70
65
Figure 45. Clock Inputs
When driven with a single-ended CMOS clock input,
it is best to connect CLKM (pin 11) to ground with a
0.01µF capacitor, while CLKP is ac-coupled with a
0.01µF capacitor to the clock source, as shown in
Figure 46.
SNR
40
45
50
Clock Duty Cycle (%)
55
60
µ
0.01 F
Square Wave
or Sine Wave
CLKP
ADS5541
Figure 48. AC Performance vs Clock Duty Cycle
(3VPP
)
CLKM
µ
0.01
F
Figure 46. AC-Coupled, Single-Ended Clock Input
25
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Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter further
improves as the amplitude is increased. In that
sense, using a differential clock allows for the use of
larger amplitudes without exceeding the supply rails
and absolute maximum ratings of the ADC clock
input. Figure 49 shows the performance variation of
the device versus input clock amplitude. For detailed
clocking schemes based on transformer or
PECL-level clocks, see the ADS5541EVM User's
Guide (SLWU010), available for download from
www.ti.com.
of the two modes, the device enters power-down
mode if no clock or a slow clock is provided. The
limit of the clock frequency where the device
functions properly with default settings is ensured to
be over 2MHz.
OUTPUT INFORMATION
The ADC provides 14 data outputs (D13 to D0, with
D13 being the MSB and D0 the LSB), a data-ready
signal (CLKOUT, pin 43), and an out-of-range
indicator (OVR, pin 64) that equals '1' when the
output reaches the full-scale limits.
Two different output formats (straight offset binary or
two's complement) and two different output clock
polarities (latching output data on rising or falling
edge of the output clock) can be selected by setting
DFS (pin 40) to one of four different voltages.
Table 3 details the four modes. In addition, output
enable control (OE, pin 41, active high) is provided to
put the outputs into a high-impedance state.
95
f
IN
= 70MHz
90
85
80
75
70
65
SFDR
SNR
In the event of an input voltage overdrive, the digital
outputs go to the appropriate full-scale level. For a
positive overdrive, the output code is 0x3FFF in
straight offset binary output format, and 0x1FFF in
two's complement output format. For a negative input
overdrive, the output code is 0x0000 in straight offset
binary output format, and 0x2000 in two's
complement output format. These outputs to an
overdrive signal are ensured through design and
characterization
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Differential Clock Amplitude (V)
Figure 49. AC Performance vs Clock Amplitude
INTERNAL DLL
The output circuitry of the ADS5541, by design,
minimizes the noise produced by the data switching
transients, and, in particular, its coupling to the ADC
analog circuitry. Output D4 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output
slew rate described in the timing diagram of Figure 1.
Care should be taken to ensure that all output lines
(including CLKOUT) have nearly the same load as
D4 (pin 51). This circuit also reduces the sensitivity
of the output timing versus supply voltage or
temperature. Placing external resistors in series with
the outputs is not recommended.
In order to achieve the fastest possible sampling
rates with the ADS5541, the device uses an internal
delay locked loop (DLL). The effective delay range of
the DLL limits its use to sampling rates above
60MSPS. In order to operate the device below
60MSPS, the internal DLL must be shut off using the
DLL OFF mode described in the Serial Programming
Interface section. The Typical Characteristics show
the performance obtained in both modes of
operation: DLL ON (default) and DLL OFF. In either
26
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The timing characteristics of the digital outputs
change for sampling rates below the 105MSPS
maximum sampling frequency. Table 5 and Table 6
show the setup, hold, and input clocks to output data
delays, and rise and fall times for different sampling
frequencies with the DLL on and off, respectively.
To use the input clock as the data capture clock, it is
necessary to delay the input clock by a delay, td, that
results in the desired setup or hold time. Use either
of the following equations to calculate the value of tD.
Desired setup time = tD– tSTART
Desired hold time = tEND – tD
Table 7 and Table 8 show the values of various
timing parameters for lower sampling frequencies,
both with DLL on and off.
Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
tSU (ns)
tH (ns)
tSTART (ns)
tEND (ns)
tR (ns)
tF (ns)
fS
(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
80
65
2.8
3.8
3.7
4.6
2.8
3.6
3.3
4.1
0.5
1.7
0.8
5.3
5.3
7.9
8.5
5.8
6.7
6.6
7.2
4.4
5.5
5.3
6.4
–0.5
Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
tSU (ns)
tH (ns)
tSTART (ns)
tEND (ns)
tR (ns)
tF (ns)
fS
(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
80
65
40
20
10
2
3.2
4.3
8.5
17
4.2
5.7
11
1.8
2
3
3.8
2.8
5
4.5
1.5
2
8.4
8.3
11
5.8
6.6
7.5
7.5
6.6
7.2
8
4.4
5.5
7.3
7.6
5.3
6.4
7.8
8
3
11.8
14.5
21.6
31
2.6
2.5
4
3.5
4.7
6.5
19
–1
8.9
25.7
51
–9.8
-30
185
9.5
8
27
-3
11.5
515
284
370
8
320
576
50
82
75
150
Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
CLKOUT
tRISE (ns)
CLKOUT
tFALL (ns)
CLKOUT Jitter, Peak-to-Peak
tJIT (ps)
Input-to-Output Clock Delay
tPDI (ns)
fS
(MSPS)
MIN
TYP
2.5
MAX
2.8
MIN
TYP
2.1
MAX
2.3
MIN
TYP
210
260
MAX
315
MIN
3.7
TYP
4.3
MAX
5.1
80
65
3.1
3.5
2.6
2.9
380
3.5
4.1
4.8
Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
CLKOUT Jitter,
CLKOUT
tRISE (ns)
CLKOUT
tFALL (ns)
Peak-to-Peak
tJIT (ps)
Input-to-Output Clock Delay
tPDI (ns)
fS
(MSPS)
MIN
TYP
2.5
3.1
4.8
8.3
31
MAX
2.8
3.5
5.3
9.5
52
MIN
TYP
2.1
2.6
4
MAX
2.3
2.9
4.4
8.2
65
MIN
TYP
210
260
445
800
2610
MAX
315
MIN
7.1
7.8
9.5
13
TYP
8
MAX
8.9
80
65
40
20
2
380
8.5
9.4
650
10.4
15.5
551
11.4
18
7.6
36
1200
4400
537
567
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SERIAL PROGRAMMING INTERFACE
frame die pad (or thermal pad) is exposed on the
bottom of the IC. This provides an extremely low
thermal resistance path between the die and the
exterior of the package. The thermal pad on the
bottom of the IC can then be soldered directly to the
PCB, using the PCB as a heatsink.
The ADS5541 has internal registers for the
programming of some of the modes described in the
previous sections. The registers should be reset after
power-up by applying a 2µs (minimum) high pulse on
RESET (pin 35); this pulse also resets the entire
ADC and sets the data outputs to low. This pin has a
Assembly Process
200kΩ internal pullup resistor to AVDD
.
The
1. Prepare the PCB top-side etch pattern
including etch for the leads as well as the
thermal pad as illustrated in the Mechanical
Data section. The recommended thermal pad
dimension is 8mm × 8mm.
programming is done through a three-wire interface.
Table 2 shows the different modes and the bit values
to be written to the register to enable them.
Note that some of these modes may modify the
standard operation of the device and possibly vary
the performance with respect to the typical data
shown in this data sheet.
2. Place a 5-by-5 array of thermal vias in the
thermal pad area. These holes should be
13mils in diameter. The small size prevents
wicking of the solder through the holes.
Applying a RESET signal is absolutely essential to
set the internal registers to the default states for
normal operation. If the hardware RESET function is
not used in the system, the RESET pin must be tied
to ground, and it is necessary to write the default
values to the internal registers through the serial
programming interface. The registers must be written
in the following order.
3. It is recommended to place a small number of
25mil diameter holes under the package, but
outside the thermal pad area to provide an
additional heat path.
4. Connect all holes (both those inside and
outside the thermal pad area) to an internal
copper plane (such as a ground plane).
Write 9000h (Address 9, Data 000)
Write A000h (Address A, Data 000)
Write B000h (Address B, Data 000)
Write C000h (Address C, Data 000)
Write D000h (Address D, Data 000)
Write E000h (Address E, Data 804)
Write 0000h (Address 0, Data 000)
Write 1000h (Address 1, Data 000)
Write F000h (Address F, Data 000)
5. Do not use the typical web or spoke via
connection pattern when connecting the
thermal vias to the ground plane. The spoke
pattern increases the thermal resistance to the
ground plane.
6. The top-side solder mask should leave
exposed the terminals of the package and the
thermal pad area.
7. Cover the entire bottom side of the PowerPAD
vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal
pad area and all of the package terminals.
NOTE: This procedure is only required if a RESET
pulse is not provided to the device.
For more detailed information regarding the
PowerPAD package and its thermal properties, see
either the application brief SLMA004B (PowerPAD
Made Easy) or technical brief SLMA002 (PowerPAD
Thermally Enhanced Package).
PowerPAD PACKAGE
The PowerPAD package is a thermally-enhanced
standard size IC package designed to eliminate the
use of bulky heatsinks and slugs traditionally used in
thermal packages. This package can be easily
mounted using standard printed circuit board (PCB)
assembly techniques, and can be removed and
replaced using standard repair procedures.
The PowerPAD package is designed so that the lead
28
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Changes from B Revision (March 2006) to C Revision ................................................................................................. Page
Added MIN and MAX values for offset error and gain error, footnote for gain error. ........................................................... 3
•
29
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PACKAGE OPTION ADDENDUM
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10-Jun-2014
PACKAGING INFORMATION
Orderable Device
ADS5541IPAP
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
HTQFP
HTQFP
PAP
64
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS5541I
ADS5541I
ADS5541IPAPR
ACTIVE
PAP
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS5541IPAPR
HTQFP
PAP
64
1000
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PAP 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
ADS5541IPAPR
1000
Pack Materials-Page 2
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相关型号：
ADS5545IRGZR
1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLASTIC, QFN-48
TI
ADS5545IRGZRG4
1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLASTIC, QFN-48
TI
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