ADS5542IPAPG4 [TI]
14-Bit, 80-MSPS Analog-to-Digital Converter (ADC) 64-HTQFP -40 to 85;
| 型号： | ADS5542IPAPG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-Bit, 80-MSPS Analog-to-Digital Converter (ADC) 64-HTQFP -40 to 85 转换器 |
| 文件： | 总33页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
14-Bit, 80 MSPS
Analog-To-Digital Converter
FEATURES
•
•
TQFP-64 PowerPAD™ Package
Recommended Amplifiers:
OPA695, OPA847, THS3201, THS3202,
THS4503, THS4509, THS9001
•
•
•
•
•
•
•
•
•
14-Bit Resolution
80 MSPS Sample Rate
High SNR: 72.9 dBFS at 100 MHz fIN
High SFDR: 88 dBc at 100 MHz fIN
2.3-VPP Differential Input Voltage
Internal Voltage Reference
APPLICATIONS
•
Wireless Communication
–
–
Communication Receivers
Base Station Infrastructure
3.3-V Single-Supply Voltage
Analog Power Dissipation: 545 mW
Serial Programming Interface
•
•
•
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Communication Instrumentation
–
Radar, Infrared
•
•
Video and Imaging
Medical Equipment
DESCRIPTION
The ADS5542 is a high-performance, 14-bit, 80 MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference.
Designed for applications demanding the highest speed and highest dynamic performance in little space, the
ADS5542 has excellent power consumption of 545 mW at 3.3-V single-supply voltage. This allows an even
higher system integration density. The provided internal reference simplifies system design requirements.
Parallel CMOS-compatible output ensures seamless interfacing with common logic.
The ADS5542 is available in a 64-pin TQFP PowerPAD package over the industrial temperature range -40°C to
85°C.
ADS5500 PRODUCT FAMILY
80 MSPS
ADS5522
ADS5542
105 MSPS
ADS5521
ADS5541
125 MSPS
ADS5542
ADS5500
12 Bit
14 Bit
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5542
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
AV
DD
DRV
DD
CLK+
CLK−
Timing Circuitry
CLKOUT
14-Bit
Pipeline
ADC
D0
Digital
Error
Correction
V
IN+
.
.
.
Output
Control
S&H
V
D13
IN−
Core
OVR
DFS
Internal
Reference
Control Logic
CM
Serial Programming Register
ADS5542
A
GND
SEN
SDATA SCLK
DR
GND
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT PACKAGE-LEAD
HTQFP-64(2)
ADS5542
ADS5542IPAP
Tray, 160
PAP
–40°C to 85°C
ADS5542I
PowerPAD
ADS5542IPAPR
Tape and Reel, 1000
(1) For the most current product and ordering information, see the Package Option Addendum at the end of this data sheet.
(2) Thermal pad size: 3,5 mm × 3,5 mm (min), 4 mm x 4 mm (max). θJA = 21.47°C/W and θJC = 2.99°C/W, when used with 2 oz. copper
trace and pad soldered directly to a JEDEC standard, four-layer, 3 in × 3 in PCB.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
ADS5500
–0.3 to 3.7
UNIT
V
AVDD to AGND, DRVDD to DRGND
AGND to DRGND
Supply Voltage
±0.1
V
(2)(3)
Analog input to AGND
Logic input to DRGND
–0.3 to minimum (AVDD + 0.3, 3.6)
–0.3 to DRVDD
–0.3 to DRVDD
–40 to 85
V
V
Digital data output to DRGND
Operating temperature range
Junction temperature
V
°C
°C
°C
105
Storage temperature range
–65 to 150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 Ω should be added in series with each of the analog
input pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycle
of the overshoot should be limited to less than 5% for inputs up to 3.9 V.
(3) The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as a
percentage. The total time of overshoot is the integrated time of all overshoot occurences over the lifetime of the device.
2
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLIES
Analog supply voltage, AVDD
Output driver supply voltage, DRVDD
ANALOG INPUT
3
3
3.3
3.3
3.6
3.6
V
V
Differential input range
2.3
VPP
V
(1)
Input common-mode voltage, VCM
1.45
1.55
1.65
DIGITAL OUTPUT
Maximum output load
10
pF
CLOCK INPUT
ADCLK input sample rate (sine wave) 1/tC
Clock amplitude, sine wave, differential(2)
Clock duty cycle(3)
2
1
80
85
MSPS
VPP
3
50%
Open free-air temperature range
–40
°C
(1) Input common-mode should be connected to CM.
(2) See Figure 47 for more information.
(3) See Figure 46 for more information.
ELECTRICAL CHARACTERISTICS
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1dBFS differential input,
unless otherwise noted
=
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12
Bits
Analog Inputs
Differential input range
2.3
6.6
4
VPP
kΩ
pF
Differential input impedance
Differential input capacitance
See Figure 37
See Figure 37
Analog input common-mode current (per
input)
200
µA
Analog input bandwidth
Source impedance = 50 Ω
750
4
MHz
Voltage overload recovery time
Internal Reference Voltages
Reference bottom voltage, VREFM
Reference top voltage, VREFP
Reference error
Clock cycles
1.0
2.15
V
V
–4%
±0.6%
4%
Common-mode voltage output, VCM
Dynamic DC Characteristics and Accuracy
No missing codes
1.55 ±0.05
V
Assured
0.5
Differential nonlinearity error, DNL
Integral nonlinearity error, INL
Offset error
fIN = 10 MHz
fIN = 10 MHz
-0.9
–5
1.1
5
LSB
LSB
±2
-11
±1.5
0.02
11
mV
Offset temperature coefficient
mV/°C
∆offset error/∆AVDD from AVDD = 3 V to
AVDD = 3.6 V
DC power-supply rejection ratio, DC PSRR
0.25
mV/V
(1)
Gain error
-2
0.3
2
%FS
Gain temperature coefficient
–0.02
∆%/°C
(1) Gain error is specified by design and characterization; it is not tested in production.
3
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1dBFS differential input,
unless otherwise noted
=
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic AC Characteristics
25°C to 85°C
72.7
71.5
74.3
74.0
73.7
73.5
73
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
Full temp range
25°C to 85°C
71.5
70.0
Signal-to-noise ratio, SNR
RMS output noise
dBFS
LSB
dBc
Full temp range
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
72.9
71.9
70.7
1.1
92
Input tied to common-mode
25°C
80
78
fIN = 10 MHz
Full temp range
90
fIN = 55 MHz
fIN = 70 MHz
88
25°C
80
78
87
Spurious-free dynamic range, SFDR
Full temp range
86
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
88
85
77
25°C
80
78
92
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
Full temp range
90
88
25°C
80
78
87
Second-harmonic, HD2
dBc
Full temp range
86
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
88
85
77
25°C
80
78
89
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
Full temp range
88
79
25°C
80
78
85
Third-harmonic, HD3
dBc
dBc
Full temp range
83
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
fIN = 10 MHz
fIN = 70 MHz
83
80
76
25°C
88
Worst-harmonic/spur (other than HD2 and
HD3)
25°C
87
25°C to 85°C
Full temp range
72.2
71
73.8
73.5
73.2
73.2
72.5
72.5
71.8
69.8
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
25°C to 85°C
71
Signal-to-noise + distortion, SINAD
dBFS
Full temp range
69.5
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
4
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
=
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1dBFS differential input,
unless otherwise noted
PARAMETER
CONDITIONS
MIN
78
TYP
90
MAX
UNIT
25°C
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
Full temp range
76
88
83.4
86
25°C
78
76
Total harmonic distortion, THD
dBc
Full temp range
84
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
fIN = 70 MHz
83.4
81.2
75.8
11.9
93.8
92.4
Effective number of bits, ENOB
Bits
f = 10.1 MHz, 15.1 MHz (–7dBFS each tone)
f = 50.1 MHz, 55.1 MHz (–7dBFS each tone)
Two-tone intermodulation distortion, IMD
dBFS
dB
f = 148.1 MHz, 153.1 MHz (–7dBFS each
tone)
92.6
35
AC power supply rejection ratio, ACPSRR
Power Supply
Supply noise frequency ≤ 100 MHz
Total supply current, ICC
fIN = 70 MHz
fIN = 70 MHz
fIN = 70 MHz
Analog only
204
165
39
230
180
50
mA
mA
mA
Analog supply current, IAVDD
Output buffer supply current, IDRVDD
545
594
Power dissipation
Standby power
mW
mW
Output buffer power with 10-pF load on
digital output to ground
129
180
165
250
With Clocks running
DIGITAL CHARACTERISTICS
Valid over full recommended operating temperature range, AVDD = DRVDD = 3.3 V, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
VIH
VIL
IIH
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input current for RESET
Input capacitance
2.4
V
0.8
10
V
µA
µA
µA
pF
IIL
–10
–20
4
Digital Outputs
VOL
VOH
Low-level output voltage
CLOAD = 10 pF
CLOAD = 10 pF
0.3
3
0.4
V
V
High-level output voltage
Output capacitance
2.4
3
pF
5
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TIMING CHARACTERISTICS(1)(2)
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF, unless
otherwise noted
=
PARAMETER
DESCRIPTION
MIN
TYP
MAX UNIT
Switching Specification
tA
Aperture delay
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
Data valid(3) to 50% of CLKOUT rising edge
50% of CLKOUT rising edge to data becoming invalid(3)
1
300
4.2
3.0
3.8
ns
fs
Aperture jitter (uncertainty)
tSETUP Data setup time
tHOLD Data hold time
3.2
1.8
ns
ns
ns
tSTART Input clock to output data valid Input clock rising edge to data valid start delay
start(4)(5)
5.0
tEND
Input clock to output data valid Input clock rising edge to data valid end delay(4)(5)
end
8.4
7.1
11.0
ns
tJIT
tr
Output clock jitter
Uncertainty in CLKOUT rising edge, peak-to-peak
Rise time of CLKOUT from 20% to 80% of DRVDD
Fall time of CLKOUT from 80% to 20% of DRVDD
210
2.5
2.1
8.0
315
2.8
2.3
8.9
psPP
ns
Output clock rise time
Output clock fall time
tf
ns
tPDI
Input clock to output clock
delay
Input clock rising edge, zero crossing, to output clock rising
edge 50%
ns
tr
tf
Data rise time
Data fall time
Data rise time measured from 20% to 80% of DRVDD
Data fall time measured from 80% to 20% of DRVDD
5.8
4.4
6.6
5.3
ns
ns
Output enable(OE) to data
output delay
Time required for outputs to have stable timings with regard to
input clock(6) after OE is activated
1000 Clock
cycles
Time to valid data after coming out of software power down
Time to valid data after stopping and restarting the clock
Time for a sample to propagate to the ADC outputs
1000
1000
Clock
cycles
Wakeup time
Latency
17.5
Clock
cycles
(1) Timing parameters are ensured by design and characterization, and not tested in production.
(2) See Table 5 through Table 6 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.
(4) See the Output Information section for details on using the input clock for data capture.
(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 2). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
(6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
N + 3
N + 4
N + 2
Sample
N
Analog
Input
N + 1
N + 17
N + 16
N + 14
N + 15
Signal
t
A
Input Clock
t
START
t
PDI
Output Clock
t
su
Data Out
(D0−D11)
N − 17
N − 16
N − 15
N − 14
N − 13
N − 3
N − 2
N − 1
N
Data Invalid
t
t
END
h
17.5 Clock Cycles
A. It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above
timing matches closely with the specified values.
Figure 1. Timing Diagram
6
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RESET TIMING CHARACTERISTICS
Typical values given at TA = 25°C, min and max specified over the full recommended operating temperature range, AVDD
=
UNIT
ms
DRVDD = 3.3 V, and 3-VPP differential clock, unless otherwise noted
PARAMETER
DESCRIPTION
MIN
TYP MAX
Switching Specification
t1
Power-on delay
Delay from power-on of AVDD and DRVDD to RESET pulse
active
10
t2
t3
Reset pulse width
Register write delay
Power-up time
Pulse width of active RESET signal
2
2
µs
µs
Delay from RESET disable to SEN active
Delay from power-up of AVDD and DRVDD to output stable
40
ms
Power Supply
(AV , DRV
)
DD
DD
t . 10 ms
1
t . 2 ms
2
t . 2 ms
3
SEN Active
RESET (Pin 35)
Figure 2. Reset Timing Diagram
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The ADS5542 has a three-wire serial interface. The ADS5542 latches serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
•
•
•
•
•
•
Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.
Minimum width of data stream for a valid loading is 16 clocks.
Data is loaded at every 16th SCLK falling edge while SEN is low.
In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
Data can be loaded in multiples of 16-bit words within a single active SEN pulse.
The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
A3
A2
A1
A0
D11
D10
D9
D0
SDATA
ADDRESS
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
t
SLOADS
t
SEN
SLOADH
t
t
t
SCLK
WSCLK WSCLK
SCLK
t
t
h(D)
su(D)
SDATA
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
SYMBOL
tSCLK
PARAMETER
SCLK period
MIN(1) TYP(1) MAX(1)
UNIT
50
ns
tWSCLK
tSLOADS
tSLOADH
tDS
SCLK duty cycle
SEN to SCLK setup time
SCLK to SEN hold time
Data setup time
25%
50%
75%
8
6
8
6
ns
ns
ns
ns
tDH
Data hold time
(1) Min, typ, and max values are characterized, but not production tested.
Table 2. Serial Register Table(1)
A3 A2 A1 A0 D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
D1
D0
DESCRIPTION
TP<1> TP<0>
Test Mode
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
Normal mode of operation
All outputs forced to 0
0
All outputs forced to 1
(2)(3)
0
Each output bit toggles between 0 and 1.
Power Down
PDN
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
0
Normal mode of operation
1
Device is put in power-down (low-current) mode.
(1) The register contents default to the appropriate setting for normal operation up on RESET.
(2) The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode
outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section.
(3) While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D13. For
example, when D0 is a 1, D1 in not assured to be a 0, and vice versa.
Table 3. Data Format Select (DFS) Table
DFS-PIN VOLTAGE (VDFS
)
DATA FORMAT
CLOCK OUTPUT POLARITY
2
12
V
AV
AV
V
t
AV
DD
Straight Binary
Data valid on rising edge
DFS
DD
5
12
4
12
t V
t V
t
AV
AV
Two's Complement
Straight Binary
Data valid on rising edge
Data valid on falling edge
Data valid on falling edge
DD
DFS
8
12
7
12
t
DD
DD
DFS
10
12
u
AV
DD
Two's Complement
DFS
8
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
PIN CONFIGURATION
PAP PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
46
DRGND
SCLK
SDATA
SEN
DRGND
D3
3
D2
4
45 D1
AVDD
AGND
5
44 D0 (LSB)
43 CLKOUT
6
7
42
41
AVDD
AGND
DRGND
OE
ADS5542
8
PowerPAD
AVDD
CLKP
CLKM
AGND
9
40 DFS
10
11
12
39
38
37
AVDD
AGND
AVDD
AGND 13
AGND 14
AVDD 15
36 AGND
35 RESET
34 AVDD
16
33
AVDD
AGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
9
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PIN CONFIGURATION (continued)
PIN ASSIGNMENTS
TERMINAL
NO. OF
NAME
NO.
PINS
I/O DESCRIPTION
5, 7, 9, 15, 22,
24, 26, 28, 33,
34, 37, 39
AVDD
12
I
Analog power supply
6, 8, 12–14,
16, 18, 21, 23,
25, 27, 32, 36,
38
AGND
14
I
Analog ground (PowerPAD is connected to analog ground.)
DRVDD
DRGND
49, 58
2
6
I
I
Output driver power supply
Output driver ground
1, 42, 48, 50,
57, 59
INP
19
20
29
30
31
17
35
41
40
10
11
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
Differential analog input (positive)
Differential analog input (negative)
INM
REFP
REFM
IREF
CM
O
O
I
Reference voltage (positive); 1-µF capacitor in series with a 1-Ω resistor to GND
Reference voltage (negative); 1-µF capacitor in series with a 1-Ω resistor to GND
Current set; 56.2-kΩ resistor to GND; do not connect capacitors
Common-mode output voltage
O
I
(1)
RESET
OE
Reset (active high), Internal 200-kΩ resistor to AVDD
Output enable (active high)(2)
Data format and clock out polarity select(3)(2)
Data converter differential input clock (positive)
Data converter differential input clock (negative)
Serial interface chip select(2)
I
DFS
I
CLKP
CLKM
SEN
I
I
I
SDATA
SCLK
3
I
Serial interface data(2)
Serial interface clock(2)
2
I
D0 (LSB) to
D13 (MSB)
44-47, 51-56,
60-63
14
O
Parallel data output
OVR
64
43
1
1
O
O
Over-range indicator bit
CLKOUT
CMOS clock out in sync with data
(1) If unused, the RESET pin should be tied to AGND. See the serial programmine interface section for details.
(2) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins
must also run off the same supply voltage as DRVDD.
(3) Table 3defines the voltage levels for each mode selectable via the DFS pin.
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DEFINITION OF SPECIFICATIONS
Offset Error
Analog Bandwidth
The offset error is the difference, given in number of
LSBs, between the ADC's actual average idle
channel output code and the ideal average idle
channel output code. This quantity is often mapped
into mV.
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low frequency value.
Aperture Delay
Temperature Drift
The delay in time between the falling edge of the
input sampling clock and the actual time at which the
sampling occurs.
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per
degree Celsius of the parameter from TMIN to TMAX. It
is calculated by dividing the maximum deviation of
the parameter across the TMIN to TMAX range by the
difference (TMAX – TMIN).
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
Signal-to-Noise Ratio (SNR)
The duty cycle of a clock signal is the ratio of the
time the clock signal remains at a logic high (clock
pulse width) to the period of the clock signal. Duty
cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50%
duty cycle.
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and the first eight harmonics.
PS
SNR + 10Log
10 PN
Maximum Conversion Rate
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to Full-Scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
Signal-to-Noise and Distortion (SINAD)
The minimum sampling rate at which the ADC
functions.
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral
components including noise (PN) and distortion (PD),
but excluding dc.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog
input values spaced exactly 1LSB apart. The DNL is
the deviation of any single step from this ideal value,
measured in units of LSBs.
PS
SINAD + 10Log
10 PN ) PD
(1)
Integral Nonlinearity (INL)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
The INL is the deviation of the ADC's transfer
function from a best fit line determined by a least
squares curve fit of that transfer function, measured
in units of LSBs.
Effective Number of Bits (ENOB)
Gain Error
The ENOB is
performance as compared to the theoretical limit
based on quantization noise.
a
measure of
a
converter's
The gain error is the deviation of the ADC's actual
input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input
full-scale range. Gain error does not account for
variations in the internal reference voltages (see the
Electrical Specifications section for limits on the
variation of VREFP and VREFM).
SINAD * 1.76
ENOB +
6.02
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Total Harmonic Distortion (THD)
Two-Tone Intermodulation Distortion (IMD3)
THD is the ratio of the power of the fundamental (PS)
to the power of the first eight harmonics (PD).
PS
THD + 10Log
10 PD
IMD3 is the ratio of the power of the fundamental (at
frequencies f1 and f2) to the power of the worst
spectral component at either frequency 2f1 – f2 or
2f2 – f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to Full-Scale)
when the power of the fundamental is extrapolated to
the converter's full-scale range.
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc
(dB to carrier).
DC Power Supply Rejection Ration (DC PSRR)
The DC PSSR is the ratio of the change in offset
error to a change in analog supply voltage. The DC
PSRR is typically given in units of mV/V.
Reference Error
The reference error is the variation of the actual
reference voltage (VREFP - VREFM) from its ideal
value. The reference error is typically given as a
percentage.
Voltage Overload Recovery Time
The voltage overload recovery time is defined as the
time required for the ADC to recover to within 1% of
the full-scale range in response to an input voltage
overload of 10% beyond the full-scale range.
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TYPICAL CHARACTERISTICS
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPS
and 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 4 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 16 MHz Input Signal)
0
20
40
60
80
0
20
40
60
80
SFDR = 92.1dBc
SNR = 74.0dBFS
THD = 88.4dBc
SFDR = 92.0dBc
SNR = 73.6dBFS
THD = 88.2dBc
−
−
−
−
−
−
−
−
SINAD = 73.9dBFS
SINAD = 73.5dBFS
−
−
−
−
100
120
100
120
0
0
0
5
5
5
10
15
20
25
30
35
40
0
0
0
5
10
15
20
25
30
35
40
40
40
−
−
−
−
f
Frequency MHz
f
Frequency MHz
Figure 5.
Figure 6.
SPECTRAL PERFORMANCE
(FFT for 55 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 70 MHz Input Signal)
0
0
SFDR = 87.5dBc
SNR = 73.6dBFS
THD = 83.4dBc
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
SINAD = 73.2dBFS
−
−
−
−
100
120
100
120
10
15
20
25
30
35
40
5
10
15
20
25
30
35
−
−
f
Frequency MHz
−
−
f
Frequency MHz
Figure 7.
Figure 8.
SPECTRAL PERFORMANCE
(FFT for 100 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 125 MHz Input Signal)
0
0
SFDR = 87.2dBc
SNR = 72.8dBFS
THD = 83.4dBc
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
SINAD = 72.5dBFS
−
−
−
−
100
120
100
120
10
15
20
25
30
35
40
5
10
15
20
25
30
35
−
−
−
−
f
Frequency MHz
f
Frequency MHz
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPS
and 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 150 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 220 MHz Input Signal)
0
20
40
60
80
0
20
40
60
80
SFDR = 78.4dBc
SNR = 70.7dBFS
THD = 75.8dBc
−
−
−
−
−
−
−
−
SINAD = 69.8dBFS
−
−
−
−
100
120
100
120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
−
−
f
Frequency MHz
−
−
f
Frequency MHz
Figure 11.
Figure 12.
SPECTRAL PERFORMANCE
(FFT for 300 MHz Input Signal)
TWO-TONE INTERMODULATION
0
0
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
100
120
100
120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
−
−
−
−
f
Frequency MHz
f
Frequency MHz
Figure 13.
Figure 14.
TWO-TONE INTERMODULATION
TWO-TONE INTERMODULATION
0
0
−
f1 = 45.1MHz ( 7dBFS)
−
f2 = 50.1MHz ( 7dBFS)
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
2−Tone SFDR = 91.6dBc
−
−
−
−
100
120
100
120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
−
−
f
Frequency MHz
−
−
f
Frequency MHz
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPS
and 3-V differential clock, unless otherwise noted
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
1.0
0.8
0.6
0.4
0.2
0
2.0
1.5
1.0
0.5
0
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
0.5
1.0
1.5
2.0
0
2048 4096 6144 8192 10240 12288 14336 16384
Code
0
2048 4096 6144 8192 10240 12288 14336 16384
Code
Figure 17.
Figure 18.
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs INPUT FREQUENCY
100
95
90
85
80
75
70
65
60
76
75
74
73
72
71
70
69
68
67
0
50
100
150
200
250
300
0
50
100
150
200
250
300
−
−
Frequency MHz
Frequency MHz
Figure 19.
Figure 20.
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
100
95
90
85
80
72
70
65
60
98
94
90
86
82
48
74
70
66
fIN = 150MHz
fIN = 70MHz
SFDR
SFDR
SNR
SNR
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−
−
−
−
AVDD Analog Supply Voltage
V
AVDD Analog Supply Voltage V
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPS
and 3-V differential clock, unless otherwise noted
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
95
90
85
80
75
70
65
95
90
85
80
75
70
65
fIN = 150MHz
fIN = 70MHz
SFDR
SFDR
SNR
SNR
3.0
3.1
20
−
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−
−
−
−
DVDD Digital Supply Voltage
V
DVDD Digital Supply Voltage V
Figure 23.
Figure 24.
POWER DISSIPATION
vs SAMPLE RATE
POWER DISSIPATION
vs SAMPLE RATE
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
fIN = 70MHz
fIN = 150MHz
10
30
40
50
60
70
80
10
20
30
40
50
60
70
80
−
−
Sample Rate MSPS
Sample Rate MSPS
Figure 25.
Figure 26.
AC PERFORMANCE
vs TEMPERATURE
AC PERFORMANCE
vs INPUT AMPLITUDE
100
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
fIN = 70MHz
SNR (dBFS)
SFDR
SNR
SFDR (dBc)
SNR (dBc)
−
−
−
10
20
30
fIN = 70MHz
−
−
−
−
−
−
−
−
−
−
−
10
40
15
+10
+35
− _
+60
+85
100 90
80
70
60
50
40
30
20
0
Temperature
C
−
Input Amplitude dBFS
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1dBFS, sampling rate = 80 MSPS
and 3-V differential clock, unless otherwise noted
AC PERFORMANCE
vs INPUT AMPLITUDE
AC PERFORMANCE
vs INPUT AMPLITUDE
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
SNR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBc)
SNR (dBc)
SNR (dBc)
−
−
−
10
20
30
−
−
−
10
20
30
fIN = 220MHz
fIN = 150MHz
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10
100 90
80
70
60
50
40
30
20
10
0
100 90
80
70
60
50
40
30
20
0
3.0
60
−
−
Input Amplitude dBFS
Input Amplitude dBFS
Figure 29.
Figure 30.
OUTPUT
AC PERFORMANCE
vs CLOCK AMPLITUDE
NOISE HISTOGRAM
40
35
30
25
20
15
10
5
95
fIN = 70MHz
90
85
80
75
70
65
SFDR
SNR
0
0
0.5
1.0
1.5
2.0
2.5
−
Differential Clock Amplitude
V
Code
Figure 31.
Figure 32.
WCDMA
CARRIER
AC PERFORMANCE
vs CLOCK DUTY CYCLE
0
100
95
90
85
80
75
70
65
fIN = 20MHz
SFDR
−
20
40
60
80
−
−
−
−
−
−
100
120
140
SNR
0
5
10
15
20
25
30
35
40
40
45
50
55
−
−
−
Clock Duty Cycle %
f
Frequency MHz
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,
unless otherwise noted
SIGNAL-TO-NOISE RATIO (SNR)
74
100
90
80
70
60
50
40
30
20
10
70
74
69
72
70
68
66
64
62
73
71
72
70
74
69
71
73
72
66
65
70
68
69
67
66
74
71
64
68
65
67
69
70
100
72
73
66
63
50
150
200
250
300
Input Frequency (MHz)
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,
unless otherwise noted
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
87
100
81
85
81
90
85
80
75
70
65
81
85
79
67
87
90
80
70
60
50
40
30
20
10
75
87
71
87
85
85
85
73
79
91
87
89
85
69
77
87
85
81
87
89
83
85
79
81
77
71
75
91
73
83
85
89
87
81
85
69
71
73
91
83
81
75
79
87
73
87
85
77
87
89
91
75
81
85
81
77
150
83
79
71
50
100
200
250
300
Input Frequency (MHz)
Figure 36.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5542 is a low-power, 14-bit, 80 MSPS, CMOS, switched capacitor, pipeline ADC that operates from a
single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the
signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges
are used to propagate the sample through the pipeline every half clock cycle. This process results in a
datalatency of 17.5 clock cycles, after which the output data is available as a 14-bit parallel word, coded in either
straight offset binary or binary two's complement format.
INPUT CONFIGURATION
The analog input for the ADS5542 consists of a differential sample-and-hold architecture implemented using the
switched capacitor technique shown in Figure 37.
S
3a
L1
R1a
C1a
INP
INM
S
S
1a
CP1
CP3
S
2
R3
CA
L2
R1b
C1b
VINCM
1V
1b
CP2
CP4
S
3b
L , L : 6 nH − 10 nH effective
1
2
R
1a
, R : 5W − 8W
1b
C , C : 2.2 pF − 2.6 pF
1a 1b
CP , CP : 2.5 pF − 3.5 pF
1
2
CP , CP : 1.2 pF − 1.8 pF
3
4
C : 0.8 pF − 1.2 pF
A
R : 80 W − 120 W
3
Swithches: S , S
On Resistance: 35 W − 50 W
1a 1b:
S : On Resistance: 7.5 W − 15 W
2
S
, S : On Resistance: 40 W − 60 W
3a 3b
All switches OFF Resistance: 10 GW
A. All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 37. Analog Input Stage
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This differential input topology produces a high level of ac-performance for high sampling rates. It also results in
a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling
applications. The ADS5542 requires each of the analog inputs (INP, INM) to be externally biased around the
common-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differential
lines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575 V and CM – 0.575 V. This
means that each input is driven with a signal of up to CM ± 0.575 V, so that each input has a maximum
differential signal of 1.15 VPP for a total differential input signal swing of 2.3 VPP. The maximum swing is
determined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM,
pin 30).
The ADS5542 obtains optimum performance when the analog inputs are driven differentially. The circuit shown
in Figure 38 shows one possible configuration using an RF transformer.
R0
Z0
W
W
W
50
W
25
50
INP
1:1
R
50
AC Signal
Source
ADS5542
W
25
INM
CM
ADT1−1WT
W
10
m
0.1 F
1nF
Figure 38. Transformer Input to Convert Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of an RF transformer. Since the input signal must be
biased around the common-mode voltage of the internal circuitry, the common-mode voltage (VCM) from the
ADS5542 is connected to the center-tap of the secondary winding. To ensure a steady low-noise VCM reference,
best performance is obtained when the CM (pin 17) output is filtered to ground with 0.1 µF and 0.001-µF
low-inductance capacitors.
Output VCM (pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be aware
that the input structure of the ADC sinks a common-mode current in the order of 400 µA (200 µA per input) at 80
MSPS. Equation 2 describes the dependency of the common-mode current and the sampling frequency:
400mA fS (in MSPS)
80 MSPS
(2)
Where:
fS > 2MSPS.
This equation helps to design the output capability and impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without
a transformer, to drive the input of the ADS5542. Texas Instruments offers a wide selection of single-ended
operational amplifiers (including the THS3201, THS3202, OPA695, and OPA847) that can be selected
depending on the application. An RF gain block amplifier, such as Texas Instruments THS9001, can also be
used with an RF transformer for high input frequency applications. The THS4503 is a recommended differential
input/output amplifier. Table 4 lists the recommended amplifiers.
When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA695, or OPA847) to
provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF
transformer and one amplifier in each of the legs of the secondary driving the two differential inputs of the
ADS5542. These three amplifier circuits minimize even-order harmonics. For high frequency inputs, an RF gain
block amplifier can be used to drive a transformer primary; in this case, the transformer secondary connections
can drive the input of the ADS5542 directly, as shown in Figure 38, or with the addition of the filter circuit shown
in Figure 39.
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Figure 39 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the
ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these
components be included in the ADS5542 circuit layout when any of the amplifier circuits discussed previously
are used. The components allow fine-tuning of the circuit performance. Any mismatch between the differential
lines of the ADS5542 input produces a degradation in performance at high input frequencies, mainly
characterized by an increase in the even-order harmonics. In this case, special care should be taken to keep as
much electrical symmetry as possible between both inputs.
Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that
can simplify the driver circuit for applications requiring dc-coupling of the input. Flexible in their configurations
(see Figure 40), such amplifiers can be used for single-ended-to-differential conversion signal amplification.
Table 4. Recommended Amplifiers to Drive the Input of the ADS5542
INPUT SIGNAL FREQUENCY
DC to 20 MHz
RECOMMENDED AMPLIFIER
THS4503
TYPE OF AMPLIFIER
Differential In/Out Amp
Operational Amp
USE WITH TRANSFORMER?
No
Yes
No
DC to 50 MHz
OPA847
DC to 100 MHz
THS4509
Differential In/Out Amp
Operational Amp
OPA695
Yes
Yes
Yes
Yes
10 MHz to 120 MHz
Over 100 MHz
THS3201
Operational Amp
THS3202
Operational Amp
THS9001
RF Gain Block
-
+5V 5V
RS
m
0.1 F
VIN
100 W
RIN
25 W
25 W
1:1
INP
OPA695
RT
100 W
CIN
1000pF
ADS5542
R1
400 W
INM
CM
RIN
AV = 8V/V
(18dB)
10 W
R2
57.5 W
m
0.1 F
Figure 39. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
RS
RG
RF
+5V
RT
+3.3V
m
m
10 F
0.1 F
RIN
RIN
INP
ADS5542
VOCM
14-Bit / 80 MSPS
INM
m
1 F
THS4503
CM
m
m
10 F
0.1 F
W
10
-
5V
RG
RF
m
0.1 F
Figure 40. Using the THS4503 with the ADS5542
22
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
POWER-SUPPLY SEQUENCE
The preferred power-up sequence is to ramp AVDD first, followed by DRVDD, including a simultaneous ramp of
AVDD and DRVDD. In the event that DRVDD ramps up first in the system, care must be taken to ensure that AVDD
ramps up within 10 ms. Optionally, it is recommended to put a 2-kΩ resistor from REFP (pin 29) to AVDD as
shown in Figure 41. This helps to make the device more robust to power supply ramp-up timings.
28
29
AVDD
REFP
2 kW
1 W
1 mF
Figure 41.
POWER-DOWN
The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit
throught the serial programming interface. Using the reduced clock speed, power-down may be initiated for clock
frequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to device.
Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and
only the internal reference remains on to reduce the power-up time. The power-down mode reduces power
dissipation to approximately 180 mW.
REFERENCE CIRCUIT
The ADS5542 has built-in internal reference generation, requiring no external circuitry on the printed circuit
board (PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1-µF
decoupling capacitor (the 1-Ω resistor shown in Figure 42 is optional). In addition, an external 56.2-kΩ resistor
should be connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as
shown in Figure 42. No capacitor should be connected between pin 31 and ground; only the 56.2-kΩ resistor
should be used.
1 W
REFP
REFM
IREF
29
30
31
1 mF
1 mF
1 W
56.2 kW
Figure 42. REFP, REFM, and IREF Connections for Optimum Performance
23
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
CLOCK INPUT
The ADS5542 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. The common-mode voltage of the clock inputs
is set internally to CM (pin 17) using internal 5-kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to
CM (pin 17), as shown in Figure 43.
CM
CM
5 kW
5 kW
CLKM
CLKP
6 pF
3 pF
3 pF
Figure 43. Clock Inputs
When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a
0.01-µF capacitor, while CLKP is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in
Figure 44.
m
0.01 F
Square Wave
or Sine Wave
CLKP
ADS5542
(3VPP
)
CLKM
m
0.01
F
Figure 44. AC-Coupled, Single-Ended Clock Input
The ADS5542 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this
case, it is best to connect both clock inputs to the differential input clock signal with 0.01-µF capacitors, as
shown in Figure 45.
m
0.01 F
CLKP
Differential Square Wave
or Sine Wave
(3VPP
ADS5542
CLKM
)
m
0.01 F
Figure 45. AC-Coupled, Differential Clock Input
For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, the
internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty
cycle should be provided. Figure 46 shows the performance variation of the ADC versus clock duty cycle.
24
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
100
95
90
85
80
75
70
65
60
fIN = 20MHz
SFDR
SNR
35
40
45
50
55
%
60
65
−
Clock Duty Cycle
Figure 46. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When
using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a
differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute
maximum ratings of the ADC clock input. Figure 47 shows the performance variation of the device versus input
clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see the
ADS55xxEVM User's Guide (SLWU010), available for download from www.ti.com.
95
fIN = 70MHz
90
85
SFDR
80
75
SNR
70
65
60
0
0.5
1.0
1.5
2.0
2.5
3.0
−
Differential Clock Amplitude
V
Figure 47. AC Performance vs Clock Amplitude
OUTPUT INFORMATION
The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals one when the output reaches the
full-scale limits.
Two different output formats (straight offset binary or two's complement) and two different output clock polarities
(latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one
of four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, active
high) is provided to put the outputs into a high-impedance state.
25
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive
overdrive, the output code is 0x3FFF in straight offset binary output format, and 0x1FFF in 2's complement
output format. For a negative input overdrive, the output code is 0x0000 in straight offset binary output format
and 0x2000 in two's complement output format. These outputs to an overdrive signal are ensured through
design and characterization
The output circuitry of the ADS5542, by design, minimizes the noise produced by the data switching transients,
and, in particular, its coupling to the ADC analog circuitry. Output D4 (pin 51) senses the load capacitance and
adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in
the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have
nearly the same load as D4 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply
voltage or temperature. Placing external resistors in series with the outputs is not recommended.
The timing characteristics of the digital outputs change for sampling rates below the 80 MSPS maximum
sampling frequency. Table 5 and Table 6 show the values of various timing parameters for lower sampling
frequenies.
To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay, td, that
results in the desired setup or hold time. Use either of the following equations to calculate the value of td.
Desired setup time = td – tSTART
Desired hold time = tEND – td
Table 5. Timing Characteristics at Additional Sampling Frequencies
tSETUP (ns)
tHOLD (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
fS
(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
65
40
20
10
2
4.3
8.5
17
5.7
11
2
2.6
2.5
4
3
2.8
–1
4.5
1.5
2
8.3
8.9
11.8
14.5
21.6
31
6.6
7.5
7.5
7.2
8
5.5
7.3
7.6
6.4
7.8
8
3.5
4.7
6.5
19
25.7
51
–9.8
-30
185
9.5
8
27
-3
11.5
515
284
370
8
320
576
50
82
75
150
Table 6. Timing Characteristics at Additional Sampling Frequencies
CLKOUT Jitter,
Peak-to-Peak
tJIT (ps)
CLKOUT, Rise Time
tr (ns)
CLKOUT, Fall Time
tf (ns)
Input-to-Output Clock Delay
tPDI (ns)
fS
(MSPS)
MIN
TYP
3.1
4.8
8.3
MAX
MIN
TYP
2.6
4
MAX
MIN
TYP
260
445
800
MAX
380
MIN
7.8
9.5
13
TYP
8.5
MAX
9.4
65
40
20
10
2
3.5
5.3
9.5
2.9
4.4
8.2
650
10.4
15.5
20.7
551
11.4
18
7.6
1200
16
25.5
567
31
52
36
65
2610
4400
537
SERIAL PROGRAMMING INTERFACE
The ADS5542 has internal registers for the programming of some of the modes described in the previous
sections. The registers should be reset after power-up by applying a 2 us (minimum) high pulse on RESET (pin
35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200-kΩ internal pullup
resistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serial register
setting in the Serial Programing Interface section describe the programming of this register.
Table 2 shows the different modes and the bit values to be written to the register to enable them.
Note that some of these modes may modify the standard operation of the device and possibly vary the
performance with respect to the typical data shown in this data sheet.
26
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
Applying a RESET signal is absolutely essential to set the internal registers to their default states for normal
operation. If the hardware RESET function is not used in the system, the RESET pin must be tied to ground and
it is necessary to write the default values to the internal registers through the serial programming interface. The
following registers must be written in this order.
Write 9000h (Address 9, Data 000)
Write A000h (Address A, Data 000)
Write B000h (Address B, Data 000)
Write C000h (Address C, Data 000)
Write D000h (Address D, Data 000)
Write E000h (Address E, Data 804)
Write 0000h (Address 0, Data 000)
Write 1000h (Address 1, Data 000)
Write F000h (Address F, Data 000)
NOTE:
This procedure is only required if a RESET pulse is not provided to the device.
PowerPAD PACKAGE
The PowerPAD package is a thermally enhanced standard size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques and can be removed and replaced using standard
repair procedures.
The PowerPAD package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom
of the IC. This provides a low thermal resistance path between the die and the exterior of the package. The
thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the
PCB as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as
illustrated in the Mechanical Data section. The recommended thermal pad dimension is 8 mm x 8 mm.
2. Place a 5-by-5 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter.
The small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25 mil diameter holes under the package, but outside the
thermal pad area to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such
as a ground plane).
5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the
ground plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
application brief SLMA004B (PowerPAD Made Easy) or technical brief SLMA002 (PowerPAD Thermally
Enhanced Package).
27
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SBAS308D–MAY 2004–REVISED FEBRUARY 2007
Table 7. Revision History
Added notes regarding the input voltage overstress requirements in the absolute maximum ratings table
Changed minimum recommended sampling rate to 2 MSPS.
Added timing parameters - output clock jitter, wakeup time, output clock rise and fall time, Tpdi and timings across Fs.
Clarified output capture test modes.
Pin table info added - RESET pin, note on OE, SEN, SDATA and SCLK pins
Updated the definitions section.
Removed the input voltage stress section - notes added in absolute maximum ratings table
Updated the Power Down section to reflect the newly specified 2 MSPS minimum sampling rate.
Note added in Power supply sequence section for robust power supply ramp-up.
Note on mandatory RESET added
Rev D
Added min/max specs for Offset and Gain errors.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
PACKAGING INFORMATION
Orderable Device
ADS5542IPAP
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
HTQFP
HTQFP
PAP
64
64
160
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
-40 to 85 ADS5542I
ADS5542IPAPG4
ACTIVE
PAP
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
-40 to 85
ADS5542I
ADS5542I
ADS5542IPAPR
OBSOLETE
OBSOLETE
HTQFP
HTQFP
PAP
PAP
64
64
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
ADS5542IPAPRG4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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