ADS5545IRGZ [TI]
14-BITS, 170 MSPS ADC WITH LVDS/CMOS OUTPUTS; 14位， 170 MSPS ADC，具有LVDS / CMOS输出
| 型号： | ADS5545IRGZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-BITS, 170 MSPS ADC WITH LVDS/CMOS OUTPUTS |
| 文件： | 总8页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5545
www.ti.com
SLWS180–SEPTEMBER 2005
14-BITS, 170 MSPS ADC WITH LVDS/CMOS OUTPUTS
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
Wireless Communication
Software Defined Radio
•
•
•
•
Maximum Sample Rate: 170 MSPS
14-Bit Resolution
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
No Missing Codes
Power Dissipation
– Core Power: 1 W
– Total Power: 1.22 W
•
•
•
•
•
Internal Sample and Hold
73.5-dBFS SNR at 70-MHz IF
85-dBc SFDR at 70-MHz IF
Parallel CMOS and LVDS Output Options
Radar Systems
Internal Reference, External Reference
Support
•
•
3.3-V Analog and Digital Supply
48-Pin QFN Package (7 mm × 7 mm)
DESCRIPTION
The ADS5545 is a high performance 14-bit 170-MSPS ADC. Using an internal sample and hold and low jitter
clock buffer this ADC supports high SNR and high SFDR at high IF. With programmable options for parallel
CMOS and LVDS outputs, this device is available in a compact 48-pin QFN package. The device provides
internal references or can optionally be driven with an external reference. The device is specified over a –40°C to
85°C operating range.
CLKP
PLL
CLKOUT
CLKM
INP
INM
DIGITAL
ENCODER
SH
D13−D0
14-Bit ADC
OVR
REFERENCE
CONTROL I/F
VCMOUT/
REFIN
IN CMOS MODE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
Copyright © 2005, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
ADS5545
www.ti.com
SLWS180–SEPTEMBER 2005
PACKAG/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
PACKAGE-
PACKAGE
DESIGNATOR
PRODUCT
LEAD
ADS5545
48-QFN
RGZ
–40°C to 85°C
ADS5545IRGZ
(1) θJA = TBD, θJC = TBD
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.3 V to 3.9
–0.3 V to 3.9
–0.3 to 0.3
–0.3 to 3.3
–0.3 to 2
UNIT
AVDD
DRVDD Supply voltage range
Voltage between AGND and DRGND
Supply voltage range
V
V
V
V
V
Voltage between AVDD to DRVDD
Voltage applied to external pin
CM
Voltage applied to analog input pins
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
–0.3 V to minimum (3.6, AVDD + 0.3 V )
V
TA
–40 to 85
125
°C
°C
°C
°C
TJ
Tstg
–65 to 150
220
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX UNIT
SUPPLIES AND REFERENCES
AVDD Analog supply voltage
3
3
3.3
3.3
3.6
3.6
V
V
DRVDD Digital supply voltage
CLOCK INPUT
Input clock sample rate
1
170 MSPS
Vpp
Input clock amplitude, differential
Input clock duty cycle
50%
Operating free-air temperature
–40
85
°C
ELECTRICAL CHARACTERISTICS
Typical values at 25°C, min, max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD
= 3.3 V, sampling rate = 170 MSPS, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, LVDS
data output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
Resolution
14
Assured
0.5
bits
No missing codes
DNL
INL
Differential non-linearity
Integral non-linearity
Offset error
–0.9
TBD
LSB
LSB
±3
±10
mV
Offset temperature coefficient
Gain error
TBD
±1
ppm/°C
%FS
∆/°C
Gain temperature coefficient
TBD
2
ADS5545
www.ti.com
SLWS180–SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
Typical values at 25°C, min, max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD
= 3.3 V, sampling rate = 170 MSPS, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, LVDS
data output (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
ICC
Total supply current
FIN = TBD
FIN = TBD
369
315
54
mA
mA
mA
mA
W
IAVDD
Analog supply current
LVDS mode, FIN = TBD, CL = 5 pF
CMOS mode, FIN = TBD, CL = 5 pF
LVDS mode, FIN = TBD
IDRVDD Digital supply current
70
Total power dissipation
Power down dissipation
1.22
TBD
Clock running
mW
REFERENCE VOLTAGES
VREFB
VREFT
VCM
Reference bottom
0.5
2.5
1.5
±4
V
V
Reference top
Common mode voltage (internal)
VCM output current
V
mA
ANALOG INPUT
Differential input capacitance
7
VCM ± 0.1
2
pF
V
Analog input common mode range
Differential input voltage range
Analog input bandwidth
Vpp
MHz
–3 dB, source impedance 50 Ω
400
DYNAMIC AC CHARACTERISTICS
FIN = 10 MHz
FIN = 70 MHz
FIN = 150 MHz
FIN = 10 MHz
FIN = 70 MHz
FIN = 150 MHz
90
85
SFDR
SNR
Spurious free dynamic range
Signal-to-noise ratio
dBc
84
74
73.5
72
dBFS
3
ADS5545
www.ti.com
SLWS180–SEPTEMBER 2005
DIGITAL CHARACTERISTICS
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω.(1)
All LVDS and CMOS specifications are characterized, but not tested at production.
PARAMETER
DIGITAL INPUTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
2.4
V
0.8
V
10
10
4
µA
µA
pF
DIGITAL OUTPUTS – CMOS MODE
High-level output voltage
Low-level output voltage
Output capacitance
3.3
0
V
V
Output capacitance inside the device, from either
output to ground
4
pF
DIGITAL OUTPUTS – LVDS MODE
High-level output voltage
1375
1025
350
1200
4
mV
mV
mV
mV
pF
Low-level output voltage
Output differential voltage, |VOD
VOS Output offset voltage(1)
Output capacitance
|
Common-mode voltage of OUTP and OUTM
Output capacitance inside the device, from either
output to ground
Change in |VOD|, |∆VOD
|
25
25
mV
mV
Change in |VOS|, |∆VOS
|
(1) IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
0
−10
F = 170 MSPS
S
−20
−30
F
= 10.1 MHz
IN
SFDR = 91.5 dBc
SNR = 74.09
dBFS
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
0
10
20
30
40
50
60
70
80
Figure 1. ADS5545 FFT Plot at 170 MSPS and 10-MHz Input
4
ADS5545
www.ti.com
SLWS180–SEPTEMBER 2005
0
−10
F = 170 MSPS
S
−20
F
= 70.1 MHz
−30
IN
−40
SFDR = 87.8 dBc
SNR = 73.5 dBFS
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
0
10
20
30
40
50
60
70
80
Figure 2. ADS5545 FFT Plot at 170 MSPS and 70-MHz Input
5
PACKAGE OPTION ADDENDUM
www.ti.com
21-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
ADS5545IRGZ
PREVIEW
QFN
RGZ
48
250
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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