ADC12D1800RF [TI]
ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC; ADC12D1800RF 12位，单3.6 GSPS RF采样ADC
| 型号： | ADC12D1800RF |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC |
| 文件： | 总68页 (文件大小：2454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC12D1800RF
ADC12D1800RF 12-Bit, Single 3.6 GSPS RF Sampling ADC
Literature Number: SNAS518F
October 17, 2011
ADC12D1800RF
12-Bit, Single 3.6 GSPS RF Sampling ADC
1.0 General Description
3.0 Features
The 12-bit 1.8 GSPS ADC12D1800RF is an RF-sampling
GSPS ADC that can directly sample input frequencies up to
and above 2.7 GHz. The ADC12D1800RF augments the very
large Nyquist zone of National’s GSPS ADCs with excellent
noise and linearity performance at RF frequencies, extending
its usable range beyond the 3rd Nyquist zone.
Excellent noise and linearity up to and above fIN = 2.7 GHz
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Configurable to either 3.6 GSPS interleaved or 1800
MSPS dual ADC
New DESCLKIQ Mode for high bandwidth, high sampling
rate apps
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Pin-compatible with ADC1xD1x00, ADC12Dx00RF
AutoSync feature for multi-chip synchronization
Internally terminated, buffered, differential analog inputs
Interleaved timing automatic and manual skew adjust
Test patterns at output for system debug
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The ADC12D1800RF provides a flexible LVDS interface
which has multiple SPI programmable options to facilitate
board design and FPGA/ASIC data capture. The LVDS out-
puts are compatible with IEEE 1596.3-1996 and supports
programmable common mode voltage. The product is pack-
aged in a lead-free 292-ball thermally enhanced BGA pack-
age over the rated industrial temperature range of -40°C to
+85°C.
Time Stamp feature to capture external trigger
Programmable gain, offset, and tAD adjust feature
1:1 non-demuxed or 1:2 demuxed LVDS outputs
To achieve the full rated performance for Fclk > 1.6 GHz,
it is necessary to write the max power settings once to
Register 6h via the Serial Interface; see Section 19.0 Reg-
ister Definitions for more information.
4.0 Key Specifications
Resolution
12 Bits
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Interleaved 3.6 GSPS ADC
2.0 Applications
IMD3 (Fin = 2.7GHz @ -13dBFS)
IMD3 (Fin = 2.7GHz @ -16dBFS)
Noise Floor Density
Power
-62 dBc (typ)
-64 dBc (typ)
-155.0 dBm/Hz (typ)
4.29 W (typ)
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3G/4G Wireless Basestation
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Receive Path
DPD Path
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Wideband Microwave Backhaul
RF Sampling Software Defined Radio
Military Communications
SIGINT
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Dual 1800 MSPS ADC, Fin = 498 MHz
ENOB
SNR
SFDR
Power per Channel
9.3 Bits (typ)
58.1 dB (typ)
71.7 dBc (typ)
2.15 W (typ)
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RADAR / LIDAR
Wideband Communications
Consumer RF
Test and Measurement
5.0 Block Diagram
30164311
© 2011 National Semiconductor Corporation
301643
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6.0 RF Performance
-40
-50
-60
-70
-80
-90
-100
-7 dBFS
-10 dBFS
-13 dBFS
-16 dBFS
0
1
2
3
4
INPUT FREQUENCY (GHz)
30164398
ADC12D1800RF Non-DES Mode IMD3
0
-30
Fin = 2.7 GHz
-60
-90
-120
905 910 915 920 925 930 935 940
FREQUENCY (MHz)
30164314
ADC12D1800RF DES Mode FFT
CW Blocker: Fin = 2675 MHz; Total Power = -13 dBFS
WCDMA Blocker: Fc = 2685 MHz; Bandwidth = 3.84 MHz; Total Power = -13 dBFS
IMD3 Product Power = -75 dBFS
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7.0 Connection Diagram
30164301
FIGURE 1. ADC12D1800RF Connection Diagram
The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance.
See Section 18.5 SUPPLY / GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS for more information.
8.0 Ordering Information
Industrial Temperature Range (-40°C < TA < +85°C)
ADC12D1800RFIUT/NOPB
NS Package
Lead-free 292-Ball BGA Thermally Enhanced Package
Leaded 292-Ball BGA Thermally Enhanced Package
Reference Board
ADC12D1800RFIUT
ADC12D1800RFRB
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Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 Features ........................................................................................................................................ 1
4.0 Key Specifications ........................................................................................................................... 1
5.0 Block Diagram ................................................................................................................................ 1
6.0 RF Performance .............................................................................................................................. 2
7.0 Connection Diagram ........................................................................................................................ 3
8.0 Ordering Information ....................................................................................................................... 3
9.0 Ball Descriptions and Equivalent Circuits ............................................................................................ 7
10.0 Absolute Maximum Ratings ........................................................................................................... 16
11.0 Operating Ratings ....................................................................................................................... 16
12.0 Converter Electrical Characteristics ................................................................................................ 17
13.0 Specification Definitions ................................................................................................................ 28
14.0 Transfer Characteristic ................................................................................................................. 30
15.0 Timing Diagrams ......................................................................................................................... 31
16.0 Typical Performance Plots ............................................................................................................ 34
17.0 Functional Description .................................................................................................................. 39
17.1 OVERVIEW ......................................................................................................................... 39
17.2 CONTROL MODES .............................................................................................................. 39
17.2.1 Non-Extended Control Mode ........................................................................................ 39
17.2.1.1 Dual Edge Sampling Pin (DES) ........................................................................... 39
17.2.1.2 Non-Demultiplexed Mode Pin (NDM) ................................................................... 39
17.2.1.3 Dual Data Rate Phase Pin (DDRPh) .................................................................... 40
17.2.1.4 Calibration Pin (CAL) ......................................................................................... 40
17.2.1.5 Calibration Delay Pin (CalDly) ............................................................................ 40
17.2.1.6 Power Down I-channel Pin (PDI) ......................................................................... 40
17.2.1.7 Power Down Q-channel Pin (PDQ) ...................................................................... 40
17.2.1.8 Test Pattern Mode Pin (TPM) ............................................................................. 40
17.2.1.9 Full-Scale Input Range Pin (FSR) ....................................................................... 40
17.2.1.10 AC / DC-Coupled Mode Pin (VCMO) ................................................................... 40
17.2.1.11 LVDS Output Common-mode Pin (VBG) ............................................................. 40
17.2.2 Extended Control Mode ............................................................................................... 41
17.2.2.1 The Serial Interface ........................................................................................... 41
17.3 FEATURES ......................................................................................................................... 42
17.3.1 Input Control and Adjust .............................................................................................. 43
17.3.1.1 AC/DC-coupled Mode ........................................................................................ 43
17.3.1.2 Input Full-Scale Range Adjust ............................................................................ 43
17.3.1.3 Input Offset Adjust ............................................................................................ 43
17.3.1.4 DES/Non-DES Mode ......................................................................................... 43
17.3.1.5 DES Timing Adjust ............................................................................................ 44
17.3.1.6 Sampling Clock Phase Adjust ............................................................................. 44
17.3.2 Output Control and Adjust ............................................................................................ 44
17.3.2.1 SDR / DDR Clock ............................................................................................. 44
17.3.2.2 LVDS Output Differential Voltage ........................................................................ 45
17.3.2.3 LVDS Output Common-Mode Voltage ................................................................. 45
17.3.2.4 Output Formatting ............................................................................................. 45
17.3.2.5 Demux/Non-demux Mode .................................................................................. 45
17.3.2.6 Test Pattern Mode ............................................................................................ 45
17.3.2.7 Time Stamp ..................................................................................................... 45
17.3.3 Calibration Feature ..................................................................................................... 45
17.3.3.1 Calibration Control Pins and Bits ......................................................................... 46
17.3.3.2 How to Execute a Calibration .............................................................................. 46
17.3.3.3 Power-on Calibration ......................................................................................... 46
17.3.3.4 On-command Calibration ................................................................................... 46
17.3.3.5 Calibration Adjust .............................................................................................. 46
17.3.3.6 Read / Write Calibration Settings ........................................................................ 46
17.3.3.7 Calibration and Power-Down .............................................................................. 47
17.3.3.8 Calibration and the Digital Outputs ...................................................................... 47
17.3.4 Power Down .............................................................................................................. 47
18.0 Applications Information ............................................................................................................... 48
18.1 THE ANALOG INPUTS ......................................................................................................... 48
18.1.1 Acquiring the Input ...................................................................................................... 48
18.1.2 Driving the ADC in DES Mode ...................................................................................... 48
18.1.3 FSR and the Reference Voltage ................................................................................... 48
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18.1.4 Out-Of-Range Indication .............................................................................................. 48
18.1.5 Maximum Input Range ................................................................................................ 49
18.1.6 AC-coupled Input Signals ............................................................................................ 49
18.1.7 DC-coupled Input Signals ............................................................................................ 49
18.1.8 Single-Ended Input Signals .......................................................................................... 49
18.2 THE CLOCK INPUTS ........................................................................................................... 49
18.2.1 CLK Coupling ............................................................................................................. 49
18.2.2 CLK Frequency .......................................................................................................... 50
18.2.3 CLK Level .................................................................................................................. 50
18.2.4 CLK Duty Cycle .......................................................................................................... 50
18.2.5 CLK Jitter .................................................................................................................. 50
18.2.6 CLK Layout ................................................................................................................ 50
18.3 THE LVDS OUTPUTS ........................................................................................................... 50
18.3.1 Common-mode and Differential Voltage ......................................................................... 50
18.3.2 Output Data Rate ........................................................................................................ 50
18.3.3 Terminating Unused LVDS Output Pins ......................................................................... 50
18.4 SYNCHRONIZING MULTIPLE ADC12D1800RFS IN A SYSTEM ................................................ 50
18.4.1 AutoSync Feature ....................................................................................................... 51
18.4.2 DCLK Reset Feature ................................................................................................... 51
18.5 SUPPLY / GROUNDING, LAYOUT AND THERMAL RECOMMENDATIONS ................................ 52
18.5.1 Power Planes ............................................................................................................. 52
18.5.2 Bypass Capacitors ...................................................................................................... 52
18.5.3 Ground Planes ........................................................................................................... 52
18.5.4 Power System Example ............................................................................................... 52
18.5.5 Thermal Management ................................................................................................. 54
18.6 SYSTEM POWER-ON CONSIDERATIONS ............................................................................. 54
18.6.1 Power-on, Configuration, and Calibration ....................................................................... 54
18.6.2 Power-on and Data Clock (DCLK) ................................................................................. 56
18.7 RECOMMENDED SYSTEM CHIPS ........................................................................................ 56
18.7.1 Temperature Sensor ................................................................................................... 56
18.7.2 Clocking Device ......................................................................................................... 57
18.7.3 Amplifiers for Analog Input ........................................................................................... 57
18.7.4 Balun Recommendations for Analog Input ...................................................................... 57
19.0 Register Definitions ...................................................................................................................... 58
20.0 Physical Dimensions .................................................................................................................... 65
List of Figures
FIGURE 1. ADC12D1800RF Connection Diagram ............................................................................................ 3
FIGURE 2. LVDS Output Signal Levels ......................................................................................................... 28
FIGURE 3. Input / Output Transfer Characteristic ............................................................................................ 30
FIGURE 4. Clocking in 1:2 Demux Non-DES Mode* ......................................................................................... 31
FIGURE 5. Clocking in Non-Demux Non-DES Mode* ........................................................................................ 31
FIGURE 6. Clocking in 1:4 Demux DES Mode* ............................................................................................... 32
FIGURE 7. Clocking in Non-Demux Mode DES Mode* ...................................................................................... 32
FIGURE 8. Data Clock Reset Timing (Demux Mode) ........................................................................................ 33
FIGURE 9. Power-on and On-Command Calibration Timing ................................................................................ 33
FIGURE 10. Serial Interface Timing ............................................................................................................. 33
FIGURE 11. Serial Data Protocol - Read Operation .......................................................................................... 41
FIGURE 12. Serial Data Protocol - Write Operation .......................................................................................... 42
FIGURE 13. DDR DCLK-to-Data Phase Relationship ........................................................................................ 44
FIGURE 14. SDR DCLK-to-Data Phase Relationship ........................................................................................ 44
FIGURE 15. Driving DESIQ Mode ............................................................................................................... 48
FIGURE 16. AC-coupled Differential Input ..................................................................................................... 49
FIGURE 17. Single-Ended to Differential Conversion Using a Balun ...................................................................... 49
FIGURE 18. Differential Input Clock Connection .............................................................................................. 49
FIGURE 19. AutoSync Example ................................................................................................................. 51
FIGURE 20. Power and Grounding Example .................................................................................................. 53
FIGURE 21. HSBGA Conceptual Drawing ..................................................................................................... 54
FIGURE 22. Power-on with Control Pins set by Pull-up / down Resistors ................................................................ 55
FIGURE 23. Power-on with Control Pins set by FPGA pre Power-on Cal ................................................................ 55
FIGURE 24. Power-on with Control Pins set by FPGA post Power-on Cal ............................................................... 56
FIGURE 25. Supply and DCLK Ramping ....................................................................................................... 56
FIGURE 26. Typical Temperature Sensor Application ....................................................................................... 57
List of Tables
TABLE 1. Analog Front-End and Clock Balls ................................................................................................... 7
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TABLE 2. Control and Status Balls .............................................................................................................. 10
TABLE 3. Power and Ground Balls .............................................................................................................. 13
TABLE 4. High-Speed Digital Outputs .......................................................................................................... 14
TABLE 5. Package Thermal Resistance ........................................................................................................ 16
TABLE 6. Static Converter Characteristics ..................................................................................................... 17
TABLE 7. Dynamic Converter Characteristics ................................................................................................ 17
TABLE 8. Analog Input / Output and Reference Characteristics ............................................................................ 21
TABLE 9. I-Channel to Q-Channel Characteristics ............................................................................................ 22
TABLE 10. Sampling Clock Characteristics ................................................................................................... 22
TABLE 11. AutoSync Feature Characteristics ................................................................................................ 22
TABLE 12. Digital Control and Output Pin Characteristics ................................................................................... 23
TABLE 13. Power Supply Characteristics ...................................................................................................... 24
TABLE 14. AC Electrical Characteristics ........................................................................................................ 24
TABLE 15. Serial Port Interface ................................................................................................................. 26
TABLE 16. Calibration ............................................................................................................................. 26
TABLE 17. Non-ECM Pin Summary ............................................................................................................. 39
TABLE 18. Serial Interface Pins .................................................................................................................. 41
TABLE 19. Command and Data Field Definitions ............................................................................................. 41
TABLE 20. Features and Modes ................................................................................................................ 42
TABLE 21. Supported Demux, Data Rate Modes ............................................................................................. 45
TABLE 22. Test Pattern by Output Port in Demux Mode .................................................................................... 45
TABLE 23. Test Pattern by Output Port in Non-Demux Mode .............................................................................. 45
TABLE 24. Calibration Pins ....................................................................................................................... 46
TABLE 25. Unused Analog Input Recommended Termination ............................................................................. 48
TABLE 26. Unused AutoSync and DCLK Reset Pin Recommendation ................................................................... 51
TABLE 27. Temperature Sensor Recommendation .......................................................................................... 56
TABLE 28. Amplifier Recommendation ......................................................................................................... 57
TABLE 29. Balun Recommendations ............................................................................................................ 57
TABLE 30. Register Addresses .................................................................................................................. 58
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9.0 Ball Descriptions and Equivalent Circuits
TABLE 1. Analog Front-End and Clock Balls
Ball No.
Name
Equivalent Circuit
Description
Differential signal I- and Q-inputs. In the Non-Du-
al Edge Sampling (Non-DES) Mode, each I- and
Q-input is sampled and converted by its respec-
tive channel with each positive transition of the
CLK input. In Non-ECM (Non-Extended Control
Mode) and DES Mode, both channels sample the
I-input. In Extended Control Mode (ECM), the Q-
input may optionally be selected for conversion
in DES Mode by the DEQ Bit (Addr: 0h, Bit 6).
Each I- and Q-channel input has an internal com-
mon mode bias that is disabled when DC-cou-
pled Mode is selected. Both inputs must be either
AC- or DC-coupled. The coupling mode is se-
lected by the VCMO Pin.
H1/J1
N1/M1
VinI+/-
VinQ+/-
In Non-ECM, the full-scale range of these inputs
is determined by the FSR Pin; both I- and Q-
channels have the same full-scale input range. In
ECM, the full-scale input range of the I- and Q-
channel inputs may be independently set via the
Control Register (Addr: 3h and Addr: Bh).
The input offset may also be adjusted in ECM.
Differential Converter Sampling Clock. In the
Non-DES Mode, the analog inputs are sampled
on the positive transitions of this clock signal. In
the DES Mode, the selected input is sampled on
both transitions of this clock. This clock must be
AC-coupled.
U2/V1
CLK+/-
Differential DCLK Reset. A positive pulse on this
input is used to reset the DCLKI and DCLKQ
outputs of two or more ADC12D1800RFs in order
to synchronize them with other
ADC12D1800RFs in the system. DCLKI and
DCLKQ are always in phase with each other,
unless one channel is powered down, and do not
require a pulse from DCLK_RST to become
synchronized. The pulse applied here must meet
timing relationships with respect to the CLK input.
Although supported, this feature has been
superseded by AutoSync.
V2/W1
DCLK_RST+/-
7
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Ball No.
Name
Equivalent Circuit
Description
Common Mode Voltage Output or Signal
Coupling Select. If AC-coupled operation at the
analog inputs is desired, this pin should be held
at logic-low level. This pin is capable of sourcing/
sinking up to 100 µA. For DC-coupled operation,
this pin should be left floating or terminated into
high-impedance. In DC-coupled Mode, this pin
provides an output voltage which is the optimal
common-mode voltage for the input signal and
should be used to set the common-mode voltage
of the driving buffer.
VCMO
C2
Bandgap Voltage Output or LVDS Common-
mode Voltage Select. This pin provides a
buffered version of the bandgap output voltage
and is capable of sourcing / sinking 100 uA and
driving a load of up to 80 pF. Alternately, this pin
may be used to select the LVDS digital output
common-mode voltage. If tied to logic-high, the
1.2V LVDS common-mode voltage is selected;
0.8V is the default.
VBG
B1
External Reference Resistor terminals. A 3.3 kΩ
±0.1% resistor should be connected between
Rext+/-. The Rext resistor is used as a reference
to trim internal circuits which affect the linearity of
the converter; the value and precision of this
resistor should not be compromised.
C3/D3
Rext+/-
Input Termination Trim Resistor terminals. A 3.3
kΩ ±0.1% resistor should be connected between
Rtrim+/-. The Rtrim resistor is used to establish
the calibrated 100Ω input impedance of VinI,
VinQ and CLK. These impedances may be fine
tuned by varying the value of the resistor by a
corresponding percentage; however, the tuning
range and performance is not guaranteed for
such an alternate value.
C1/D2
Rtrim+/-
Temperature Sensor Diode Positive (Anode) and
Negative (Cathode) Terminals. This set of pins is
used for die temperature measurements. It has
not been fully characterized.
E2/F3
Tdiode+/-
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Ball No.
Name
Equivalent Circuit
Description
Reference Clock Input. When the AutoSync
feature is active, and the ADC12D1800RF is in
Slave Mode, the internal divided clocks are
synchronized with respect to this input clock. The
delay on this clock may be adjusted when
synchronizing multiple ADCs. This feature is
available in ECM via Control Register (Addr:
Eh).
Y4/W5
RCLK+/-
Reference Clock Output 1 and 2. These signals
provide a reference clock at a rate of CLK/4,
when enabled, independently of whether the
ADC is in Master or Slave Mode. They are used
to drive the RCLK of another ADC12D1800RF,
to enable automatic synchronization for multiple
ADCs (AutoSync feature). The impedance of
each trace from RCOut1 and RCOut2 to
Y5/U6
V6/V7
RCOut1+/-
RCOut2+/-
the RCLK of another ADC12D1800RF should be
100Ω differential. Having two clock outputs
allows the auto-synchronization to propagate as
a binary tree. Use the DOC Bit (Addr: Eh, Bit 1)
to enable/ disable this feature; default is disabled.
9
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TABLE 2. Control and Status Balls
Equivalent Circuit
Ball No.
Name
Description
Dual Edge Sampling (DES) Mode select. In the
Non-Extended Control Mode (Non-ECM), when
this input is set to logic-high, the DES Mode of
operation is selected, meaning that the VinI input
is sampled by both channels in a time-interleaved
manner. The VinQ input is ignored. When this
input is set to logic-low, the device is in Non-DES
Mode, i.e. the I- and Q-channels operate
independently. In the Extended Control Mode
(ECM), this input is ignored and DES Mode
selection is controlled through the Control
Register by the DES Bit (Addr: 0h, Bit 7); default
is Non-DES Mode operation.
V5
DES
Calibration Delay select. By setting this input
logic-high or logic-low, the user can select the
device to wait a longer or shorter amount of time,
respectively, before the automatic power-on self-
calibration is initiated. This feature is pin-
controlled only and is always active during ECM
and Non-ECM.
V4
CalDly
Calibration cycle initiate. The user can command
the device to execute a self-calibration cycle by
holding this input high a minimum of tCAL_H after
having held it low a minimum of tCAL_L. If this input
is held high at the time of power-on, the automatic
power-on calibration cycle is inhibited until this
input is cycled low-then-high. This pin is active in
both ECM and Non-ECM. In ECM, this pin is
logically OR'd with the CAL Bit (Addr: 0h, Bit 15)
in the Control Register. Therefore, both pin and
bit must be set low and then either can be set high
to execute an on-command calibration.
D6
CAL
Calibration Running indication. This output is
logic-high while the calibration sequence is
executing. This output is logic-low otherwise.
B5
CalRun
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Ball No.
Name
Equivalent Circuit
Description
Power Down I- and Q-channel. Setting either
input to logic-high powers down the respective I-
or Q-channel. Setting either input to logic-low
brings the respective I- or Q-channel to an
operational state after a finite time delay. This pin
is active in both ECM and Non-ECM. In ECM,
each Pin is logically OR'd with its respective Bit.
Therefore, either this pin or the PDI and PDQ Bit
in the Control Register can be used to power-
down the I- and Q-channel (Addr: 0h, Bit 11 and
Bit 10), respectively.
U3
V3
PDI
PDQ
Test Pattern Mode select. With this input at logic-
high, the device continuously outputs a fixed,
repetitive test pattern at the digital outputs. In the
ECM, this input is ignored and the Test Pattern
Mode can only be activated through the Control
Register by the TPM Bit (Addr: 0h, Bit 12).
A4
A5
Y3
TPM
NDM
FSR
Non-Demuxed Mode select. Setting this input to
logic-high causes the digital output bus to be in
the 1:1 Non-Demuxed Mode. Setting this input to
logic-low causes the digital output bus to be in the
1:2 Demuxed Mode. This feature is pin-controlled
only and remains active during ECM and Non-
ECM.
Full-Scale input Range select. In Non-ECM, this
input must be set to logic-high; the full-scale dif-
ferential input range for both I- and Q-channel
inputs is set by this pin. In the ECM, this input is
ignored and the full-scale range of the I- and Q-
channel inputs is independently determined by
the setting of Addr: 3h and Addr: Bh, respective-
ly. Note that the logic-high FSR value in Non-
ECM corresponds to the minimum allowed
selection in ECM.
DDR Phase select. This input, when logic-low,
selects the 0° Data-to-DCLK phase relationship.
When logic-high, it selects the 90° Data-to-DCLK
phase relationship, i.e. the DCLK transition
indicates the middle of the valid data outputs.
This pin only has an effect when the chip is in 1:2
Demuxed Mode, i.e. the NDM pin is set to logic-
low. In ECM, this input is ignored and the DDR
phase is selected through the Control Register by
the DPS Bit (Addr: 0h, Bit 14); the default is 0°
Mode.
W4
DDRPh
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Ball No.
Name
Equivalent Circuit
Description
Extended Control Enable bar. Extended feature
control through the SPI interface is enabled when
this signal is asserted (logic-low). In this case,
most of the direct control pins have no effect.
When this signal is de-asserted (logic-high), the
SPI interface is disabled, all SPI registers are
reset to their default values, and all available
settings are controlled via the control pins.
B3
ECE
Serial Chip Select bar. In ECM, when this signal
is asserted (logic-low), SCLK is used to clock in
serial data which is present on SDI and to source
serial data on SDO. When this signal is de-
asserted (logic-high), SDI is ignored and SDO is
in TRI-STATE.
C4
SCS
Serial Clock. In ECM, serial data is shifted into
and out of the device synchronously to this clock
signal. This clock may be disabled and held logic-
low, as long as timing specifications are not
violated when the clock is enabled or disabled.
C5
SCLK
Serial Data-In. In ECM, serial data is shifted into
the device on this pin while SCS signal is
asserted (logic-low).
B4
SDI
Serial Data-Out. In ECM, serial data is shifted out
of the device on this pin while SCS signal is
asserted (logic-low). This output is at TRI-STATE
when SCS is de-asserted.
A3
SDO
Do Not Connect. These pins are used for internal
purposes and should not be connected, i.e. left
floating. Do not ground.
D1, D7, E3, F4,
W3, U7
DNC
NC
NONE
NONE
Not Connected. This pin is not bonded and may
be left floating or connected to any potential.
C7
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TABLE 3. Power and Ground Balls
Equivalent Circuit
Ball No.
Name
Description
A2, A6, B6, C6,
D8, D9, E1, F1,
H4, N4, R1, T1,
U8, U9, W6, Y2,
Y6
Power Supply for the Analog circuitry. This
supply is tied to the ESD ring. Therefore, it must
be powered up before or with any other supply.
VA
NONE
NONE
G1, G3, G4, H2,
J3, K3, L3, M3,
N2, P1, P3, P4,
R3, R4
Power Supply for the Track-and-Hold and Clock
circuitry.
VTC
A11, A15, C18,
D11, D15, D17,
J17, J20, R17,
R20, T17, U11,
U15, U16, Y11,
Y15
VDR
NONE
Power Supply for the Output Drivers.
Power Supply for the Digital Encoder.
A8, B9, C8, V8,
W9, Y8
VE
NONE
NONE
Bias Voltage I-channel. This is an externally
decoupled bias voltage for the I-channel. Each
pin should individually be decoupled with a 100
nF capacitor via a low resistance, low inductance
path to GND.
J4, K2
L2, M4
VbiasI
Bias Voltage Q-channel. This is an externally
decoupled bias voltage for the Q-channel. Each
pin should individually be decoupled with a 100
nF capacitor via a low resistance, low inductance
path to GND.
VbiasQ
NONE
A1, A7, B2, B7,
D4, D5, E4, K1,
L1, T4, U4, U5,
W2, W7, Y1, Y7,
H8:N13
GND
NONE
NONE
Ground Return for the Analog circuitry.
F2, G2, H3, J2,
K4, L4, M2, N3,
P2, R2, T2, T3, U1
Ground Return for the Track-and-Hold and Clock
circuitry.
GNDTC
A13, A17, A20,
D13, D16, E17,
F17, F20, M17,
M20, U13, U17,
V18, Y13, Y17,
Y20
GNDDR
GNDE
NONE
NONE
Ground Return for the Output Drivers.
Ground Return for the Digital Encoder.
A9, B8, C9, V9,
W8, Y9
13
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TABLE 4. High-Speed Digital Outputs
Ball No.
Name
Equivalent Circuit
Description
Data Clock Output for the I- and Q-channel data
bus. These differential clock outputs are used to
latch the output data and, if used, should always
be terminated with a 100Ω differential resistor
placed as closely as possible to the differential
receiver. Delayed and non-delayed data outputs
are supplied synchronously to this signal. In 1:2
Demux Mode or Non-Demux Mode, this signal is
at ¼ or ½ the sampling clock rate, respectively.
DCLKI and DCLKQ are always in phase with
each other, unless one channel is powered down,
and do not require a pulse from DCLK_RST to
become synchronized.
K19/K20
L19/L20
DCLKI+/-
DCLKQ+/-
Out-of-Range Output for the I- and Q-channel.
This differential output is asserted logic-high
while the over- or under-range condition exists,
i.e. the differential signal at each respective
analog input exceeds the full-scale value. Each
OR result refers to the current Data, with which it
is clocked out. If used, each of these outputs
should always be terminated with a 100Ω
differential resistor placed as closely as possible
to the differential receiver. ORQ (Note 19).
K17/K18
L17/L18
ORI+/-
ORQ+/-
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14
Ball No.
Name
Equivalent Circuit
Description
J18/J19
H19/H20
H17/H18
G19/G20
G17/G18
F18/F19
E19/E20
D19/D20
D18/E18
C19/C20
B19/B20
B18/C17
·
M18/M19
N19/N20
N17/N18
P19/P20
P17/P18
R18/R19
T19/T20
U19/U20
U18/T18
V19/V20
W19/W20
W18/V17
DI11+/-
DI10+/-
DI9+/-
DI8+/-
DI7+/-
DI6+/-
DI5+/-
DI4+/-
DI3+/-
DI2+/-
DI1+/-
DI0+/-
·
DQ11+/-
DQ10+/-
DQ9+/-
DQ8+/-
DQ7+/-
DQ6+/-
DQ5+/-
DQ4+/-
DQ3+/-
DQ2+/-
DQ1+/-
DQ0+/-
I- and Q-channel Digital Data Outputs. In Non-
Demux Mode, this LVDS data is transmitted at
the sampling clock rate. In Demux Mode, these
outputs provide ½ the data at ½ the sampling
clock rate, synchronized with the delayed data,
i.e. the other ½ of the data which was sampled
one clock cycle earlier. Compared with the DId
and DQd outputs, these outputs represent the
later time samples. If used, each of these outputs
should always be terminated with a 100Ω
differential resistor placed as closely as possible
to the differential receiver.
A18/A19
B17/C16
A16/B16
B15/C15
C14/D14
A14/B14
B13/C13
C12/D12
A12/B12
B11/C11
C10/D10
A10/B10
·
Y18/Y19
W17/V16
Y16/W16
W15/V15
V14/U14
Y14/W14
W13/V13
V12/U12
Y12/W12
W11/V11
V10/U10
Y10/W10
DId11+/-
DId10+/-
DId9+/-
DId8+/-
DId7+/-
DId6+/-
DId5+/-
DId4+/-
DId3+/-
DId2+/-
DId1+/-
DId0+/-
·
DQd11+/-
DQd10+/-
DQd9+/-
DQd8+/-
DQd7+/-
DQd6+/-
DQd5+/-
DQd4+/-
DQd3+/-
DQd2+/-
DQd1+/-
DQd0+/-
Delayed I- and Q-channel Digital Data Outputs.
In Non-Demux Mode, these outputs are at TRI-
STATE. In Demux Mode, these outputs provide
½ the data at ½ the sampling clock rate,
synchronized with the non-delayed data, i.e. the
other ½ of the data which was sampled one clock
cycle later. Compared with the DI and DQ
outputs, these outputs represent the earlier time
samples. If used, each of these outputs should
always be terminated with a 100Ω differential
resistor placed as closely as possible to the
differential receiver.
15
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10.0 Absolute Maximum Ratings
(Note 1, Note 2)
11.0 Operating Ratings
(Note 1, Note 2)
Ambient Temperature Range
Supply Voltage (VA, VTC, VDR, VE)
2.2V
ADC12D1800RF (Standard
JEDEC thermal model)
Supply Difference
max(VA/TC/DR/E)-
−40°C ≤ TA ≤ +50°C
−40°C ≤ TA ≤ +85°C
ADC12D1800RF (Enhanced
thermal model / heatsink)
min(VA/TC/DR/E
)
0V to 100 mV
Voltage on Any Input Pin
(except VIN+/-)
−0.15V to
(VA + 0.15V)
Junction Temperature Range -
applies only to maximum operating
speed
VIN+/- Voltage Range
Ground Difference
-0.5V to 2.5V
TJ ≤ +120°C
+1.8V to +2.0V
Supply Voltage (VA, VTC, VE)
max(GNDTC/DR/E
)
Driver Supply Voltage (VDR
)
+1.8V to VA
-min(GNDTC/DR/E
)
0V to 100 mV
±50 mA
VIN+/- Voltage Range (Note 14)
-0.4V to 2.4V
(d.c.-coupled)
Input Current at Any Pin (Note 3)
ADC12D1800RF Package Power
Dissipation at TA ≤ 65°C (Note 3)
VIN+/- Differential Voltage Range
(Note 15)
1.0V (d.c.-coupled
@100% duty cycle)
2.0V (d.c.-coupled
@20% duty cycle)
2.8V (d.c.-coupled
@10% duty cycle)
4.95 W
ESD Susceptibility (Note 4)
Human Body Model
Charged Device Model
Machine Model
ꢀ
2500V
1000V
250V
VIN+/- Current Range (Note 14)
±50 mA peak
(a.c.-coupled)
Storage Temperature
−65°C to +150°C
VIN+/- Power
15.3 dBm
(maintaining
common mode
voltage, a.c.-
coupled)
17.1 dBm
( not maintaining
common mode
voltage, a.c.-
coupled)
Ground Difference
max(GNDTC/DR/E
)
-min(GNDTC/DR/E
)
0V
0V to VA
CLK+/- Voltage Range
Differential CLK Amplitude
Common Mode Input Voltage
0.4VP-P to 2.0VP-P
VCMO - 150mV <
VCMI < VCMO +150mV
TABLE 5. Package Thermal Resistance
Package
θJC2
θJA
θJC1
292-Ball BGA Thermally 16°C/W 2.9°C/W 2.5°C/W
Enhanced Package
Soldering
process
must
comply
with
National
Semiconductor’s Reflow Temperature Profile specifications.
Refer to www.national.com/packaging.
www.national.com
16
12.0 Converter Electrical Characteristics
Unless otherwise specified, the following apply after calibration for VA = VDR = VTC = VE = +1.9V; I- and Q-channels, AC-coupled,
unused channel terminated to AC ground, FSR Pin = High; CL = 10 pF; Differential, AC coupled Sine Wave Sampling Clock,
fCLK = 1.8 GHz at 0.5 VP-P with 50% duty cycle (as specified); VBG = Floating; Extended Control Mode with Register 6h written to
1C0Eh; Rext = Rtrim = 3300Ω ± 0.1%; Analog Signal Source Impedance = 100Ω Differential; 1:2 Demultiplex Non-DES Mode;
Duty Cycle Stabilizer on. Boldface limits apply for TA = TMIN to TMAX and for TJ < 105°C. All other limits TA = 25°C, unless
otherwise noted. (Note 5, Note 6, Note 7)
TABLE 6. Static Converter Characteristics
ADC12D1800RF
Units
(Limits)
Symbol
Parameter
Conditions
Typ
Lim
Resolution with No Missing Codes
12
bits
INL
Integral Non-Linearity
(Best fit)
1 MHz DC-coupled over-ranged
sine wave
±2.5
±0.4
LSB
DNL
Differential Non-Linearity
1 MHz DC-coupled over-ranged
sine wave
LSB
VOFF
Offset Error
5
LSB
mV
VOFF_ADJ
PFSE
Input Offset Adjustment Range
Positive Full-Scale Error
Negative Full-Scale Error
Extended Control Mode
(Note 8)
±45
±25
±25
4095
0
mV (max)
mV (max)
NFSE
(Note 8)
Out-of-Range Output Code (Note (VIN+) − (VIN−) > + Full Scale
9)
(VIN+) − (VIN−) < − Full Scale
TABLE 7. Dynamic Converter Characteristics
(Note 10)
ADC12D1800RF
Units
(Limits)
Symbol
Parameter
Conditions
Typ
Lim
Bandwidth
Non-DES Mode, DESCLKIQ Mode
-3 dB (Note 17)
-6 dB
2.7
3.1
3.5
4.0
GHz
GHz
GHz
GHz
-9 dB
-12 dB
DESI Mode, DESQ Mode
-3 dB (Note 17)
-6 dB
1.2
2.3
2.7
3.0
GHz
GHz
GHz
GHz
-9 dB
-12 dB
DESIQ Mode
-3 dB (Note 17)
-6 dB
1.75
2.7
GHz
GHz
17
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ADC12D1800RF
Typ Lim
Units
(Limits)
Symbol
Parameter
Gain Flatness
Conditions
Non-DES Mode
D.C. to Fs/2
D.C. to Fs
±0.4
±1.1
±1.7
±5.7
dB
dB
dB
dB
D.C. to 3Fs/2
D.C. to 2Fs
DESI, DESQ Mode
D.C. to Fs/2
D.C. to Fs
±2.7
±9.2
dB
dB
DESIQ Mode
D.C. to Fs/2
DESCLKIQ Mode
D.C. to Fs/2
±1.6
dB
dB
±1.2
10-18
CER
Code Error Rate
Error/
Sample
IMD3
3rd order Intermodulation
Distortion
DES Mode
FIN = 2670 MHz ± 2.5MHz
@ -13 dBFS
-75
-62
dBFS
dBc
FIN = 2070 MHz ± 2.5MHz
@ -13 dBFS
-85
dBFS
dBc
-72
FIN = 2670 MHz ± 2.5MHz
@ -16 dBFS
-80
dBFS
dBc
-64
FIN = 2070 MHz ± 2.5MHz
@ -16 dBFS
-83
dBFS
dBc
-67
Noise Floor Density
-155.0
-154.0
dBm/Hz
dBFS/Hz
50Ω single-ended termination,
DES Mode
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18
ADC12D1800RF
Units
(Limits)
Symbol
Parameter
Conditions
Typ
Lim
Non-DES Mode (Note 11, Note 13, Note 20)
ENOB
SINAD
SNR
Effective Number of Bits
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
9.3
9.3
bits
bits
9.3
8.4
bits (min)
bits
8.7
8.7
bits
Signal-to-Noise Plus Distortion
Ratio
57.7
57.7
57.7
54.1
54
dB
dB
52.1
52.9
-60
dB (min)
dB
dB
Signal-to-Noise Ratio
58.6
58.2
58.1
54.9
54.3
-64.9
-65.7
-67
dB
dB
dB (min)
dB
dB
THD
Total Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
dB
dB
dB (max)
dB
-61.5
-64.9
-68.8
-85.6
-72.5
-81.2
-70.4
-70.4
-67.5
-69.8
-70.4
-73
dB
2nd Harm
3rd Harm
SFDR
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Spurious-Free Dynamic Range AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
68.1
67
dBc
dBc
AIN = 498 MHz @ -0.5 dBFS
71.7
60
54
dBc (min)
dBc
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
61
dBc
19
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ADC12D1800RF
Typ Lim
Units
(Limits)
Symbol
Parameter
Conditions
DES Mode (Note 11, Note 12, Note 13, Note 20)
ENOB
SINAD
SNR
Effective Number of Bits
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
9
bits
bits
bits
bits
bits
dB
9
9.1
8.6
8.6
Signal-to-Noise Plus Distortion
Ratio
56
56
dB
56.5
53.6
53.6
57.2
57.3
57.3
54.7
54
dB
dB
dB
Signal-to-Noise Ratio
dB
dB
dB
dB
dB
THD
Total Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
-62.1
-61.6
-64
dB
dB
dB
-59.7
-62.8
-82
dB
dB
2nd Harm
3rd Harm
SFDR
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
-78.5
-71.1
-76.9
-75.3
-64.7
-62.5
-71.4
-60.4
-65.8
64.2
62.4
68.1
60.3
63.6
Spurious-Free Dynamic Range AIN = 125 MHz @ -0.5 dBFS
AIN = 248 MHz @ -0.5 dBFS
AIN = 498 MHz @ -0.5 dBFS
AIN = 1147 MHz @ -0.5 dBFS
AIN = 1448 MHz @ -0.5 dBFS
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20
TABLE 8. Analog Input / Output and Reference Characteristics
ADC12D1800RF
Units
(Limits)
Symbol
Parameter
Conditions
Typ
Lim
Analog Inputs
VIN_FSR
Analog Differential Input Full Scale Non-Extended Control Mode
Range
FSR Pin High
mVP-P
(min)
740
860
800
mVP-P
(max)
Extended Control Mode
FM(14:0) = 4000h (default)
FM(14:0) = 7FFFh
Differential
mVP-P
mVP-P
pF
800
1000
0.02
1.6
CIN
Analog Input Capacitance,
Non-DES Mode (Note 9, Note 16)
Each input pin to ground
Differential
pF
Analog Input Capacitance,
DES Mode (Note 9, Note 16)
0.08
2.2
pF
Each input pin to ground
pF
RIN
Differential Input Resistance
91
Ω (min)
Ω (max)
100
109
Common Mode Output
VCMO
Common Mode Output Voltage
ICMO = ±100 µA
1.15
1.35
V (min)
V (max)
1.25
38
TC_VCMO
VCMO_LVL
CL_VCMO
Common Mode Output Voltage
Temperature Coefficient
ICMO = ±100 µA (Note 10)
(Note 10)
ppm/°C
VCMO input threshold to set
DC-coupling Mode
0.63
V
Maximum VCMO Load Capacitance (Note 9)
80
pF
Bandgap Reference
VBG
Bandgap Reference Output
Voltage
IBG = ±100 µA
1.15
1.35
V (min)
V (max)
1.25
32
TC_VBG
CL_VBG
Bandgap Reference Voltage
Temperature Coefficient
IBG = ±100 µA (Note 10)
(Note 9)
ppm/°C
pF
Maximum Bandgap Reference
load Capacitance
80
21
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TABLE 9. I-Channel to Q-Channel Characteristics
ADC12D1800RF
Typ Lim
Units
(Limits)
Symbol
Parameter
Conditions
Offset Match
(Note 10)
2
LSB
Positive Full-Scale Match
Negative Full-Scale Match
Zero offset selected in
Control Register
2
LSB
Zero offset selected in
Control Register
2
LSB
Degree
dB
Phase Matching (I, Q)
fIN = 1.0 GHz (Note 10)
< 1
−70
X-TALK
Crosstalk from I-channel
Aggressor = 867 MHz F.S.
(Aggressor) to Q-channel (Victim) Victim = 100 MHz F.S.
Crosstalk from Q-channel Aggressor = 867 MHz F.S.
(Aggressor) to I-channel (Victim) Victim = 100 MHz F.S.
−70
dB
TABLE 10. Sampling Clock Characteristics
ADC12D1800RF
Units
(Limits)
Symbol
VIN_CLK
Parameter
Conditions
Typ
Lim
0.4
2.0
0.4
2.0
Differential Sampling Clock Input Sine Wave Clock
Level (Note 10) Differential Peak-to-Peak
VP-P (min)
VP-P (max)
VP-P (min)
VP-P (max)
pF
0.6
Square Wave Clock
Differential Peak-to-Peak
0.6
CIN_CLK
RIN_CLK
Sampling Clock Input Capacitance Differential
(Note 9)
0.1
1
Each input to ground
pF
Sampling Clock Differential Input (Note 10)
100
Ω
Resistance
TABLE 11. AutoSync Feature Characteristics
ADC12D1800RF
Units
(Limits)
Symbol
VIN_RCLK
Parameter
Conditions
Typ
Lim
Differential RCLK Input Level
Differential Peak-to-Peak
mVP-P
360
(Note 10)
CIN_RCLK
RCLK Input Capacitance (Note
10)
Differential
0.1
1
pF
pF
Each input to ground
(Note 10)
RIN_RCLK
IIH_RCLK
IIL_RCLK
RCLK Differential Input
Resistance
100
22
Ω
Input Leakage Current;
VIN = VA
µA
Input Leakage Current;
VIN = GND
-33
µA
VO_RCOUT
Differential RCOut Output Voltage
mV
360
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22
TABLE 12. Digital Control and Output Pin Characteristics
ADC12D1800RF
Units
(Limits)
Symbol
Parameter
Conditions
Typ
Digital Control Pins (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)
Lim
VIH
VIL
IIH
Logic High Input Voltage
Logic Low Input Voltage
0.7×VA
0.3×VA
V (min)
V (max)
Input Leakage Current;
VIN = VA
0.02
μA
μA
IIL
Input Leakage Current;
VIN = GND
FSR, CalDly, CAL, NDM, TPM,
DDRPh, DES
-0.02
SCS, SCLK, SDI
PDI, PDQ, ECE
-17
-38
μA
μA
CIN_DIG
Digital Control Pin Input
Capacitance (Note 9)
Measured from each control pin to
GND
1.5
630
460
pF
Digital Output Pins (Data, DCLKI, DCLKQ, ORI, ORQ)
VOD
LVDS Differential Output Voltage VBG = Floating, OVS = High
mVP-P
(min)
400
800
230
630
mVP-P
(max)
mVP-P
(min)
VBG = Floating, OVS = Low
mVP-P
(max)
mVP-P
VBG = VA, OVS = High
VBG = VA, OVS = Low
670
500
mVP-P
Change in LVDS Output Swing
Between Logic Levels
ΔVO DIFF
±1
mV
VOS
Output Offset Voltage (Note 10)
VBG = Floating
VBG = VA
0.8
1.2
V
V
Output Offset Voltage Change
Between Logic Levels
(Note 10)
ΔVOS
±1
mV
mA
IOS
Output Short Circuit Current (Note VBG = Floating;
10)
±4
D+ and D− connected to 0.8V
ZO
Differential Output Impedance
Logic High Output Level
(Note 10)
100
1.65
Ω
VOH
CalRun, IOH = −100 µA, (Note 10)
SDO, IOH = −400 µA (Note 10)
V
VOL
Logic Low Output Level
CalRun, IOL = 100 µA, (Note 10)
SDO, IOL = 400 µA (Note 10)
0.15
V
Differential DCLK Reset Pins (DCLK_RST)
VCMI_DRST
VID_DRST
RIN_DRST
DCLK_RST Common Mode Input (Note 10)
Voltage
1.25
VIN_CLK
100
V
Differential DCLK_RST Input
Voltage
(Note 10)
(Note 10)
VP-P
Differential DCLK_RST Input
Resistance
Ω
23
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TABLE 13. Power Supply Characteristics
ADC12D1800RF
Units
(Limits)
Symbol
Parameter
Conditions
Typ
Lim
IA
Analog Supply Current
PDI = PDQ = Low
1360
745
745
2.7
515
305
305
650
275
145
145
6
mA
mA
mA
mA
mA
mA
mA
µA
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
ITC
IDR
IE
Track-and-Hold and Clock Supply PDI = PDQ = Low
Current
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
Output Driver Supply Current
PDI = PDQ = Low
mA
mA
mA
µA
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
Digital Encoder Supply Current
PDI = PDQ = Low
110
65
mA
mA
mA
µA
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
65
34
ITOTAL
Total Supply Current
Power Consumption
1:2 Demux Mode
PDI = PDQ = Low
2260
2220
2481
4.7
mA (max)
mA
Non-Demux Mode
PDI = PDQ = Low
PC
1:2 Demux Mode
PDI = PDQ = Low
4.29
2.39
2.39
6.5
W (max)
W
PDI = Low; PDQ = High
PDI = High; PDQ = Low
PDI = PDQ = High
Non-Demux Mode
PDI = PDQ = Low
W
mW
4.22
W
TABLE 14. AC Electrical Characteristics
ADC12D1800RF
Units
(Limits)
Symbol
Parameter
Conditions
Typ
Lim
Sampling Clock (CLK)
fCLK (max)
Maximum Sampling Clock
Frequency
1.8
GHz
fCLK (min)
Minimum Sampling Clock
Frequency
Non-DES Mode; LFS = 0b
Non-DES Mode; LFS = 1b
DES Mode
300
150
500
20
MHz
MHz
MHz
Sampling Clock Duty Cycle
% (min)
% (max)
ps (min)
ps (min)
fCLK(min) ≤ fCLK ≤ fCLK(max)
(Note 10)
50
80
tCL
tCH
Sampling Clock Low Time
Sampling Clock High Time
(Note 9)
278
278
111
111
(Note 9)
(Note 9)
Data Clock (DCLKI, DCLKQ)
DCLK Duty Cycle
45
55
% (min)
% (max)
ps
50
tSR
tHR
Setup Time DCLK_RST±
Hold Time DCLK_RST±
(Note 10)
(Note 10)
45
45
ps
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24
ADC12D1800RF
Units
(Limits)
Symbol
tPWR
Parameter
Conditions
Typ
Lim
Pulse Width DCLK_RST±
(Note 9)
Sampling
Clock
Cycles
(min)
5
tSYNC_DLY
DCLK Synchronization Delay
90° Mode (Note 9)
0° Mode (Note 9)
4
5
Sampling
Clock
Cycles
tLHT
tHLT
Differential Low-to-High Transition 10%-to-90%, CL = 2.5 pF (Note
Time
Differential High-to-Low Transition 10%-to-90%, CL = 2.5 pF (Note
200
200
ps
ps
10)
Time
10)
tSU
tH
Data-to-DCLK Setup Time
DCLK-to-Data Hold Time
DCLK-to-Data Output Skew
90° Mode (Note 9)
90° Mode (Note 9)
430
430
ps
ps
tOSK
50% of DCLK transition to 50% of
Data transition (Note 9)
±50
ps
Data Input-to-Output
tAD
Aperture Delay (Note 10)
Sampling CLK+ Rise to
Acquisition of Data
1.29
0.2
ns
tAJ
Aperture Jitter
(Note 10)
ps (rms)
tOD
Sampling Clock-to Data Output
Delay (in addition to Latency)
50% of Sampling Clock transition
to 50% of Data transition (Note
10)
3.2
ns
tLAT
Latency in 1:2 Demux Non-DES DI, DQ Outputs
Mode (Note 9)
Latency in 1:4 Demux DES Mode DI Outputs
34
35
DId, DQd Outputs
34
(Note 9)
DQ Outputs
DId Outputs
DQd Outputs
34.5
35
Sampling
Clock
Cycles
35.5
34
Latency in Non-Demux Non-DES DI Outputs
Mode (Note 9)
Latency in Non-Demux DES Mode DI Outputs
DQ Outputs
34
34
(Note 9)
DQ Outputs
34.5
tORR
Over Range Recovery Time
Differential VIN step from ±1.2V to
0V to accurate conversion (Note
10)
Sampling
Clock
Cycle
1
tWU
Wake-Up Time (PDI/PDQ low to Non-DES Mode (Note 9)
500
1
ns
µs
Rated Accuracy Conversion)
DES Mode (Note 9)
25
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TABLE 15. Serial Port Interface
ADC12D1800RF
Units
(Limits)
Symbol
fSCLK
Parameter
Conditions
Typ
Lim
Serial Clock Frequency
Serial Clock Low Time
Serial Clock High Time
(Note 9)
15
MHz
30
30
ns (min)
ns (min)
tSSU
tSH
Serial Data-to-Serial Clock Rising (Note 9)
Setup Time
2.5
1
ns (min)
ns (min)
ns
Serial Data-to-Serial Clock Rising (Note 9)
Hold Time
tSCS
tHCS
tBSU
SCS-to-Serial Clock Rising Setup (Note 10)
Time
2.5
SCS-to-Serial Clock Falling Hold (Note 10)
Time
1.5
10
ns
ns
Bus turn-around time
(Note 10)
TABLE 16. Calibration
ADC12D1800RF
Units
(Limits)
Symbol
tCAL
Parameter
Conditions
Typ
Lim
Calibration Cycle Time
Non-ECM
Sampling
Clock
Cycles
4.1·107
ECM CSS = 0b
ECM CSS = 1b
(Note 9)
tCAL_L
tCAL_H
CAL Pin Low Time
CAL Pin High Time
Sampling
Clock
Cycles
(min)
1280
1280
224
(Note 9)
tCalDly
Calibration delay determined by
CalDly Pin (Note 9)
CalDly = Low
CalDly = High
Sampling
Clock
Cycles
(max)
230
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits, i.e. less than GND or greater than VA, the current at that pin should be limited to 50
mA. In addition, over-voltage at a pin must adhere to the maximum voltage limits. Simultaneous over-voltage at multiple pins requires adherence to the maximum
package power dissipation limits. These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on
specific customer thermal situation and specified package thermal resistances from junction to case.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Charged device model
simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 5: The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
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26
30164304
Note 6: To guarantee accuracy, it is required that VA, VTC, VE and VDR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 7: Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 8: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 3. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.
Note 9: This parameter is guaranteed by design and is not tested in production.
Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 11: The Dynamic Specifications are guaranteed for room to hot ambient temperature only (25°C to 85°C). Refer to the plots of the dynamic performance
vs. temperature in the Typical Performance Plots to see typical performance from cold to room temperature (-40°C to 25°C).
Note 12: These measurements were taken in Extended Control Mode (ECM) with the DES Timing Adjust feature enabled (Addr: 7h). This feature is used to
reduce the interleaving timing spur amplitude, which occurs at fs/2-fin, and thereby increase the SFDR, SINAD and ENOB.
Note 13: The Fs/2 spur was removed from all the dynamic performance specifications.
Note 14: Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.
Note 15: This rating is intended for d.c.-coupled applications; the voltages listed may be safely applied to VIN+/- for the life-time duty-cycle of the part.
Note 16: The differential and pin-to-ground input capacitances are lumped capacitance values from design; they are defined as shown below.
30164395
Note 17: The -3 dB point is the traditional Full-Power Bandwidth (FPBW) specification. Although the insertion loss is approximately half the power at this frequency,
the dynamic performance of the ADC does not necessarily begin to degrade to a level below which it may be effectively used in an application. The ADC may be
used at input frequencies above the -3 dB FPBW point, for example, into the 3rd Nyquist zone. Depending on system requirements, it is only necessary to
compensate for the insertion loss.
Note 18: This feature functionality is not tested in production test; performance is tested in the specified / default mode only.
Note 19: This pin / bit functionality is not tested in production test; performance is tested in the specified / default mode only.
Note 20: Typical dynamic performance is only tested at Fin = 498 MHz; other input frequencies are guaranteed by design and / or characterization and are not
tested in production.
27
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Ground. VOD peak is VOD,P= (VD+ - VD-) and VOD peak-to-peak
is VOD,P-P= 2*(VD+ - VD-); for this product, the VOD is measured
peak-to-peak.
13.0 Specification Definitions
APERTURE (SAMPLING) DELAY is the amount of delay,
measured from the sampling edge of the CLK input, after
which the signal present at the input pin is sampled inside the
device.
APERTURE JITTER (tAJ) is the variation in aperture delay
from sample-to-sample. Aperture jitter can be effectively con-
sidered as noise at the input.
CODE ERROR RATE (CER) is the probability of error and is
defined as the probable number of word errors on the ADC
output per unit of time divided by the number of words seen
in that amount of time. A CER of 10-18 corresponds to a sta-
tistical error in one word about every 31.7 years.
30164346
CLOCK DUTY CYCLE is the ratio of the time that the clock
waveform is at a logic high to the total time of one clock period.
FIGURE 2. LVDS Output Signal Levels
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB. It is
measured at the relevant sample rate, fCLK, with fIN = 1MHz
sine wave.
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint
between the D+ and D- pins output voltage with respect to
ground; i.e., [(VD+) +( VD-)]/2. See Figure 2.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD −
1.76) / 6.02 and states that the converter is equivalent to a
perfect ADC of this many (ENOB) number of bits.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes can-
not be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and Full-
Scale Errors. The Positive Gain Error is the Offset Error minus
the Positive Full-Scale Error. The Negative Gain Error is the
Negative Full-Scale Error minus the Offset Error. The Gain
Error is the Negative Full-Scale Error minus the Positive Full-
Scale Error; it is also equal to the Positive Gain Error plus the
Negative Gain Error.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of
how far the first code transition is from the ideal 1/2 LSB above
a differential −VIN/2. For the ADC12D1800RF the reference
voltage is assumed to be ideal, so this error is a combination
of full-scale error and reference voltage error.
NOISE FLOOR DENSITY is a measure of the power density
of the noise floor, expressed in dBFS/Hz and dBm/Hz. '0
dBFS' is defined as the power of a sinusoid which precisely
uses the full-scale range of the ADC.
GAIN FLATNESS is the measure of the variation in gain over
the specified bandwidth. For example, for the AD-
C12D1800RF, from D.C. to Fs/2 is to 900 MHz for the Non-
DES Mode and from D.C. to Fs/2 is 1800 MHz for the DES
Mode.
NOISE POWER RATIO (NPR) is the ratio of the sum of the
power outside the notched bins to the sum of the power in an
equal number of bins inside the notch, expressed in dB.
OFFSET ERROR (VOFF) is a measure of how far the mid-
scale point is from the ideal zero voltage differential input.
INTEGRAL NON-LINEARITY (INL) is a measure of worst
case deviation of the ADC transfer function from an ideal
straight line drawn through the ADC transfer function. The
deviation of any given code from this straight line is measured
from the center of that code value step. The best fit method
is used.
Offset Error = Actual Input causing average of 8k samples to
result in an average code of 2047.5.
OUTPUT DELAY (tOD) is the time delay (in addition to Laten-
cy) after the rising edge of CLK+ before the data update is
present at the output pins.
INSERTION LOSS is the loss in power of a signal due to the
insertion of a device, e.g. the ADC12D1800RF, expressed in
dB.
OVER-RANGE RECOVERY TIME is the time required after
the differential input voltages goes from ±1.2V to 0V for the
converter to recover and make a conversion with its rated ac-
curacy.
INTERMODULATION DISTORTION (IMD) is a measure of
the near-in 3rd order distortion products (2f2 - f1, 2f1 - f2) which
occur when two tones which are close in frequency (f1, f2) are
applied to the ADC input. It is measured from the input tones
level to the higher of the two distortion products (dBc) or sim-
ply the level of the higher of the two distortion products
(dBFS). The input tones are typically -7dBFS.
PIPELINE DELAY (LATENCY) is the number of input clock
cycles between initiation of conversion and when that data is
presented to the output driver stage. The data lags the con-
version by the Latency plus the tOD
.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of
how far the last code transition is from the ideal 1-1/2 LSB
below a differential +VIN/2. For the ADC12D1800RF the ref-
erence voltage is assumed to be ideal, so this error is a
combination of full-scale error and reference voltage error.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value or weight of all bits. This value is
VFS / 2N
where VFS is the differential full-scale amplitude VIN_FSR as set
by the FSR input and "N" is the ADC resolution in bits, which
is 12 for the ADC12D1800RF.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the fundamental for a single-tone to
the rms value of the sum of all other spectral components
below one-half the sampling frequency, not including har-
monics or DC.
LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS)
DIFFERENTIAL OUTPUT VOLTAGE (VID and VOD) is two
times the absolute value of the difference between the VD+
and VD- signals; each signal measured with respect to
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28
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
fundamental for a single-tone to the rms value of all of the
other spectral components below half the input clock frequen-
cy, including harmonics but excluding DC.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal at the output and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input, excluding DC.
where Af1 is the RMS power of the fundamental (output) fre-
quency and Af2 through Af10 are the RMS power of the first 9
harmonic frequencies in the output spectrum.
– Second Harmonic Distortion (2nd Harm) is the differ-
ence, expressed in dB, between the RMS power in the input
frequency seen at the output and the power in its 2nd har-
monic level at the output.
θ
θ
JA is the thermal resistance between the junction to ambient.
JC1 represents the thermal resistance between the die and
the exposed metal area on the top of the HSBGA package.
– Third Harmonic Distortion (3rd Harm) is the difference
expressed in dB between the RMS power in the input fre-
quency seen at the output and the power in its 3rd harmonic
level at the output.
θ
JC2 represents the thermal resistance between the die and
the center group of balls on the bottom of the HSBGA pack-
age.
TOTAL HARMONIC DISTORTION (THD) is the ratio ex-
pressed in dB, of the rms total of the first nine harmonic levels
at the output to the level of the fundamental at the output. THD
is calculated as
29
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14.0 Transfer Characteristic
30164322
FIGURE 3. Input / Output Transfer Characteristic
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30
15.0 Timing Diagrams
30164359
FIGURE 4. Clocking in 1:2 Demux Non-DES Mode*
30164360
FIGURE 5. Clocking in Non-Demux Non-DES Mode*
31
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30164399
FIGURE 6. Clocking in 1:4 Demux DES Mode*
30164396
FIGURE 7. Clocking in Non-Demux Mode DES Mode*
* The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case,
the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ.
Both I- and Q-channel use the same CLK.
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32
30164320
FIGURE 8. Data Clock Reset Timing (Demux Mode)
30164325
FIGURE 9. Power-on and On-Command Calibration Timing
30164319
FIGURE 10. Serial Interface Timing
33
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16.0 Typical Performance Plots
VA = VDR = VTC = VE = 1.9V, fCLK = 1.8 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux Non-
DES Mode has similar performance), unless otherwise stated.
INL vs. CODE (ADC12D1800RF)
INL vs. TEMPERATURE (ADC12D1800RF)
3
1.0
+INL
-INL
2
1
0
0.5
0.0
-0.5
-1.0
-1
-2
-3
0
4095
-50
0
50
100
OUTPUT CODE
TEMPERATURE (°C)
30164338
30164340
DNL vs. CODE (ADC12D1800RF)
0.75
DNL vs. TEMPERATURE (ADC12D1800RF)
0.50
+DNL
-DNL
0.50
0.25
0.25
0.00
0.00
-0.25
-0.50
-0.25
-0.50
-0.75
0
4095
-50
0
50
100
OUTPUT CODE
TEMPERATURE (°C)
30164339
30164341
ENOB vs. TEMPERATURE (ADC12D1800RF)
ENOB vs. SUPPLY VOLTAGE (ADC12D1800RF)
10
10
9
8
9
8
7
7
NON-DES MODE
NON-DES MODE
DES MODE
6
DES MODE
6
-50
0
50
100
1.8
1.9
2.0
(V)
2.1
2.2
TEMPERATURE (°C)
V
A
30164376
30164377
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34
ENOB vs. CLOCK FREQUENCY (ADC12D1800RF)
ENOB vs. INPUT FREQUENCY (ADC12D1800RF)
10
10
NON-DES MODE
DES MODE
9
9
8
8
7
6
7
NON-DES MODE
DES MODE
6
0
600
1200
1800
0
1000
2000
3000
CLOCK FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
30164378
30164379
ENOB vs. VCMI (ADC12D1800RF)
SNR vs. TEMPERATURE (ADC12D1800RF)
60
10
NON-DES MODE
DES MODE
58
56
54
9
8
7
6
52
NON-DES MODE
DES MODE
50
-50
0
50
100
0.75
1.00
1.25
(V)
1.50
1.75
TEMPERATURE (°C)
V
CMI
30164368
30164342
SNR vs. SUPPLY VOLTAGE (ADC12D1800RF)
SNR vs. CLOCK FREQUENCY (ADC12D1800RF)
60
60
NON-DES MODE
DES MODE
58
56
54
58
56
54
52
50
52
NON-DES MODE
DES MODE
50
1.8
1.9
2.0
(V)
2.1
2.2
0
600
1200
1800
V
CLOCK FREQUENCY (MHz)
A
30164369
30164370
35
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SNR vs. INPUT FREQUENCY (ADC12D1800RF)
THD vs. TEMPERATURE (ADC12D1800RF)
60
-40
-50
-60
55
50
-70
NON-DES MODE
NON-DES MODE
DES MODE
45
DES MODE
-80
0
1000
2000
3000
-50
0
50
100
INPUT FREQUENCY (MHz)
TEMPERATURE (°C)
30164371
30164372
THD vs. SUPPLY VOLTAGE (ADC12D1800RF)
THD vs. CLOCK FREQUENCY (ADC12D1800RF)
-40
-40
NON-DES MODE
DES MODE
-50
-60
-50
-60
-70
-80
-70
NON-DES MODE
DES MODE
-80
1.8
1.9
2.0
(V)
2.1
2.2
0
600
1200
1800
V
CLOCK FREQUENCY (MHz)
A
30164373
30164374
THD vs. INPUT FREQUENCY (ADC12D1800RF)
SFDR vs. TEMPERATURE (ADC12D1800RF)
-40
80
NON-DES MODE
DES MODE
-50
70
60
-60
-70
-80
50
NON-DES MODE
DES MODE
40
0
1000
2000
3000
-50
0
50
100
INPUT FREQUENCY (MHz)
TEMPERATURE (°C)
30164375
30164385
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36
SFDR vs. SUPPLY VOLTAGE (ADC12D1800RF)
SFDR vs. CLOCK FREQUENCY (ADC12D1800RF)
80
80
NON-DES MODE
DES MODE
70
60
70
60
50
40
50
NON-DES MODE
DES MODE
40
1.8
1.9
2.0
(V)
2.1
2.2
0
600
1200
1800
V
CLOCK FREQUENCY (MHz)
A
30164384
30164382
SFDR vs. INPUT FREQUENCY (ADC12D1800RF)
SPECTRAL RESPONSE NON-DES MODE (ADC12D1800RF)
80
0
NON-DES MODE
70
60
-25
-50
50
-75
NON-DES MODE
DES MODE
40
-100
0
1000
2000
3000
0
300
600
900
INPUT FREQUENCY (MHz)
FREQUENCY (MHz)
30164383
30164389
SPECTRAL RESPONSE DESI MODE (ADC12D1800RF) SPECTRAL RESPONSE DESCLKIQ MODE (ADC12D1800RF)
0
0
DESI MODE
-25
-25
-50
-50
-75
-75
-100
-100
0
600
1200
1800
0
600
1200
1800
FREQUENCY (MHz)
FREQUENCY (MHz)
30164387
30164391
37
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CROSSTALK vs. SOURCE FREQUENCY (ADC12D1800RF)
INSERTION LOSS (ADC12D1800RF)
-30
0
NON-DES MODE
-40
-50
-60
-70
-80
-90
-3
-6
-9
-12
DESI MODE
DESIQ MODE
NON-DES, DESCLKIQ MODE
-15
0
1000
2000
3000
0
1000
2000
3000
4000
AGGRESSOR INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
30164363
30164348
POWER CONSUMPTION vs. CLOCK FREQUENCY
(ADC12D1800RF)
5.0
NON-DEMUX MODE
DEMUX MODE
4.5
4.0
3.5
3.0
2.5
2.0
0
600
1200
1800
CLOCK FREQUENCY (MHz)
30164381
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38
for AC/DC-coupled Mode selection and LVDS output com-
mon-mode voltage selection. See Table 17 for a summary.
17.0 Functional Description
The ADC12D1800RF is a versatile A/D converter with an in-
novative architecture which permits very high speed opera-
tion. The controls available ease the application of the device
to circuit solutions. Optimum performance requires adher-
ence to the provisions discussed here and in the Applications
Information Section. This section covers an overview, a de-
scription of control modes (Extended Control Mode and Non-
Extended Control Mode), and features.
TABLE 17. Non-ECM Pin Summary
Pin
Name
Logic-Low
Logic-High
Floating
Dedicated Control Pins
Non-DES
Mode
DES
Mode
DES
Not valid
Demux
NDM
Non-Demux
Mode
17.1 OVERVIEW
Not valid
Not valid
Not valid
Not valid
Mode
The ADC12D1800RF uses a calibrated folding and interpo-
lating architecture that achieves a high Effective Number of
Bits (ENOB). The use of folding amplifiers greatly reduces the
number of comparators and power consumption. Interpola-
tion reduces the number of front-end amplifiers required,
minimizing the load on the input signal and further reducing
power requirements. In addition to correcting other non-ide-
alities, on-chip calibration reduces the INL bow often seen
with folding architectures. The result is an extremely fast, high
performance, low power converter.
DDRPh
CAL
0° Mode
90° Mode
See Section 17.2.1.4
Calibration Pin (CAL)
CalDly Shorter delay Longer delay
I-channel
active
Power Down Power Down
I-channel I-channel
Power Down Power Down
PDI
PDQ
TPM
FSR
Q-channel
active
Q-channel
Q-channel
The analog input signal (which is within the converter's input
voltage range) is digitized to twelve bits at speeds of 150
MSPS to 3.6 GSPS, typical. Differential input voltages below
negative full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at the I- or Q-input will cause the Out-of-
Range I-channel or Q-channel output (ORI or ORQ), respec-
tively, to output a logic-high signal.
Non-Test
Pattern Mode
Test Pattern
Mode
Not valid
Nominal FS
input Range
Not allowed
Not valid
Dual-purpose Control Pins
AC-coupled
operation
DC-coupled
operation
VCMO
Not allowed
In ECM, an expanded feature set is available via the Serial
Interface. The ADC12D1800RF builds upon previous archi-
tectures, introducing a new DES Mode Timing Adjust, Au-
toSync feature for multi-chip synchronization and increasing
to 15-bit for gain and 12-bit plus sign for offset the indepen-
dent programmable adjustment for each channel.
Higher LVDS Lower LVDS
common- common-
mode voltage mode voltage
VBG
Not allowed
17.2.1.1 Dual Edge Sampling Pin (DES)
The Dual Edge Sampling (DES) Pin selects whether the
ADC12D1800RF is in DES Mode (logic-high) or Non-DES
Mode (logic-low). DES Mode means that a single analog input
is sampled by both I- and Q-channels in a time-interleaved
manner. One of the ADCs samples the input signal on the
rising sampling clock edge (duty cycle corrected); the other
ADC samples the input signal on the falling sampling clock
edge (duty cycle corrected). In Non-ECM, only the I-input may
be used for DES Mode, a.k.a. "DESI Mode". In ECM, the Q-
input may be selected via the DEQ Bit (Addr: 0h, Bit: 6), a.k.a.
"DESQ Mode". In ECM, both the I- and Q-inputs maybe se-
lected, a.k.a. "DESIQ Mode".
Each channel has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 Demux Mode is selected,
the output data rate is reduced to half the input sample rate
on each bus. When Non-Demux Mode is selected, the output
data rate on each channel is at the same rate as the input
sample clock and only one 12-bit bus per channel is active.
17.2 CONTROL MODES
The ADC12D1800RF may be operated in one of two control
modes: Non-extended Control Mode (Non-ECM) or Extended
Control Mode (ECM). In the simpler Non-ECM (also some-
times referred to as Pin Control Mode), the user affects avail-
able configuration and control of the device through the
control pins. The ECM provides additional configuration and
control options through a serial interface and a set of 16 reg-
isters, most of which are available to the customer.
To use this feature in ECM, use the DES bit in the Configu-
ration Register (Addr: 0h; Bit: 7). See Section 17.3.1.4 DES/
Non-DES Mode for more information.
17.2.1.2 Non-Demultiplexed Mode Pin (NDM)
The Non-Demultiplexed Mode (NDM) Pin selects whether the
ADC12D1800RF is in Demux Mode (logic-low) or Non-De-
mux Mode (logic-high). In Non-Demux Mode, the data from
the input is produced at the sampled rate at a single 12-bit
output bus. In Demux Mode, the data from the input is pro-
duced at half the sampled rate at twice the number of output
buses. For Non-DES Mode, each I- or Q-channel will produce
its data on one or two buses for Non-Demux or Demux Mode,
respectively. For DES Mode, the selected channel will pro-
duce its data on two or four buses for Non-Demux or Demux
Mode, respectively.
17.2.1 Non-Extended Control Mode
In Non-extended Control Mode (Non-ECM), the Serial Inter-
face is not active and all available functions are controlled via
various pin settings. Non-ECM is selected by setting the
ECE Pin to logic-high. Note that, for the control pins, "logic-
high" and "logic-low" refer to VA and GND, respectively. Nine
dedicated control pins provide a wide range of control for the
ADC12D1800RF and facilitate its operation. These control
pins provide DES Mode selection, Demux Mode selection,
DDR Phase selection, execute Calibration, Calibration Delay
setting, Power Down I-channel, Power Down Q-channel, Test
Pattern Mode selection, and Full-Scale Input Range selec-
tion. In addition to this, two dual-purpose control pins provide
39
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This feature is pin-controlled only and remains active during
both Non-ECM and ECM. See Section 17.3.2.5 Demux/Non-
demux Mode for more information.
to power-down the I-channel. See Section 17.3.4 Power
Down for more information.
17.2.1.7 Power Down Q-channel Pin (PDQ)
17.2.1.3 Dual Data Rate Phase Pin (DDRPh)
The Power Down Q-channel (PDQ) Pin selects whether the
Q-channel is powered down (logic-high) or active (logic-low).
This pin functions similarly to the PDI pin, except that it applies
to the Q-channel. The PDI and PDQ pins function indepen-
dently of each other to control whether each I- or Q-channel
is powered down or active.
The Dual Data Rate Phase (DDRPh) Pin selects whether the
ADC12D1800RF is in 0° Mode (logic-low) or 90° Mode (logic-
high) for DDR Mode. If the device is in SDR Mode, then the
DDRPh Pin selects whether the ADC12D1800RF is in Falling
Mode (logic low) or Rising Mode (logic high). For DDR Mode,
the Data may transition either with the DCLK transition (0°
Mode) or halfway between DCLK transitions (90° Mode). The
DDRPh Pin selects 0° Mode or 90° Mode for both the I-chan-
nel: DI- and DId-to-DCLKI phase relationship and for the Q-
channel: DQ- and DQd-to-DCLKQ phase relationship.
This pin remains active in ECM. In ECM, either this pin or the
PDQ bit (Addr: 0h; Bit: 10) in the Control Register may be
used to power-down the Q-channel. See Section 17.3.4 Pow-
er Down for more information.
17.2.1.8 Test Pattern Mode Pin (TPM)
To use this feature in ECM, use the DPS bit in the Configu-
ration Register (Addr: 0h; Bit: 14). See Section 17.3.2.1 SDR /
DDR Clock for more information.
The Test Pattern Mode (TPM) Pin selects whether the
output of the ADC12D1800RF is a test pattern (logic-high) or
the
converted
analog
input
(logic-low).
The
17.2.1.4 Calibration Pin (CAL)
ADC12D1800RF can provide a test pattern at the four output
buses independently of the input signal to aid in system de-
bug. In TPM, the ADC is disengaged and a test pattern
generator is connected to the outputs, including ORI and
ORQ. SeeSection 17.3.2.6 Test Pattern Mode for more infor-
mation.
The Calibration (CAL) Pin may be used to execute an on-
command calibration or to disable the power-on calibration.
The effect of calibration is to maximize the dynamic perfor-
mance. To initiate an on-command calibration via the CAL
pin, bring the CAL pin high for a minimum of tCAL_H input clock
cycles after it has been low for a minimum of tCAL_L input clock
cycles. Holding the CAL pin high upon power-on will prevent
execution of the power-on calibration. In ECM, this pin re-
mains active and is logically OR'd with the CAL bit.
17.2.1.9 Full-Scale Input Range Pin (FSR)
The Full-Scale Input Range (FSR) Pin sets the full-scale input
range for both the I- and Q-channel; for the ADC12D1800RF,
only the logic-high setting is available. The input full-scale
range is specified as VIN_FSR in Table 8. In Non-ECM, the full-
scale input range for each I- and Q-channel may not be set
independently, but it is possible to do so in ECM. The device
must be calibrated following a change in FSR to obtain opti-
mal performance.
To use this feature in ECM, use the CAL bit in the Configu-
ration Register (Addr: 0h; Bit: 15). See Section 17.3.3 Cali-
bration Feature for more information.
17.2.1.5 Calibration Delay Pin (CalDly)
The Calibration Delay (CalDly) Pin selects whether a shorter
or longer delay time is present, after the application of power,
until the start of the power-on calibration. The actual delay
time is specified as tCalDly and may be found in Table 16. This
feature is pin-controlled only and remains active in ECM. It is
recommended to select the desired delay time prior to power-
on and not dynamically alter this selection.
To use this feature in ECM, use the Configuration Registers
(Addr: 3h and Bh). See Section 17.3.1 Input Control and Ad-
just for more information.
17.2.1.10 AC / DC-Coupled Mode Pin (VCMO
)
The VCMO Pin serves a dual purpose. When functioning as an
output, it provides the optimal common-mode voltage for the
DC-coupled analog inputs. When functioning as an input, it
selects whether the device is AC-coupled (logic-low) or DC-
coupled (floating). This pin is always active, in both ECM and
Non-ECM.
See Section 17.3.3 Calibration Feature for more information.
17.2.1.6 Power Down I-channel Pin (PDI)
The Power Down I-channel (PDI) Pin selects whether the I-
channel is powered down (logic-high) or active (logic-low).
The digital data output pins, DI and DId, (both positive and
negative) are put into a high impedance state when the I-
channel is powered down. Upon return to the active state, the
pipeline will contain meaningless information and must be
flushed. The supply currents (typicals and limits) are available
for the I-channel powered down or active and may be found
in Table 13. The device should be recalibrated following a
power-cycle of PDI (or PDQ).
17.2.1.11 LVDS Output Common-mode Pin (VBG
)
The VBG Pin serves a dual purpose. When functioning as an
output, it provides the bandgap reference. When functioning
as an input, it selects whether the LVDS output common-
mode voltage is higher (logic-high) or lower (floating). The
LVDS output common-mode voltage is specified as VOS and
may be found in Table 12. This pin is always active, in both
ECM and Non-ECM.
This pin remains active in ECM. In ECM, either this pin or the
PDI bit (Addr: 0h; Bit: 11) in the Control Register may be used
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40
17.2.2 Extended Control Mode
than 24 clocks, data write will occur normally through the SDI
input upon the 24th clock. Setup and hold times, tSCS and
tHCS, with respect to the SCLK must be observed. SCS must
be toggled in between register access cycles.
In Extended Control Mode (ECM), most functions are con-
trolled via the Serial Interface. In addition to this, several of
the control pins remain active. See Table 20 for details. ECM
is selected by setting the ECE Pin to logic-low. If the ECE Pin
is set to logic-high (Non-ECM), then the registers are reset to
their default values. So, a simple way to reset the registers is
by toggling the ECE pin. Four pins on the ADC12D1800RF
control the Serial Interface: SCS, SCLK, SDI and SDO. This
section covers the Serial Interface. The Register Definitions
are located at the end of the datasheet so that they are easy
to find, see Section 19.0 Register Definitions.
SCLK: This signal is used to register the input data (SDI) on
the rising edge; and to source the output data (SDO) on the
falling edge. The user may disable the clock and hold it at
logic-low. There is no minimum frequency requirement for
SCLK; see fSCLK in Table 15 for more details.
SDI: Each register access requires a specific 24-bit pattern at
this input, consisting of a command field and a data field. If
the SDI and SDO wired are shared (3-wire mode), then during
read operations it is necessary to tri-state the master which is
driving SDI while the data field is being output by the ADC on
SDO. The master must be at TRI-STATE before the falling
edge of the 8th clock. If SDI and SDO are not shared (4-wire
mode), then this is not necessary. Setup and hold times, tSH
and tSSU, with respect to the SCLK must be observed.
17.2.2.1 The Serial Interface
The ADC12D1800RF offers a Serial Interface that allows ac-
cess to the sixteen control registers within the device. The
Serial Interface is a generic 4-wire (optionally 3-wire) syn-
chronous interface that is compatible with SPI type interfaces
that are used on many micro-controllers and DSP controllers.
Each serial interface access cycle is exactly 24 bits long. A
register-read or register-write can be accomplished in one
cycle. The signals are defined in such a way that the user can
opt to simply join SDI and SDO signals in his system to ac-
complish a single, bidirectional SDI/O signal. A summary of
the pins for this interface may be found in Table 18. See Fig-
ure 10 for the timing diagram and Table 15 for timing specifi-
cation details. Control register contents are retained when the
device is put into power-down mode. If this feature is unused,
the SCLK, SDI, and SCS pins may be left floating because
they each have an internal pull-up.
SDO: This output is normally at TRI-STATE and is driven only
when SCS is asserted, the first 8 bits of command data have
been received and it is a READ operation. The data is shifted
out, MSB first, starting with the 8th clock's falling edge. At the
end of the access, when SCS is de-asserted, this output is at
TRI-STATE once again. If an invalid address is accessed, the
data sourced will consist of all zeroes. If it is a read operation,
there will be a bus turnaround time, tBSU, from when the last
bit of the command field was read in until the first bit of the
data field is written out.
Table 19 shows the Serial Interface bit definitions.
TABLE 19. Command and Data Field Definitions
TABLE 18. Serial Interface Pins
Bit No.
Name
Read / Write (R/W)
Reserved
Comments
Pin
C4
C5
B4
A3
Name
1b indicates a read operation
0b indicates a write operation
SCS (Serial Chip Select bar)
SCLK (Serial Clock)
SDI (Serial Data In)
1
2-3
Bits must be set to 10b
16 registers may be
addressed. The order is MSB
first
SDO (Serial Data Out)
4-7
A<3:0>
SCS: Each assertion (logic-low) of this signal starts a new
register access, i.e. the SDI command field must be ready on
the following SCLK rising edge. The user is required to de-
assert this signal after the 24th clock. If the SCS is de-
asserted before the 24th clock, no data read / write will occur.
For a read operation, if the SCS is asserted longer than 24
clocks, the SDO output will hold the D0 bit until SCS is de-
asserted. For a write operation, if the SCS is asserted longer
8
X
This is a "don't care" bit
Data written to or read from
addressed register
9-24
D<15:0>
The serial data protocol is shown for a read and write opera-
tion in Figure 11 and Figure 12, respectively.
30164392
FIGURE 11. Serial Data Protocol - Read Operation
41
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30164393
FIGURE 12. Serial Data Protocol - Write Operation
17.3 FEATURES
20 is a summary of the features available, as well as details
for the control mode chosen. "N/A" means "Not Applicable."
The ADC12D1800RF offers many features to make the de-
vice convenient to use in a wide variety of applications. Table
TABLE 20. Features and Modes
Control Pin
Active in
ECM
Feature
Non-ECM
ECM
Default ECM State
Input Control and Adjust
Selected via VCMO
(Pin C2)
AC/DC-coupled Mode
Selection
Yes
No
Not available
N/A
Input Full-scale Range
Adjust
Selected via FSR
(Pin Y3)
Selected via the Config Reg
Low FSR value
Offset = 0 mV
Non-DES Mode
N/A
(Addr: 3h and Bh)
Selected via the Config Reg
Input Offset Adjust Setting
Not available
N/A
No
(Addr: 2h and Ah)
DES/Non-DES Mode
Selection
Selected via DES
(Pin V5)
Selected via the DES Bit
(Addr: 0h; Bit: 7)
Selected via the DCK Bit
DES Mode Input Selection
DESCLKIQ Mode (Note 18)
DES Timing Adjust
Not available
N/A
(Addr: Eh; Bit: 6)
Selected via the DES Timing
Adjust Reg
Not available
N/A
N/A
(Addr: 7h)
Selected via the DES Timing
Not available
Not available
N/A
N/A
Mid skew offset
Adjust Reg (Addr: 7h)
Sampling Clock Phase
Adjust
Selected via the Config Reg
tAD adjust disabled
(Addr: Ch and Dh)
Output Control and Adjust
Selected via DDRPh Selected via the DPS Bit
DDR Clock Phase Selection
DDR / SDR DCLK Selection
No
N/A
N/A
N/A
0° Mode
DDR Mode
N/A
(Pin W4)
(Addr: 0h; Bit: 14)
Selected via the SDR Bit
Not available
(Addr: 0h; Bit: 2)
SDR Rising / Falling DCLK
Selected via the DPS Bit
Not available
Selection (Note 18)
(Addr: 0h; Bit: 14)
LVDS Differential Voltage
Amplitude Selection
Higher amplitude
only
Selected via the OVS Bit
Higher amplitude
(Addr: 0h; Bit: 13)
LVDS Common-Mode
Voltage Amplitude
Selection(Note 18)
Selected via VBG
(Pin B1)
Yes
Not available
N/A
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42
Control Pin
Active in
ECM
Feature
Non-ECM
ECM
Default ECM State
Output Formatting
Selection (Note 18)
Selected via the 2SC Bit
Offset Binary only
N/A
No
Offset Binary
TPM disabled
N/A
(Addr: 0h; Bit: 4)
Selected via TPM
(Pin A4)
Selected via the TPM Bit
Test Pattern Mode at Output
(Addr: 0h; Bit: 12)
Demux/Non-Demux Mode
Selection
Selected via NDM
(Pin A5)
Yes
N/A
N/A
Not available
Selected via the Config Reg
Master Mode,
RCOut1/2 disabled
AutoSync
DCLK Reset
Time Stamp
Not available
Not available
Not available
(Addr: Eh)
Selected via the Config Reg
DCLK Reset disabled
Time Stamp disabled
(Addr: Eh; Bit 0)
Selected via the TSE Bit
N/A
(Addr: 0h; Bit: 3)
Calibration
Yes
Selected via CAL
(Pin D6)
Selected via the CAL Bit
N/A
(CAL = 0)
On-command Calibration
(Addr: 0h; Bit: 15)
Power-on Calibration Delay Selected via CalDly
Yes
N/A
Not available
N/A
tCAL
Selection(Note 18)
(Pin V4)
Selected via the Config Reg
Calibration Adjust(Note 18)
Not available
(Addr: 4h)
Read / Write Calibration
Selected via the SSC Bit
R/W calibration values
disabled
Not available
N/A
Settings(Note 18)
(Addr: 4h; Bit: 7)
Power-Down
Yes
Selected via PDI
(Pin U3)
Selected via the PDI Bit
Power down I-channel
I-channel operational
Q-channel operational
(Addr: 0h; Bit: 11)
Selected via PDQ
(Pin V3)
Selected via the PDQ Bit
Power down Q-channel
Yes
(Addr: 0h; Bit: 10)
17.3.1 Input Control and Adjust
Section 19.0 Register Definitions for information about the
registers.
There are several features and configurations for the input of
the ADC12D1800RF so that it may be used in many different
applications. This section covers AC/DC-coupled Mode, input
full-scale range adjust, input offset adjust, DES/Non-DES
Mode, DES Timing Adjust, and sampling clock phase adjust.
17.3.1.4 DES/Non-DES Mode
The ADC12D1800RF can operate in Dual-Edge Sampling
(DES) or Non-DES Mode. The DES Mode allows for a single
analog input to be sampled by both I- and Q-channels. One
channel samples the input on the rising edge of the sampling
clock and the other samples the same input signal on the
falling edge of the sampling clock. A single input is thus sam-
pled twice per clock cycle, resulting in an overall sample rate
of twice the sampling clock frequency, e.g. 3.6 GSPS with a
1.8 GHz sampling clock. Since DES Mode uses both I- and
Q-channels to process the input signal, both channels must
be powered up for the DES Mode to function properly.
17.3.1.1 AC/DC-coupled Mode
The analog inputs may be AC or DC-coupled. See Sec-
tion 17.2.1.10 AC / DC-Coupled Mode Pin (VCMO) for infor-
mation on how to select the desired mode and Section 18.1.7
DC-coupled Input Signals and Section 18.1.6 AC-coupled In-
put Signals for applications information.
17.3.1.2 Input Full-Scale Range Adjust
The input full-scale range for the ADC12D1800RF may be
adjusted in ECM. In Non-ECM, the control pin must be set to
logic-high; see Section 17.2.1.9 Full-Scale Input Range Pin
(FSR). In ECM, the input full-scale range may be adjusted
with 15-bits of precision. See VIN_FSR in Table 8 for electrical
specification details. Note that the full-scale input range set-
ting in Non-ECM (logic-high only) corresponds to the lowest
full-scale input range settings in ECM. It is necessary to exe-
cute an on-command calibration following a change of the
input full-scale range. See Section 19.0 Register Definitions
for information about the registers.
In Non-ECM, only the I-input may be used for the DES Mode
input. See Section 17.2.1.1 Dual Edge Sampling Pin (DES)
for information on how to select the DES Mode. In ECM, either
the I- or Q-input may be selected by first using the DES bit
(Addr: 0h, Bit 7) to select the DES Mode. The DEQ Bit (Addr:
0h, Bit: 6) is used to select the Q-input, but the I-input is used
by default. Also, both I- and Q-inputs may be driven externally,
i.e. DESIQ Mode, by using the DIQ bit (Addr: 0h, Bit 5). See
Section 18.1 THE ANALOG INPUTS for more information
about how to drive the ADC in DES Mode.
In DESCLKIQ Mode, the I- and Q-channels sample their in-
puts 180° out-of-phase with respect to one another, similar to
the other DES Modes. DESCLKIQ Mode is similar to the DE-
SIQ Mode, except that the I- and Q-channels remain electri-
cally separate internal to the ADC12D1800RF. For this
reason, both I- and Q-inputs must be externally driven for the
17.3.1.3 Input Offset Adjust
The input offset adjust for the ADC12D1800RF may be ad-
justed with 12-bits of precision plus sign via ECM. See
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DESCLKIQ Mode. The DCLK Bit (Addr: Eh, Bit 6) is used to
select the 180° sampling clock mode.
for the maximum sampling clock rate of is 555ps, so it should
not be necessary to exceed this value in any case.
The DESCLKIQ Mode results in the best bandwidth for the
interleaved modes. In general, the bandwidth decreases from
Non-DES Mode to DES Mode (specifically, DESI or DESQ)
because both channels are sampling off the same input signal
and non-ideal effects introduced by interleaving the two chan-
nels lower the bandwidth. Driving both I- and Q-channels
externally (DESIQ Mode and DESCLKIQ Mode) results in
better bandwidth for the DES Mode because each channel is
being driven, which reduces routing losses. The DESCLKIQ
Mode has better bandwidth than the DESIQ Mode because
the routing internal to the ADC12D1800RF is simpler, which
results in less insertion loss.
17.3.2 Output Control and Adjust
There are several features and configurations for the output
of the ADC12D1800RF so that it may be used in many differ-
ent applications. This section covers DDR clock phase, LVDS
output differential and common-mode voltage, output format-
ting, Demux/Non-demux Mode, Test Pattern Mode, and Time
Stamp.
17.3.2.1 SDR / DDR Clock
The ADC12D1800RF output data can be delivered in Double
Data Rate (DDR) or Single Data Rate (SDR). For DDR, the
DCLK frequency is half the data rate and data is sent to the
outputs on both edges of DCLK; see Figure 13. The DCLK-
to-Data phase relationship may be either 0° or 90°. For 0°
Mode, the Data transitions on each edge of the DCLK. Any
offset from this timing is tOSK; see Table 14 for details. For 90°
Mode, the DCLK transitions in the middle of each Data cell.
Setup and hold times for this transition, tSU and tH, may also
be found in Table 14. The DCLK-to-Data phase relationship
may be selected via the DDRPh Pin in Non-ECM (see Sec-
tion 17.2.1.3 Dual Data Rate Phase Pin (DDRPh)) or the DPS
bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM.
Note that for Non-Demux Mode, 90° DDR Mode is not avail-
able.
In the DES Mode, the outputs must be carefully interleaved
in order to reconstruct the sampled signal. If the device is
programmed into the 1:4 Demux DES Mode, the data is ef-
fectively demultiplexed by 1:4. If the sampling clock is 1.8
GHz, the effective sampling rate is doubled to 3.6 GSPS and
each of the 4 output buses has an output rate of 900 MSPS.
All data is available in parallel. To properly reconstruct the
sampled waveform, the four bytes of parallel data that are
output with each DCLK must be correctly interleaved. The
sampling order is as follows, from the earliest to the latest:
DQd, DId, DQ, DI. See Figure 6. If the device is programmed
into the Non-Demux DES Mode, two bytes of parallel data are
output with each edge of the DCLK in the following sampling
order, from the earliest to the latest: DQ, DI. See Figure 7.
17.3.1.5 DES Timing Adjust
The performance of the ADC12D1800RF in DES Mode de-
pends on how well the two channels are interleaved, i.e. that
the clock samples either channel with precisely a 50% duty-
cycle, each channel has the same offset (nominally code
2047/2048), and each channel has the same full-scale range.
The ADC12D1800RF includes an automatic clock phase
background adjustment in DES Mode to automatically and
continuously adjust the clock phase of the I- and Q-channels.
In addition to this, the residual fixed timing skew offset may
be further manually adjusted, and further reduce timing spurs
for specific applications. See the DES Timing Adjust (Addr:
7h). As the DES Timing Adjust is programmed from 0d to
127d, the magnitude of the Fs/2-Fin timing interleaving spur
will decrease to a local minimum and then increase again. The
default, nominal setting of 64d may or may not coincide with
this local minimum. The user may manually skew the global
timing to achieve the lowest possible timing interleaving spur.
30164394
FIGURE 13. DDR DCLK-to-Data Phase Relationship
For SDR, the DCLK frequency is the same as the data rate
and data is sent to the outputs on a single edge of DCLK; see
Figure 14. The Data may transition on either rising or falling
edge of DCLK. Any offset from this timing is tOSK; see Table
14 for details. The DCLK rising / falling edge may be selected
via the SDR bit in the Configuration Register (Addr: 0h; Bit:
2) in ECM only. Note that SDR is available in Demux Mode,
but not in Non-Demux Mode.
17.3.1.6 Sampling Clock Phase Adjust
The sampling clock (CLK) phase may be delayed internally to
the ADC up to 825 ps in ECM. This feature is intended to help
the system designer remove small imbalances in clock distri-
bution traces at the board level when multiple ADCs are used,
or to simplify complex system functions such as beam steer-
ing for phase array antennas.
Additional delay in the clock path also creates additional jitter
when using the sampling clock phase adjust. Because the
sampling clock phase adjust delays all clocks, including the
DCLKs and output data, the user is strongly advised to use
the minimal amount of adjustment and verify the net benefit
of this feature in his system before relying on it.
Using this feature at its maximum setting, for the maximum
sampling clock rate, may affect the integrity of the sampling
clock on chip. Therefore, it is not recommended to do so. The
maximum setting for the coarse adjust is 825ps. The period
30164315
FIGURE 14. SDR DCLK-to-Data Phase Relationship
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17.3.2.2 LVDS Output Differential Voltage
TABLE 22. Test Pattern by Output Port in
Demux Mode
The ADC12D1800RF is available with a selectable higher or
lower LVDS output differential voltage. This parameter is
VOD and may be found in Table 12. The desired voltage may
be selected via the OVS Bit (Addr: 0h, Bit 13). For many ap-
plications, in which the LVDS outputs are very close to an
FPGA on the same board, for example, the lower setting is
sufficient for good performance; this will also reduce the pos-
sibility for EMI from the LVDS outputs to other signals on the
board. See Section 19.0 Register Definitions for more infor-
mation.
Time Qd
Id
Q
I
ORQ ORI Comments
T0 000h 004h 008h 010h 0b 0b
T1 FFFh FFBh FF7h FEFh 1b 1b
T2 000h 004h 008h 010h 0b 0b
T3 FFFh FFBh FF7h FEFh 1b 1b
T4 000h 004h 008h 010h 0b 0b
T5 000h 004h 008h 010h 0b 0b
T6 FFFh FFBh FF7h FEFh 1b 1b
T7 000h 004h 008h 010h 0b 0b
T8 FFFh FFBh FF7h FEFh 1b 1b
T9 000h 004h 008h 010h 0b 0b
T10 000h 004h 008h 010h 0b 0b
T11 FFFh FFBh FF7h FEFh 1b 1b
T12 000h 004h 008h 010h 0b 0b
Pattern
Sequence
n
Pattern
Sequence
n+1
17.3.2.3 LVDS Output Common-Mode Voltage
The ADC12D1800RF is available with a selectable higher or
lower LVDS output common-mode voltage. This parameter is
VOS and may be found in Table 12. See Section 17.2.1.11
LVDS Output Common-mode Pin (VBG) for information on
how to select the desired voltage.
Pattern
Sequence
n+2
17.3.2.4 Output Formatting
The formatting at the digital data outputs may be either offset
binary or two's complement. The default formatting is offset
binary, but two's complement may be selected via the 2SC
Bit (Addr: 0h, Bit 4); see Section 19.0 Register Definitions for
more information.
T13
...
...
...
...
...
...
When the part is programmed into the Non-Demux Mode, the
test pattern’s order is described in Table 23.
TABLE 23. Test Pattern by Output Port in
Non-Demux Mode
17.3.2.5 Demux/Non-demux Mode
The ADC12D1800RF may be in one of two demultiplex
modes: Demux Mode or Non-Demux Mode (also sometimes
referred to as 1:1 Demux Mode). In Non-Demux Mode, the
data from the input is simply output at the sampling rate on
one 12-bit bus. In Demux Mode, the data from the input is
output at half the sampling rate, on twice the number of buses.
Demux/Non-Demux Mode may only be selected by the NDM
pin; see Section 17.2.1.2 Non-Demultiplexed Mode Pin
(NDM). In Non-DES Mode, the output data from each channel
may be demultiplexed by a factor of 1:2 (1:2 Demux Non-DES
Mode) or not demultiplexed (Non-Demux Non-DES Mode). In
DES Mode, the output data from both channels interleaved
may be demultiplexed (1:4 Demux DES Mode) or not demul-
tiplexed (Non-Demux DES Mode).
Time
T0
Q
I
ORQ ORI
Comments
000h
000h
FFFh
FFFh
000h
FFFh
000h
FFFh
FFFh
FFFh
000h
000h
FFFh
FFFh
...
004h
004h
FFBh
FFBh
004h
FFBh
004h
FFBh
FFBh
FFBh
004h
004h
FFBh
FFBh
...
0b
0b
1b
1b
0b
1b
0b
1b
1b
1b
0b
0b
1b
1b
...
0b
0b
1b
1b
0b
1b
0b
1b
1b
1b
0b
0b
1b
1b
...
T1
T2
T3
Pattern
Sequence
n
T4
T5
T6
T7
T8
T9
Note that for Non-Demux Mode, 90° DDR Mode and SDR
Mode are not available. See Table 21 for a selection of avail-
able modes.
T10
T11
T12
T13
T14
Pattern
Sequence
n+1
TABLE 21. Supported Demux, Data Rate Modes
Non-Demux Mode
0° Mode only
1:2 Demux Mode
0° Mode / 90° Mode
Rising / Falling Mode
DDR
SDR
Not Available
17.3.2.7 Time Stamp
The Time Stamp feature enables the user to capture the tim-
ing of an external trigger event, relative to the sampled signal.
When enabled via the TSE Bit (Addr: 0h; Bit: 3), the LSB of
the digital outputs (DQd, DQ, DId, DI) captures the trigger in-
formation. In effect, the 12-bit converter becomes an 11-bit
converter and the LSB acts as a 1-bit converter with the same
latency as the 11-bit converter. The trigger should be applied
to the DCLK_RST input. It may be asynchronous to the ADC
sampling clock.
17.3.2.6 Test Pattern Mode
The ADC12D1800RF can provide a test pattern at the four
output buses independently of the input signal to aid in system
debug. In Test Pattern Mode, the ADC is disengaged and a
test pattern generator is connected to the outputs, including
ORI and ORQ. The test pattern output is the same in DES
Mode or Non-DES Mode. Each port is given a unique 12-bit
word, alternating between 1's and 0's. When the part is pro-
grammed into the Demux Mode, the test pattern’s order is
described in Table 22. If the I- or Q-channel is powered down,
the test pattern will not be output for that channel.
17.3.3 Calibration Feature
The ADC12D1800RF calibration must be run to achieve
specified performance. The calibration procedure is exactly
the same regardless of how it was initiated or when it is run.
Calibration trims the analog input differential termination re-
sistors, the CLK input resistor, and sets internal bias currents
which affect the linearity of the converter. This minimizes full-
45
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scale error, offset error, DNL and INL, which results in the
maximum dynamic performance, as measured by: SNR,
THD, SINAD (SNDR) and ENOB.
high at power up, but no calibration will be done and perfor-
mance will be impaired.
If it is necessary to toggle the CalDly Pin during the system
power up sequence, then the CAL Pin / Bit must be set to
logic-high before the toggling and afterwards for 109 Sampling
Clock cycles. This will prevent the power-on calibration, so an
on-command calibration must be executed or the perfor-
mance will be impaired.
17.3.3.1 Calibration Control Pins and Bits
Table 24 is a summary of the pins and bits used for calibration.
See Section 9.0 Ball Descriptions and Equivalent Circuits for
complete pin information and Figure 9 for the timing diagram.
TABLE 24. Calibration Pins
17.3.3.4 On-command Calibration
Pin (Bit)
Name
Function
In addition to the power-on calibration, it is recommended to
execute an on-command calibration whenever the settings or
conditions to the device are altered significantly, in order to
obtain optimal parametric performance. Some examples in-
clude: changing the FSR via ECM, power-cycling either chan-
nel, and switching into or out of DES Mode. For best
performance, it is also recommended that an on-command
calibration be run 20 seconds or more after application of
power and whenever the operating temperature changes sig-
nificantly, relative to the specific system performance require-
ments.
D6
(Addr: 0h;
Bit 15)
CAL
(Calibration)
Initiate calibration
CalDly
(Calibration
Delay)
Select power-on
calibration delay
V4
Adjust calibration
sequence
(Addr: 4h) Calibration Adjust
CalRun
(Calibration
Running)
Due to the nature of the calibration feature, it is recommended
to avoid unnecessary activities on the device while the cali-
bration is taking place. For example, do not read or write to
the Serial Interface or use the DCLK Reset feature while cal-
ibrating the ADC. Doing so will impair the performance of the
device until it is re-calibrated correctly. Also, it is recommend-
ed to not apply a strong narrow-band signal to the analog
inputs during calibration because this may impair the accu-
racy of the calibration; broad spectrum noise is acceptable.
Indicates while
calibration is running
B5
Rtrim+/-
(Input termination
trim resistor)
External resistor used to
calibrate analog and
CLK inputs
C1/D2
Rext+/-
(External
Reference
resistor)
External resistor used to
calibrate internal linearity
C3/D3
17.3.3.5 Calibration Adjust
The sequence of the calibration event itself may be adjusted.
This feature can be used if a shorter calibration time than the
default is required; see tCAL in Table 16. However, the perfor-
mance of the device, when using this feature is not guaran-
teed.
17.3.3.2 How to Execute a Calibration
Calibration may be initiated by holding the CAL pin low for at
least tCAL_L clock cycles, and then holding it high for at least
another tCAL_H clock cycles, as defined in Table 16. The min-
imum tCAL_L and tCAL_H input clock cycle sequences are re-
quired to ensure that random noise does not cause a
calibration to begin when it is not desired. The time taken by
the calibration procedure is specified as tCAL. The CAL Pin is
active in both ECM and Non-ECM. However, in ECM, the CAL
Pin is logically OR'd with the CAL Bit, so both the pin and bit
are required to be set low before executing another calibration
via either pin or bit.
The calibration sequence may be adjusted via CSS (Addr:
4h, Bit 14). The default setting of CSS = 1b executes both
RIN and RIN_CLK Calibration (using Rtrim) and internal linearity
Calibration (using Rext). Executing a calibration with CSS =
0b executes only the internal linearity Calibration. The first
time that Calibration is executed, it must be with CSS = 1b to
trim RIN and RIN_CLK. However, once the device is at its op-
erating temperature and RIN has been trimmed at least one
time, it will not drift significantly. To save time in subsequent
calibrations, trimming RIN and RIN_CLK may be skipped, i.e. by
setting CSS = 0b.
17.3.3.3 Power-on Calibration
For standard operation, power-on calibration begins after a
time delay following the application of power, as determined
by the setting of the CalDly Pin and measured by tCalDly (see
Table 16). This delay allows the power supply to come up and
stabilize before the power-on calibration takes place. The
best setting (short or long) of the CalDly Pin depends upon
the settling time of the power supply.
17.3.3.6 Read / Write Calibration Settings
When the ADC performs a calibration, the calibration con-
stants are stored in an array which is accessible via the
Calibration Values register (Addr: 5h). To save the time which
it takes to execute a calibration, tCAL, or to allow for re-use of
a previous calibration result, these values can be read from
and written to the register at a later time. For example, if an
application requires the same input impedance, RIN, this fea-
ture can be used to load a previously determined set of
values. For the calibration values to be valid, the ADC must
be operating under the same conditions, including tempera-
ture, at which the calibration values were originally deter-
mined by the ADC.
It is strongly recommended to set CalDly Pin (to either logic-
high or logic-low) before powering the device on since this pin
affects the power-on calibration timing. This may be accom-
plished by setting CalDly via an external 1kΩ resistor con-
nected to GND or VA. If the CalDly Pin is toggled while the
device is powered-on, it can execute a calibration even
though the CAL Pin / Bit remains logic-low.
The power-on calibration will be not be performed if the CAL
pin is logic-high at power-on. In this case, the calibration cycle
will not begin until the on-command calibration conditions are
met. The ADC12D1800RF will function with the CAL pin held
To read calibration values from the SPI, do the following:
1. Set ADC to desired operating conditions.
2. Set SSC (Addr: 4h, Bit 7) to 1.
3. Power down both I- and Q-channels.
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46
4. Read exactly 240 times the Calibration Values register
(Addr: 5h). The register values are R0, R1, R2... R239. The
contents of R<239:0> should be stored.
directly after power up. Therefore, a new calibration should
be executed upon powering the ADC12D1800RF back up. In
general, the ADC12D1800RF should be recalibrated when
either or both channels are powered back up, or after one
channel is powered down. For best results, this should be
done after the device has stabilized to its operating tempera-
ture.
5. Power up I- and Q-channels to original setting.
6. Set SSC (Addr: 4h, Bit 7) to 0.
7. Continue with normal operation.
To write calibration values to the SPI, do the following:
17.3.3.8 Calibration and the Digital Outputs
1. Set ADC to operating conditions at which Calibration Val-
ues were previously read.
During calibration, the digital outputs (including DI, DId, DQ,
DQd and OR) are set logic-low, to reduce noise. The DCLK
runs continuously during calibration. After the calibration is
completed and the CalRun signal is logic-low, it takes an ad-
ditional 60 Sampling Clock cycles before the output of the
ADC12D1800RF is valid converted data from the analog in-
puts. This is the time it takes for the pipeline to flush, as well
as for other internal processes.
2. Set SSC (Addr: 4h, Bit 7) to 1.
3. Power down both I- and Q-channels.
4. Write exactly 240 times the Calibration Values register (Ad-
dr: 5h). The registers should be written R0, R1... R239.
5. Make two additional dummy writes of 0000h.
6. Power up I- and Q-channels to original setting.
7. Set SSC (Addr: 4h, Bit 7) to 0.
17.3.4 Power Down
8. Continue with normal operation.
On the ADC12D1800RF, the I- and Q-channels may be pow-
ered down individually. This may be accomplished via the
control pins, PDI and PDQ, or via ECM. In ECM, the PDI and
PDQ pins are logically OR'd with the Control Register setting.
See Section 17.2.1.6 Power Down I-channel Pin (PDI)
andSection 17.2.1.7 Power Down Q-channel Pin (PDQ) for
more information.
17.3.3.7 Calibration and Power-Down
If PDI and PDQ are simultaneously asserted during a cali-
bration cycle, the ADC12D1800RF will immediately power
down. The calibration cycle will continue when either or both
channels are powered back up, but the calibration will be
compromised due to the incomplete settling of bias currents
47
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18.0 Applications Information
18.1 THE ANALOG INPUTS
The ADC12D1800RF will continuously convert any signal
which is present at the analog inputs, as long as a CLK signal
is also provided to the device. This section covers important
aspects related to the analog inputs including: acquiring the
input, driving the ADC in DES Mode, the reference voltage
and FSR, out-of-range indication, AC/DC-coupled signals,
and single-ended input signals.
18.1.1 Acquiring the Input
The Aperture Delay, tAD, is the amount of delay, measured
from the sampling edge of the clock input, after which the sig-
nal present at the input pin is sampled inside the device. Data
is acquired at the rising edge of CLK+ in Non-DES Mode and
both the falling and rising edge of CLK+ in DES Mode. In Non-
DES Mode, the I- and Q-channels always sample data on the
rising edge of CLK+. In DES Mode, i.e. DESI, DESQ, DESIQ,
and DESCLKIQ, the I-channel samples data on the rising
edge of CLK+ and the Q-channel samples data on the falling
edge of CLK+. The digital equivalent of that data is available
at the digital outputs a constant number of sampling clock cy-
cles later for the DI, DQ, DId and DQd output busses, a.k.a.
the latency, depending on the demultiplex mode which is se-
lected. In addition to the latency, there is a constant output
delay, tOD, before the data is available at the outputs. See
tOD in the Timing Diagrams. See tLAT, tAD, and tOD in Table
14.
30164313
FIGURE 15. Driving DESIQ Mode
In the case that only one channel is used in Non-DES Mode
or that the ADC is driven in DESI or DESQ Mode, the unused
analog input should be terminated to reduce any noise cou-
pling into the ADC. See Table 25 for details.
TABLE 25. Unused Analog Input Recommended
Termination
Mode
Power Coupling Recommended
Down
Termination
Non-DES Yes
AC/DC
DC
Tie Unused+ and
Unused- to Vbg
18.1.2 Driving the ADC in DES Mode
DES/
Non-DES
No
No
Tie Unused+ and
Unused- to Vbg
The ADC12D1800RF can be configured as either a 2-chan-
nel, 1.8 GSPS device (Non-DES Mode) or a 1-channel 3.6
GSPS device (DES Mode). When the device is configured in
DES Mode, there is a choice for with which input to drive the
single-channel ADC. These are the 3 options:
DES/
Non-DES
AC
Tie Unused+ to Unused-
18.1.3 FSR and the Reference Voltage
DES – externally driving the I-channel input only. This is the
default selection when the ADC is configured in DES Mode.
It may also be referred to as “DESI” for added clarity.
The full-scale analog differential input range (VIN_FSR) of the
ADC12D1800RF is derived from an internal bandgap refer-
ence. In Non-ECM, this full-scale range must be set by the
logic-high setting of the FSR Pin; see Section 17.2.1.9 Full-
Scale Input Range Pin (FSR). The FSR Pin operates on both
I- and Q-channels. In ECM, the full-scale range may be inde-
pendently set for each channel via Addr:3h and Bh with 15
bits of precision; see Section 19.0 Register Definitions. The
best SNR is obtained with a higher full-scale input range, but
better distortion and SFDR are obtained with a lower full-scale
input range. It is not possible to use an external analog ref-
erence voltage to modify the full-scale range, and this adjust-
ment should only be done digitally, as described.
DESQ – externally driving the Q-channel input only.
DESIQ, DESCLKIQ – externally driving both the I- and Q-
channel inputs. VinI+ and VinQ+ should be driven with the
exact same signal. VinI- and VinQ- should be driven with the
exact same signal, which is the differential complement to the
one driving VinI+ and VinQ+.
The input impedance for each I- and Q-input is 100Ω differ-
ential (or 50Ω single-ended), so the trace to each VinI+, VinI-,
VinQ+, and VinQ- should always be 50Ω single-ended. If a
single I- or Q-input is being driven, then that input will present
a 100Ω differential load. For example, if a 50Ω single-ended
source is driving the ADC, then a 1:2 balun will transform the
impedance to 100Ω differential. However, if the ADC is being
driven in DESIQ Mode, then the 100Ω differential impedance
from the I-input will appear in parallel with the Q-input for a
composite load of 50Ω differential and a 1:1 balun would be
appropriate. See Figure 15 for an example circuit driving the
ADC in DESIQ Mode. A recommended part selection is using
the Mini-Circuits TC1-1-13MA+ balun with Ccouple = 0.22µF.
A buffered version of the internal bandgap reference voltage
is made available at the VBG Pin for the user. The VBG pin can
drive a load of up to 80 pF and source or sink up to 100 μA.
It should be buffered if more current than this is required. This
pin remains as a constant reference voltage regardless of
what full-scale range is selected and may be used for a sys-
tem reference. VBG is a dual-purpose pin and it may also be
used to select a higher LVDS output common-mode voltage;
see Section 17.2.1.11 LVDS Output Common-mode Pin
(VBG).
18.1.4 Out-Of-Range Indication
Differential input signals are digitized to 12 bits, based on the
full-scale range. Signal excursions beyond the full-scale
range, i.e. greater than +VIN_FSR/2 or less than -VIN_FSR/2, will
be clipped at the output. An input signal which is above the
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48
FSR will result in all 1's at the output and an input signal which
is below the FSR will result in all 0's at the output. When the
conversion result is clipped for the I-channel input, the Out-
of-Range I-channel (ORI) output is activated such that ORI+
goes high and ORI- goes low while the signal is out of range.
This output is active as long as accurate data on either or both
of the buses would be outside the range of 000h to FFFh. The
Q-channel has a separate ORQ which functions similarly.
voltage of the driving device should track this change. Full-
scale distortion performance falls off as the input common
mode voltage deviates from VCMO. Therefore, it is recom-
mended to keep the input common-mode voltage within 100
mV of VCMO (typical), although this range may be extended to
±150 mV (maximum). See VCMI in Table 8 and ENOB vs.
VCMI in Section 16.0 Typical Performance Plots . Performance
in AC- and DC-coupled Mode are similar, provided that the
input common mode voltage at both analog inputs remains
18.1.5 Maximum Input Range
within 100 mV of VCMO
.
The recommended operating and absolute maximum input
range may be found in Section 11.0 Operating Ratings and
Section 10.0 Absolute Maximum Ratings, respectively. Under
the stated allowed operating conditions, each Vin+ and Vin-
input pin may be operated in the range from 0V to 2.15V if the
input is a continuous 100% duty cycle signal and from 0V to
2.5V if the input is a 10% duty cycle signal. The absolute
maximum input range for Vin+ and Vin- is from -0.15V to 2.5V.
These limits apply only for input signals for which the input
common mode voltage is properly maintained.
18.1.8 Single-Ended Input Signals
The analog inputs of the ADC12D1800RF are not designed
to accept single-ended signals. The best way to handle sin-
gle-ended signals is to first convert them to differential signals
before presenting them to the ADC. The easiest way to ac-
complish single-ended to differential signal conversion is with
an appropriate balun-transformer, as shown in Figure 17.
18.1.6 AC-coupled Input Signals
The ADC12D1800RF analog inputs require a precise com-
mon-mode voltage. This voltage is generated on-chip when
AC-coupling Mode is selected. See Section 17.2.1.10 AC /
DC-Coupled Mode Pin (VCMO) for more information about how
to select AC-coupled Mode.
30164343
In AC-coupled Mode, the analog inputs must of course be AC-
coupled. For an ADC12D1800RF used in a typical applica-
tion, this may be accomplished by on-board capacitors, as
shown in Figure 16. For the ADC12D1800RFRB, the SMA
inputs on the Reference Board are directly connected to the
analog inputs on the ADC12D1800RF, so this may be ac-
complished by DC blocks (included with the hardware kit).
FIGURE 17. Single-Ended to Differential Conversion
Using a Balun
When selecting a balun, it is important to understand the input
architecture of the ADC. The impedance of the analog source
should be matched to the ADC12D1800RF's on-chip 100Ω
differential input termination resistor. The range of this termi-
nation resistor is specified as RIN in Table 8.
When the AC-coupled Mode is selected, an analog input
channel that is not used (e.g. in DES Mode) should be con-
nected to AC ground, e.g. through capacitors to ground . Do
not connect an unused analog input directly to ground.
18.2 THE CLOCK INPUTS
The ADC12D1800RF has a differential clock input, CLK+ and
CLK-, which must be driven with an AC-coupled, differential
clock signal. This provides the level shifting necessary to al-
low for the clock to be driven with LVDS, PECL, LVPECL, or
CML levels. The clock inputs are internally terminated to
100Ω differential and self-biased. This section covers cou-
pling, frequency range, level, duty-cycle, jitter, and layout
considerations.
18.2.1 CLK Coupling
The clock inputs of the ADC12D1800RF must be capacitively
coupled to the clock pins as indicated in Figure 18.
30164344
FIGURE 16. AC-coupled Differential Input
The analog inputs for the ADC12D1800RF are internally
buffered, which simplifies the task of driving these inputs and
the RC pole which is generally used at sampling ADC inputs
is not required. If the user desires to place an amplifier circuit
before the ADC, care should be taken to choose an amplifier
with adequate noise and distortion performance, and ade-
quate gain at the frequencies used for the application.
18.1.7 DC-coupled Input Signals
30164347
In DC-coupled Mode, the ADC12D1800RF differential inputs
must have the correct common-mode voltage. This voltage is
provided by the device itself at the VCMO output pin. It is rec-
ommended to use this voltage because the VCMO output
potential will change with temperature and the common-mode
FIGURE 18. Differential Input Clock Connection
49
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The choice of capacitor value will depend on the clock fre-
quency, capacitor component characteristics and other sys-
tem economic factors. For example, on the ADC12D1800R-
FRB, the capacitors have the value Ccouple = 4.7 nF which
yields a high pass cutoff frequency, fc = 677.2 kHz.
using a balun), be terminated at the clock source in that
(100Ω) characteristic impedance.
It is good practice to keep the ADC input clock line as short
as possible, tightly coupled, keep it well away from any other
signals, and treat it as a transmission line. Otherwise, other
signals can introduce jitter into the input clock signal. Also, the
clock signal can introduce noise into the analog path if it is not
properly isolated.
18.2.2 CLK Frequency
Although the ADC12D1800RF is tested and its performance
is guaranteed with a differential 1.8 GHz sampling clock, it will
typically function well over the input clock frequency range;
see fCLK(min) and fCLK(max) in Table 14. Operation up to fCLK
(max) is possible if the maximum ambient temperatures indi-
cated are not exceeded. Operating at sample rates above
fCLK(max) for the maximum ambient temperature may result
in reduced device reliability and product lifetime. This is due
to the fact that higher sample rates results in higher power
consumption and die temperatures. If fCLK < 300 MHz, enable
LFS in the Control Register (Addr: 0h, Bit 8).
18.3 THE LVDS OUTPUTS
The Data, ORI, ORQ, DCLKI and DCLKQ outputs are LVDS.
The electrical specifications of the LVDS outputs are com-
patible with typical LVDS receivers available on ASIC and
FPGA chips; but they are not IEEE or ANSI communications
standards compliant due to the low +1.9V supply used on this
chip. These outputs should be terminated with a 100Ω differ-
ential resistor placed as closely to the receiver as possible. If
the 100Ω differential resistor is built in to the receiver, then an
externally placed resistor is not necessary. This section cov-
ers common-mode and differential voltage, and data rate.
18.2.3 CLK Level
The input clock amplitude is specified as VIN_CLK in Table
10. Input clock amplitudes above the max VIN_CLK may result
in increased input offset voltage. This would cause the con-
verter to produce an output code other than the expected
2047/2048 when both input pins are at the same potential.
Insufficient input clock levels will result in poor dynamic per-
formance. Both of these results may be avoided by keeping
the clock input amplitude within the specified limits of
18.3.1 Common-mode and Differential Voltage
The LVDS outputs have selectable common-mode and dif-
ferential voltage, VOS and VOD; see Table 12. See Sec-
tion 17.3.2 Output Control and Adjust for more information.
Selecting the higher VOS will also increase VOD slightly. The
differential voltage, VOD, may be selected for the higher or
lower value. For short LVDS lines and low noise systems,
satisfactory performance may be realized with the lower
VOD. This will also result in lower power consumption. If the
LVDS lines are long and/or the system in which the
ADC12D1800RF is used is noisy, it may be necessary to se-
VIN_CLK
.
18.2.4 CLK Duty Cycle
The duty cycle of the input clock signal can affect the perfor-
mance of any A/D converter. The ADC12D1800RF features
a duty cycle clock correction circuit which can maintain per-
formance over the 20%-to-80% specified clock duty-cycle
range. This feature is enabled by default and provides im-
proved ADC clocking, especially in the Dual-Edge Sampling
(DES) Mode.
lect the higher VOD
.
18.3.2 Output Data Rate
The data is produced at the output at the same rate it is sam-
pled at the input. The minimum recommended input clock rate
for this device is fCLK(MIN); see Table 14. However, it is possi-
ble to operate the device in 1:2 Demux Mode and capture data
from just one 12-bit bus, e.g. just DI (or DId) although both DI
and DId are fully operational. This will decimate the data by
two and effectively halve the data rate.
18.2.5 CLK Jitter
High speed, high performance ADCs such as the AD-
C12D1800RF require a very stable input clock signal with
minimum phase noise or jitter. ADC jitter requirements are
defined by the ADC resolution (number of bits), maximum
ADC input frequency and the input signal amplitude relative
to the ADC input full scale range. The maximum jitter (the sum
of the jitter from all sources) allowed to prevent a jitter-induced
reduction in SNR is found to be
18.3.3 Terminating Unused LVDS Output Pins
If the ADC is used in Non-Demux Mode, then only the DI and
DQ data outputs will have valid data present on them. The
DId and DQd data outputs may be left not connected; if un-
used, they are internally at TRI-STATE.
tJ(MAX) = ( VIN(P-P)/ VFSR) x (1/(2(N+1) x π x fIN))
Similarly, if the Q-channel is powered-down (i.e. PDQ is logic-
high), the DQ data output pins, DCLKQ and ORQ may be left
not connected.
where tJ(MAX) is the rms total of all jitter sources in seconds,
VIN(P-P) is the peak-to-peak analog input signal, VFSR is the
full-scale range of the ADC, "N" is the ADC resolution in bits
and fIN is the maximum input frequency, in Hertz, at the ADC
analog input.
18.4 SYNCHRONIZING MULTIPLE ADC12D1800RFS IN A
SYSTEM
The ADC12D1800RF has two features to assist the user with
synchronizing multiple ADCs in a system; AutoSync and
DCLK Reset. The AutoSync feature and designates one AD-
C12D1800RF as the Master ADC and other AD-
C12D1800RFs in the system as Slave ADCs. The DCLK
Reset feature performs the same function as the AutoSync
feature, but is the first generation solution to synchronizing
multiple ADCs in a system; it is disabled by default. For the
application in which there are multiple Master and Slave AD-
C12D1800RFs in a system, AutoSync may be used to syn-
chronize the Slave ADC12D1800RF(s) to each respective
Master ADC12D1800RF and the DCLK Reset may be used
to synchronize the Master ADC12D1800RFs to each other.
tJ(MAX) is the square root of the sum of the squares (RSS) sum
of the jitter from all sources, including: the ADC input clock,
system, input signals and the ADC itself. Since the effective
jitter added by the ADC is beyond user control, it is recom-
mended to keep the sum of all other externally added jitter to
a minimum.
18.2.6 CLK Layout
The ADC12D1800RF clock input is internally terminated with
a trimmed 100Ω resistor. The differential input clock line pair
should have a characteristic impedance of 100Ω and (when
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If the AutoSync or DCLK Reset feature is not used, see Table
26 for recommendations about terminating unused pins.
used to synchronize the DCLK and data outputs of one or
more Slave ADC12D1800RFs to one Master AD-
C12D1800RF. Several advantages of this feature include: no
special synchronization pulse required, any upset in synchro-
nization is recovered upon the next DCLK cycle, and the
Master / Slave ADC12D1800RFs may be arranged as a bi-
nary tree so that any upset will quickly propagate out of the
system.
TABLE 26. Unused AutoSync and DCLK Reset Pin
Recommendation
Pin(s)
Unused termination
Do not connect.
RCLK+/-
RCOUT1+/-
RCOUT2+/-
DCLK_RST+
DCLK_RST-
Do not connect.
An example system is shown below in Figure 19 which con-
sists of one Master ADC and two Slave ADCs. For simplicity,
only one DCLK is shown; in reality, there is DCLKI and
DCLKQ, but they are always in phase with one another.
Do not connect.
Connect to GND via 1kΩ resistor.
Connect to VA via 1kΩ resistor.
18.4.1 AutoSync Feature
AutoSync is a feature which continuously synchronizes the
outputs of multiple ADC12D1800RFs in a system. It may be
30164303
FIGURE 19. AutoSync Example
In order to synchronize the DCLK (and Data) outputs of mul-
tiple ADCs, the DCLKs must transition at the same time, as
well as be in phase with one another. The DCLK at each ADC
is generated from the CLK after some latency, plus tOD minus
tAD. Therefore, in order for the DCLKs to transition at the same
time, the CLK signal must reach each ADC at the same time.
To tune out any differences in the CLK path to each ADC, the
tAD adjust feature may be used. However, using the tAD adjust
feature will also affect when the DCLK is produced at the out-
put. If the device is in Demux Mode, then there are four
possible phases which each DCLK may be generated on be-
cause the typical CLK = 1.8 GHz and DCLK = 450 MHz for
this case. The RCLK signal controls the phase of the DCLK,
so that each Slave DCLK is on the same phase as the Master
DCLK.
The DCLK_RST signal can be asserted asynchronously to
the input clock. If DCLK_RST is asserted, the DCLK output is
held in a designated state (logic-high) in Demux Mode; in
Non-Demux Mode, the DCLK continues to function normally.
Depending upon when the DCLK_RST signal is asserted,
there may be a narrow pulse on the DCLK line during this
reset event. When the DCLK_RST signal is de-asserted,
there are tSYNC_DLY CLK cycles of systematic delay and the
next CLK rising edge synchronizes the DCLK output with
those of other ADC12D1800RFs in the system. For 90° Mode
(DDRPh = logic-high), the synchronizing edge occurs on the
rising edge of CLK, 4 cycles after the first rising edge of CLK
after DCLK_RST is released. For 0° Mode (DDRPh = logic-
low), this is 5 cycles instead. The DCLK output is enabled
again after a constant delay of tOD
.
The AutoSync feature may only be used via the Control Reg-
isters. For more information, see AN-2132.
For both Demux and Non-Demux Modes, there is some un-
certainty about how DCLK comes out of the reset state for the
first DCLK_RST pulse. For the second (and subsequent)
DCLK_RST pulses, the DCLK will come out of the reset state
in a known way. Therefore, if using the DCLK Reset feature,
it is recommended to apply one "dummy" DCLK_RST pulse
before using the second DCLK_RST pulse to synchronize the
outputs. This recommendation applies each time the device
or channel is powered-on.
18.4.2 DCLK Reset Feature
The DCLK reset feature is available via ECM, but it is disabled
by default. DCLKI and DCLKQ are always synchronized, by
design, and do not require a pulse from DCLK_RST to be-
come synchronized.
The DCLK_RST signal must observe certain timing require-
ments, which are shown in Figure 8 of the Timing Diagrams.
The DCLK_RST pulse must be of a minimum width and its
deassertion edge must observe setup and hold times with re-
spect to the CLK input rising edge. These timing specifica-
tions are listed as tPWR, tSR and tHR and may be found in Table
14.
When using DCLK_RST to synchronize multiple
ADC12D1800RFs, it is required that the Select Phase bits in
the Control Register (Addr: Eh, Bits 3,4) be the same for each
Master ADC12D1800RF.
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18.5 SUPPLY / GROUNDING, LAYOUT AND THERMAL
RECOMMENDATIONS
nect the power source net to the individual nets for the differ-
ent ADC power buses. As a final step, the zero ohm resistors
can be removed and the plane and peninsulas can be con-
nected manually after all other error checking is completed.
18.5.1 Power Planes
All supply buses for the ADC should be sourced from a com-
mon linear voltage regulator. This ensures that all power
buses to the ADC are turned on and off simultaneously. This
single source will be split into individual sections of the power
plane, with individual decoupling and connection to the dif-
ferent power supply buses of the ADC. Due to the low voltage
but relatively high supply current requirement, the optimal so-
lution may be to use a switching regulator to provide an
intermediate low voltage, which is then regulated down to the
final ADC supply voltage by a linear regulator. Please refer to
the documentation provided for the ADC12D1800RFRB for
additional details on specific regulators that are recommend-
ed for this configuration.
18.5.2 Bypass Capacitors
The general recommendation is to have one 100nF capacitor
for each power / ground pin pair. The capacitors should be
surface mount multi-layer ceramic chip capacitors similar to
Panasonic part number ECJ-0EB1A104K.
18.5.3 Ground Planes
Grounding should be done using continuous full ground
planes to minimize the impedance for all ground return paths,
and provide the shortest possible image/return path for all
signal traces.
18.5.4 Power System Example
Power for the ADC should be provided through a broad plane
which is located on one layer adjacent to the ground plane(s).
Placing the power and ground planes on adjacent layers will
provide low impedance decoupling of the ADC supplies, es-
pecially at higher frequencies. The output of a linear regulator
should feed into the power plane through a low impedance
multi-via connection. The power plane should be split into in-
dividual power peninsulas near the ADC. Each peninsula
should feed a particular power bus on the ADC, with decou-
pling for that power bus connecting the peninsula to the
ground plane near each power / ground pin pair. Using this
technique can be difficult on many printed circuit CAD tools.
To work around this, zero ohm resistors can be used to con-
The ADC12D1800RFRB uses continuous ground planes (ex-
cept where clear areas are needed to provide appropriate
impedance management for specific signals), see Figure 20.
Power is provided on one plane, with the 1.9V ADC supply
being split into multiple zones or peninsulas for the specific
power buses of the ADC. Decoupling capacitors are connect-
ed between these power bus peninsulas and the adjacent
ground planes using vias. The capacitors are located as close
to the individual power / ground pin pairs of the ADC as pos-
sible. In most cases, this means the capacitors are located on
the opposite side of the PCB to the ADC.
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30164302
FIGURE 20. Power and Grounding Example
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18.5.5 Thermal Management
attached to the substrate top with exposed metal in the center
top area of the package. This results in a 20% improvement
(typical) in thermal performance over the standard plastic
BGA package.
The Heat Slug Ball Grid Array (HSBGA) package is a modified
version of the industry standard plastic BGA (Ball Grid Array)
package. Inside the package, a copper heat spreader cap is
30164309
FIGURE 21. HSBGA Conceptual Drawing
The center balls are connected to the bottom of the die by vias
in the package substrate, Figure 21. This gives a low thermal
resistance between the die and these balls. Connecting these
balls to the PCB ground planes with a low thermal resistance
path is the best way dissipate the heat from the ADC. These
pins should also be connected to the ground plane via a low
impedance path for electrical purposes. The direct connection
to the ground planes is an easy method to spread heat away
from the ADC. Along with the ground plane, the parallel power
planes will provide additional thermal dissipation.
added. Representative heat sinks which might be used with
the ADC12D1800RF include the Cool Innovations p/n
3-1212XXG and similar products from other vendors. In many
applications, the printed circuit board will provide the primary
thermal path conducting heat away from the ADC package.
In those cases, θJC2 can be used in conjunction with printed
circuit board thermal modeling software to determine the al-
lowed operating conditions that will maintain the die temper-
ature below the maximum allowable limit. Additional dissipa-
tion can be achieved by coupling a heat sink to the copper
pour area on the bottom side of the printed circuit board.
The center ground balls should be soldered down to the rec-
ommended ball pads (See AN-1126). These balls will have
wide traces which in turn have vias which connect to the in-
ternal ground planes, and a bottom ground pad / pour if
possible. This ensures a good ground is provided for these
balls, and that the optimal heat transfer will occur between
these balls and the PCB ground planes.
Typically, dissipation will occur through one predominant
thermal path. In these cases, the following calculations can
be used to determine the maximum safe ambient operating
temperature:
TJ = TA + PD × (θJC+θCA
)
TJ = TA + PC(MAX) × (θJC+θCA
)
In spite of these package enhancements, analysis using the
standard JEDEC JESD51-7 four-layer PCB thermal model
shows that ambient temperatures must be limited to a max of
65°C to ensure a safe operating junction temperature for the
ADC12D1800RF. However, most applications using the AD-
C12D1800RF will have a printed circuit board which is more
complex than that used in JESD51-7. Typical circuit boards
will have more layers than the JESD51-7 (eight or more),
several of which will be used for ground and power planes. In
those applications, the thermal resistance parameters of the
ADC12D1800RF and the circuit board can be used to deter-
mine the actual safe ambient operating temperature up to a
maximum of 85°C.
For θJC, the value for the primary thermal path in the given
application environment should be used (θJC1 or θJC2). θCA is
the thermal resistance from the case to ambient, which would
typically be that of the heat sink used. Using this relationship
and the desired ambient temperature, the required heat sink
thermal resistance can be found. Alternately, the heat sink
thermal resistance can be used to find the maximum ambient
temperature. For more complex systems, thermal modeling
software can be used to evaluate the printed circuit board
system and determine the expected junction temperature giv-
en the total system dissipation and ambient temperature.
18.6 SYSTEM POWER-ON CONSIDERATIONS
Three key parameters are provided to allow for modeling and
calculations. Because there are two main thermal paths be-
tween the ADC die and external environment, the thermal
resistance for each of these paths is provided. θJC1 represents
the thermal resistance between the die and the exposed met-
al area on the top of the HSBGA package. θJC2 represents the
thermal resistance between the die and the center group of
balls on the bottom of the HSBGA package. The final param-
eter is the allowed maximum junction temperature, which is
TJ.
There are a couple important topics to consider associated
with the system power-on event including configuration and
calibration, and the Data Clock.
18.6.1 Power-on, Configuration, and Calibration
Following the application of power to the ADC12D1800RF,
several events must take place before the output from the
ADC12D1800RF is valid and at full performance; at least one
full calibration must be executed with the device configured
in the desired mode.
In other applications, a heat sink or other thermally conductive
path can be added to the top of the HSBGA package to re-
move heat. In those cases, θJC1 can be used along with the
thermal parameters for the heat sink or other thermal coupling
Following the application of power to the ADC12D1800RF,
there is a delay of tCalDly and then the Power-on Calibration is
executed. This is why it is recommended to set the CalDly Pin
via an external pull-up or pull-down resistor. This ensured that
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the state of that input will be properly set at the same time that
power is applied to the ADC and tCalDly will be a known quan-
tity. For the purpose of this section, it is assumed that CalDly
is set as recommended.
Another case is when the FPGA configures the Control Pins
(Non-ECM) or writes to the SPI (ECM), see Figure 23. It is
always necessary to comply with the Operating Ratings and
Absolute Maximum ratings, i.e. the Control Pins may not be
driven below the ground or above the supply, regardless of
what the voltage currently applied to the supply is. Therefore,
it is not recommended to write to the Control Pins or SPI be-
fore power is applied to the ADC12D1800RF. As long as the
FPGA has completed writing to the Control Pins or SPI, the
Power-on Calibration will result in a valid output at full perfor-
mance. Once again, if it takes longer than tCalDly for the system
to stabilize at its operating temperature, it is recommended to
execute an on-command calibration at that time.
The Control Bits or Pins must be set or written to configure
the ADC12D1800RF in the desired mode. This must take
place via either Extended Control Mode or Non-ECM (Pin
Control Mode) before subsequent calibrations will yield an
output at full performance in that mode. Some examples of
modes include DES/Non-DES Mode, Demux/Non-demux
Mode, and Full-Scale Range.
The simplest case is when device is in Non-ECM and the
Control Pins are set by pull-up / down resistors, see Figure
22. For this case, the settings to the Control Pins ramp con-
currently to the ADC voltage. Following the delay of tCalDly and
the calibration execution time, tCAL, the output of the AD-
C12D1800RF is valid and at full performance. If it takes longer
than tCalDly for the system to stabilize at its operating temper-
ature, it is recommended to execute an on-command calibra-
tion at that time.
Due to system requirements, it may not be possible for the
FPGA to write to the Control Pins or SPI before the Power-on
Calibration takes place, see Figure 24. It is not critical to con-
figure the device before the Power-on Calibration, but it is
critical to realize that the output for such a case is not at its
full performance. Following an On-command Calibration, the
device will be at its full performance.
30164364
FIGURE 22. Power-on with Control Pins set by Pull-up / down Resistors
30164365
FIGURE 23. Power-on with Control Pins set by FPGA pre Power-on Cal
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30164366
FIGURE 24. Power-on with Control Pins set by FPGA post Power-on Cal
18.6.2 Power-on and Data Clock (DCLK)
18.7.1 Temperature Sensor
Many applications use the DCLK output for a system clock.
For the ADC12D1800RF, each I- and Q-channel has its own
DCLKI and DCLKQ, respectively. The DCLK output is always
active, unless that channel is powered-down or the DCLK
Reset feature is used while the device is in Demux Mode. As
the supply to the ADC12D1800RF ramps, the DCLK also
comes up, see this example from the ADC12D1800RFRB:
Figure 25. While the supply is too low, there is no output at
DCLK. As the supply continues to ramp, DCLK functions in-
termittently with irregular frequency, but the amplitude con-
tinues to track with the supply. Much below the low end of
operating supply range of the ADC12D1800RF, the DCLK is
already fully operational.
The ADC12D1800RF has an on-die temperature diode con-
nected to pins Tdiode+/- which may be used to monitor the
die temperature. National also provides a family of tempera-
ture sensors for this application which monitor different num-
bers of external devices, see Table 27.
TABLE 27. Temperature Sensor Recommendation
Number of External Recommended Temperature
Devices Monitored
Sensor
LM95235
LM95213
LM95214
1
2
4
The temperature sensor (LM95235/13/14) is an 11-bit digital
temperature sensor with a 2-wire System Management Bus
(SMBus) interface that can monitor the temperature of one,
two, or four remote diodes as well as its own temperature. It
can be used to accurately monitor the temperature of up to
one, two, or four external devices such as the AD-
C12D1800RF, a FPGA, other system components, and the
ambient temperature.
The temperature sensor reports temperature in two different
formats for +127.875°C/-128°C range and 0°/255°C range. It
has a Sigma-Delta ADC core which provides the first level of
noise immunity. For improved performance in a noisy envi-
ronment, the temperature sensor includes programmable dig-
ital filters for Remote Diode temperature readings. When the
digital filters are invoked, the resolution for the Remote Diode
readings increases to 0.03125°C. For maximum flexibility and
best accuracy, the temperature sensor includes offset regis-
ters that allow calibration for other types of diodes.
Diode fault detection circuitry in the temperature sensor can
detect the absence or fault state of a remote diode: whether
D+ is shorted to the power supply, D- or ground, or floating.
30164390
In the following typical application, the LM95213 is used to
monitor the temperature of an ADC12D1800RF as well as an
FPGA, see Figure 26. If this feature is unused, the Tdiode+/-
pins may be left floating.
FIGURE 25. Supply and DCLK Ramping
18.7 RECOMMENDED SYSTEM CHIPS
National recommends these other chips including tempera-
ture sensors, clocking devices, and amplifiers in order to
support the ADC12D1800RF in a system design.
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30164397
FIGURE 26. Typical Temperature Sensor Application
18.7.2 Clocking Device
18.7.4 Balun Recommendations for Analog Input
The clock source can be a PLL/VCO device such as the
LMX2531LQxxxx family of products. The specific device
should be selected according to the desired ADC sampling
clock frequency. The ADC12D1800RFRB uses the
LMX2531LQ1778E, with the ADC clock source provided by
the Aux PLL output. Other devices which may be considered
based on clock source, jitter cleaning, and distribution pur-
poses are the LMK01XXX, LMK02XXX, LMK03XXX and
LMK04XXX product families.
The following baluns are recommended for the
ADC12D1800RF for applications which require no gain.
When evaluating a balun for the application of driving an ADC,
some important qualities to consider are phase error and
magnitude error.
TABLE 29. Balun Recommendations
Balun
Bandwidth
Mini-Circuits TC1-1-13MA+ 4.5 - 3000 MHz
Anaren B0430J50100A00 400 - 3000 MHz
18.7.3 Amplifiers for Analog Input
The following amplifiers can be used for ADC12D1800RF ap-
plications which require DC coupled input or signal gain,
neither of which can be provided with a transformer coupled
input circuit:
Mini-Circuits ADTL2-18
30 - 1800 MHz
TABLE 28. Amplifier Recommendation
Amplifier
LMH6552
LMH6553
Bandwidth Brief features
1.5 GHz
900 MHz
Configurable gain
Output clamp and
configurable gain
LMH6554
LMH6555
2.8 GHz
1.2 GHz
Configurable gain
Fixed gain
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19.0 Register Definitions
Twelve read / write registers provide several control and configuration options in the Extended Control Mode. These registers have
no effect when the device is in the Non-extended Control Mode. Each register description below also shows the Power-On Reset
(POR) state of each control bit. See Table 30 for a summary. For a description of the functionality and timing to read / write the
control registers, see Section 17.2.2.1 The Serial Interface.
Special Note: Register 6h must be written to 1C0Eh for the device to perform at full rated performance for Fclk > 1.6GHz.
TABLE 30. Register Addresses
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hex
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
Register Addressed
Configuration Register 1
Reserved
I-channel Offset
I-channel Full-Scale Range
Calibration Adjust
Calibration Values
Bias Adjust
DES Timing Adjust
Reserved
Reserved
Q-channel Offset
Q-channel Full-Scale Range
Aperture Delay Coarse Adjust
Aperture Delay Fine Adjust
AutoSync
Reserved
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Configuration Register 1
Addr: 0h (0000b)
POR state: 2000h
Bit
Name CAL DPS OVS TPM PDI PDQ Res LFS DES DEQ DIQ 2SC TSE SDR
POR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset
automatically upon completion of the calibration. Therefore, the user must reset this bit to 0b and then set it to 1b
again to execute another calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0b
before either is used to execute a calibration. (Note 19)
Bit 14
DPS: DCLK Phase Select. In DDR Mode, set this bit to 0b to select the 0° Mode DDR Data-to-DCLK phase
relationship and to 1b to select the 90° Mode. In SDR Mode, set this bit to 0b to transition the data on the Rising
edge of DCLK; set this bit to 1b to transition the data on the Falling edge of DCLK.
Bit 13
Bit 12
OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and
DCLK. 0b selects the lower level and 1b selects the higher level. See VOD in Table 12 for details.
TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the
digital Data and OR outputs. When set to 0b, the device will continually output the converted signal, which was
present at the analog inputs. See Section 17.3.2.6 Test Pattern Mode for details about the TPM pattern.
PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational; when it is set to 1b, the I-
channel is powered-down. The I-channel may be powered-down via this bit or the PDI Pin, which is active, even in
ECM.
Bit 11
Bit 10
PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational; when it is set to 1b, the
Q-channel is powered-down. The Q-channel may be powered-down via this bit or the PDQ Pin, which is active,
even in ECM.
Bit 9
Bit 8
Reserved. Must be set to 0b.
LFS: Low-Frequency Select. If the sampling clock (CLK) is at or below 300 MHz, set this bit to 1b for improved
performance.
Bit 7
DES: Dual-Edge Sampling Mode select. When this bit is set to 0b, the device will operate in the Non-DES Mode;
when it is set to 1b, the device will operate in the DES Mode. See Section 17.3.1.4 DES/Non-DES Mode for more
information.
Bit 6
Bit 5
DEQ: DES Q-input select, a.k.a. DESQ Mode. When the device is in DES Mode, this bit selects the input that the
device will operate on. The default setting of 0b selects the I-input and 1b selects the Q-input.
DIQ: DES I- and Q-input, a.k.a. DESIQ Mode. When in DES Mode, setting this bit to 1b shorts the I- and Q-inputs
internally to the device. If the bit is left at its default 0b, the I- and Q-inputs remain electrically separate. To operate
the device in DESIQ Mode, Bits<7:5> must be set to 101b. In this mode, both the I- and Q-inputs must be externally
driven; see Section 17.3.1.4 DES/Non-DES Mode for more information.
The allowed DES Modes settings are shown below: For DESCLKIQ Mode, see Addr Eh.
Mode
Addr 0h, Bits<7:5>
Addr Eh, Bit<6>
Non-DES Mode
DESI Mode
000b
100b
110b
101b
000b
0b
0b
0b
0b
1b
DESQ Mode
DESIQ Mode
DESCLKIQ Mode
Bit 4
Bit 3
Bit 2
2SC: Two's Complement output. For the default setting of 0b, the data is output in Offset Binary format; when set
to 1b, the data is output in Two's Complement format. (Note 19)
TSE: Time Stamp Enable. For the default setting of 0b, the Time Stamp feature is not enabled; when set to 1b, the
feature is enabled. See Section 17.3.2 Output Control and Adjust for more information about this feature.
SDR: Single Data Rate. For the default setting of 0b, the data is clocked in Dual Data Rate; when set to 1b, the data
is clocked in Single Data Rate. See Section 17.3.2 Output Control and Adjust for more information about this feature.
Note that for Non-Demux Mode, only 0° DDR Mode is available. See Table 21 for a selection of available modes.
Reserved. Must be set as shown.
Bits 1:0
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Reserved
Addr: 1h (0001b)
POR state: 2907h
Bit
15
14
13
1
12
0
11
1
10
0
9
0
8
1
7
0
6
0
5
0
4
0
3
0
2
1
0
Name
POR
Res
0
0
1
1
1
Bits 15:0 Reserved. Must be set as shown.
I-channel Offset Adjust
Addr: 2h (0010b)
POR state: 0000h
Bit
15
14
Res
0
13
0
12
OS
0
11
0
10
0
9
0
8
0
7
0
6
5
4
0
3
0
2
1
0
Name
POR
OM(11:0)
0
0
0
0
0
0
Bits 15:13 Reserved. Must be set to 0b.
Bit 12
OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC
output. Setting this bet to 1b incurs a negative offset of the set magnitude.
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight
binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV.
Monotonicity is guaranteed by design only for the 9 MSBs.
Code
Offset [mV]
0000 0000 0000 (default)
1000 0000 0000
1111 1111 1111
0
22.5
45
I-channel Full Scale Range Adjust
Addr: 3h (0011b)
POR state: 4000h
Bit
15
14
13
0
12
0
11
0
10
0
9
0
8
0
7
FM(14:0)
0
6
0
5
0
4
0
3
0
2
1
0
Name Res
POR
0
1
0
0
0
Bit 15
Reserved. Must be set to 0b.
Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The
allowable range is from 800 mV (16384d) to 1000 mV (32767d) with the default setting at 800 mV (16384d).
Monotonicity is guaranteed by design only for the 9 MSBs. A greater range of FSR values is available in ECM,
i.e. FSR values above 800 mV. See VIN_FSR in Table 8 for characterization details.
Code
FSR [mV]
800
100 0000 0000 0000 (default)
111 1111 1111 1111
1000
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60
Calibration Adjust
(Note 18)
Addr: 4h (0100b)
POR state: DB4Bh
Bit
15
14
13
0
12
1
11
1
10
0
9
1
8
1
7
SSC
0
6
1
5
0
4
0
3
Res
1
2
1
0
Name Res CSS
Res
POR
1
1
0
1
1
Bit 15
Bit 14
Reserved. Must be set as shown.
CSS: Calibration Sequence Select. The default 1b selects the following calibration sequence: reset all previously
calibrated elements to nominal values, do RIN Calibration, do internal linearity Calibration. Setting CSS = 0b
selects the following calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal
linearity Calibration. The calibration must be completed at least one time with CSS = 1b to calibrate RIN.
Subsequent calibrations may be run with CSS = 0b (skip RIN calibration) or 1b (full RIN and internal linearity
Calibration).
Bits 13:8 Reserved. Must be set as shown.
Bit 7
SSC: SPI Scan Control. Setting this control bit to 1b allows the calibration values, stored in Addr: 5h, to be read /
written. When not reading / writing the calibration values, this control bit should left at its default 0b setting. See
Section 17.3.3 Calibration Feature for more information.
Bits 6:0
Reserved. Must be set as shown.
Calibration Values
(Note 18)
Addr: 5h (0101b)
POR state: XXXXh
Bit
15
14
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
Name
POR
SS(15:0)
X
X
X
X
X
X
X
X
X
X
X
X
Bits 15:0 SS(15:0): SPI Scan. When the ADC performs a self-calibration, the values for the calibration are stored in this
register and may be read from/ written to it. Set SSC (Addr: 4h, Bit 7) to read / write. See Section 17.3.3 Calibration
Feature for more information.
Bias Adjust
Addr: 6h (0110b)
POR state: 1C2Eh
Bit
15
14
13
0
12
1
11
1
10
1
9
0
8
7
6
0
5
1
4
0
3
1
2
1
0
Name
POR
MPA(15:0)
0
0
0
0
1
1
0
Bits 15:0 MPA(15:0): Max Power Adjust. This register must be written to 1C0Eh to achieve full rated performance
for Fclk > 1.6GHz.
DES Timing Adjust
Addr: 7h (0111b)
POR state: 8142h
Bit
15
14
13
0
12
DTA(6:0)
0
11
0
10
0
9
0
8
1
7
0
6
1
5
0
4
Res
0
3
0
2
1
0
Name
POR
1
0
0
1
0
Bits 15:9 DTA(6:0): DES Mode Timing Adjust. In the DES Mode, the time at which the falling edge sampling clock samples
relative to the rising edge of the sampling clock may be adjusted; the automatic duty cycle correction continues
to function. See Section 17.3.1 Input Control and Adjust for more information. The nominal step size is 30fs.
Bits 8:0
Reserved. Must be set as shown.
61
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Reserved
Addr: 8h (1000b)
POR state: 0F0Fh
Bit
15
14
13
0
12
0
11
1
10
1
9
1
8
1
7
0
6
0
5
0
4
0
3
1
2
1
0
Name
POR
Res
0
0
1
1
1
Bits 15:0 Reserved. Must be set as shown.
Reserved
Addr: 9h (1001b)
POR state: 0000h
Bit
15
14
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
Name
POR
Res
0
0
0
0
0
Bits 15:0 Reserved. Must be set as shown.
Q-channel Offset Adjust
Addr: Ah (1010b)
POR state: 0000h
Bit
15
14
Res
0
13
0
12
OS
0
11
0
10
0
9
0
8
0
7
0
6
5
4
0
3
0
2
1
0
Name
POR
OM(11:0)
0
0
0
0
0
0
Bits 15:13 Reserved. Must be set to 0b.
Bit 12
OS: Offset Sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC
output. Setting this bet to 1b incurs a negative offset of the set magnitude.
Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight
binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV.
Monotonicity is guaranteed by design only for the 9 MSBs.
Code
Offset [mV]
0000 0000 0000 (default)
1000 0000 0000
1111 1111 1111
0
22.5
45
Q-channel Full-Scale Range Adjust
Addr: Bh (1011b)
POR state: 4000h
Bit
15
14
13
0
12
0
11
0
10
0
9
0
8
0
7
FM(14:0)
0
6
0
5
0
4
0
3
0
2
1
0
Name Res
POR
0
1
0
0
0
Bit 15
Reserved. Must be set to 0b.
Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The
allowable range is from 800 mV (16384d) to 1000 mV (32767d) with the default setting at 800 mV (16384d).
Monotonicity is guaranteed by design only for the 9 MSBs. A greater range of FSR values is available in ECM,
i.e. FSR values above 800 mV. See VIN_FSR in Table 8 for characterization details.
Code
FSR [mV]
800
100 0000 0000 0000 (default)
111 1111 1111 1111
1000
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62
Aperture Delay Coarse Adjust
Addr: Ch (1100b)
POR state: 0004h
Bit
15
14
13
0
12
0
11
0
10
9
8
0
7
0
6
0
5
0
4
0
3
2
1
0
Name
POR
CAM(11:0)
STA DCC
Res
0
0
0
0
0
1
0
0
Using the tAD Adjust feature at its maximum setting, for the maximum sampling clock rate, may affect the integrity of the sampling
clock on chip. Therefore, it is not recommended to do so. The maximum setting for the coarse adjust is 825ps. The period for the
maximum sampling clock rate of is 555ps, so it should not be necessary to exceed this value in any case.
Bits 15:4 CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to
the input CLK signal. The range is 0 ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for
CAM(11:0) = 2431d (±95 ps due to PVT variation) in steps of ~340 fs. For code CAM(11:0) = 2432d and above,
the delay saturates and the maximum delay applies. Additional, finer delay steps are available in register Dh.
The STA (Bit 3) must be selected to enable this function.
Bit 3
STA: Select tAD Adjust. Set this bit to 1b to enable the tAD adjust feature, which will make both coarse and fine
adjustment settings, i.e. CAM(11:0) and FAM(5:0), available.
Bit 2
DCC: Duty Cycle Correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the
chip. This feature is enabled by default.
Bits 1:0
Reserved. Must be set to 0b.
Aperture Delay Fine Adjust
(Note 18)
Addr: Dh (1101b)
POR state: 0000h
Bit
15
14
13
12
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
Name
POR
FAM(5:0)
Res
Res
0
0
0
0
0
0
0
Using the tAD Adjust feature at its maximum setting, for the maximum sampling clock rate, may affect the integrity of the sampling
clock on chip. Therefore, it is not recommended to do so. The maximum setting for the coarse adjust is 825ps. The period for the
maximum sampling clock rate of is 555ps, so it should not be necessary to exceed this value in any case.
Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will
be applied to the input CLK when the Clock Phase Adjust feature is enabled via STA (Addr: Ch, Bit 3). The range
is straight binary from 0 ps delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) = 63d (±300 fs due to PVT
variation) in steps of ~36 fs.
Bits 9:0
Reserved. Must be set as shown.
AutoSync
Addr: Eh (1110b)
POR state: 0003h
Bit
15
14
13
0
12
0
11
DRC(8:0)
0
10
0
9
0
8
0
7
0
6
5
4
3
0
2
1
0
Name
POR
DCK Res
SP(1:0)
ES DOC DR
0
0
0
0
0
0
1
1
Bits 15:7 DRC(8:0): Delay Reference Clock (9:0). These bits may be used to increase the delay on the input reference
clock when synchronizing multiple ADCs. The minimum delay is 0s (0d) to 1200 ps (319d). The delay remains
the maximum of 1200 ps for any codes above or equal to 639d. See Section 18.4 SYNCHRONIZING MULTIPLE
ADC12D1800RFS IN A SYSTEM for more information.
Bit 6
DCK: DESCLKIQ Mode. Set this bit to 1b to enable Dual-Edge Sampling, in which the Sampling Clock samples
the I- and Q-channels 180° out of phase with respect to one another, i.e. the DESCLKIQ Mode. To select the
DESCLKIQ Mode, Addr: 0h, Bits<7:5> must also be set to 000b. See Section 17.3.1.4 DES/Non-DES Mode for
more information.
Bit 5
Reserved. Must be set as shown.
63
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Bits 4:3
SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond
to the following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
Bit 2
Bit 1
Bit 0
ES: Enable Slave. Set this bit to 1b to enable the Slave Mode of operation. In this mode, the internal divided
clocks are synchronized with the reference clock coming from the master ADC. The master clock is applied on
the input pins RCLK. If this bit is set to 0b, then the device is in Master Mode.
DOC: Disable Output reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The
default setting of 1b disables these output drivers. This bit functions as described, regardless of whether the
device is operating in Master or Slave Mode, as determined by ES (Bit 2).
DR: Disable Reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to
enable DCLK_RST functionality.
Reserved
Addr: Fh (1111b)
POR state: 001Dh
Bit
15
14
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
0
Name
POR
Res
0
0
1
0
1
Bits 15:0 Reserved. This address is read only.
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64
20.0 Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
REFERENCE JEDEC REGISTRATION MS-034, VARIATION BAL-2.
292-Ball BGA Thermally Enhanced Package
Order Number ADC12D1800RFIUT
NS Package Number UFH292A
65
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