74ACT16640WDLR [TI]
ACT SERIES, DUAL 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO48, 0.300 INCH, 0.025 INCH PITCH, PLASTIC, SSOP-48;
| 型号： | 74ACT16640WDLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ACT SERIES, DUAL 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO48, 0.300 INCH, 0.025 INCH PITCH, PLASTIC, SSOP-48 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总6页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS173A - JULY 1990 - REVISED APRIL 1996
54ACT16640 . . . WD PACKAGE
74ACT16640 . . . DL PACKAGE
(TOP VIEW)
D
Members of the Texas Instruments
Widebusā Family
Inputs Are TTL-Voltage Compatible
D
D
Flow-Through Architecture Optimizes
PCB Layout
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
D
D
D
D
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
3
CC
4
5
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
6
7
V
V
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
125°C
9
Packaged in Plastic 300-mil Shrink
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Small-Outline (DL) Packages Using 25-mil
Center-to-Center Pin Spacings and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Spacings
description
The ’ACT16640 are inverting 16-bit transceivers
designed for asynchronous communication
between data buses.
V
V
CC
CC
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
2OE
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the direction-control (1DIR and 2DIR)
inputs. The output-enable (1OE and 2OE) inputs
can be used to disable the device so that the
buses are effectively isolated.
2DIR
The 74ACT16640 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16640 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16640 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
(each section)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢆ ꢁꢇ ꢈ ꢉ ꢁꢂꢃ ꢄꢅ ꢆ ꢆ ꢁ ꢇ
ꢅꢆ ꢊꢋꢌ ꢄ ꢋ ꢍ ꢎ ꢄ ꢏ ꢂ ꢐꢎ ꢃꢑ ꢌ ꢒꢑ ꢏꢎ
ꢓꢌ ꢄ ꢔ ꢕ ꢊꢎꢄꢂꢄ ꢑ ꢖꢍꢄ ꢗ ꢍꢄꢎ
SCAS173A - JULY 1990 - REVISED APRIL 1996
†
logic symbol
48
1
G3
1OE
1DIR
3 EN1 [BA]
3 EN2 [AB]
25
24
G6
2OE
2DIR
6 EN4 [BA]
6 EN5 [AB]
47
2
1A1
1B1
1
1
1
2
46
44
43
41
40
38
37
36
3
5
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
6
8
9
11
12
13
4
1
1
5
35
33
32
30
29
27
26
14
16
17
19
20
22
23
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
48
25
24
1OE
2OE
1
1DIR
2DIR
47
2
36
13
2B1
1A1
1B1
2A1
To Seven Other Channels
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS173A - JULY 1990 - REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
Maximum package power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.2 W
A
Storage temperature range,T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16640
MIN NOM
74ACT16640
MIN NOM
UNIT
MAX
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
24
−24
24
mA
mA
ns/V
°C
OH
OL
∆t/∆v
0
10
0
10
T
−55
125
−40
85
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢆ ꢁꢇ ꢈ ꢉ ꢁꢂꢃ ꢄꢅ ꢆ ꢆ ꢁ ꢇ
ꢅꢆ ꢊꢋꢌ ꢄ ꢋ ꢍ ꢎ ꢄ ꢏ ꢂ ꢐꢎ ꢃꢑ ꢌ ꢒꢑ ꢏꢎ
ꢓꢌ ꢄ ꢔ ꢕ ꢊꢎꢄꢂꢄ ꢑ ꢖꢍꢄ ꢗ ꢍꢄꢎ
SCAS173A - JULY 1990 - REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54ACT16640
74ACT16640
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
= −50 µA
OH
5.4
5.4
5.4
3.94
4.94
3.8
3.8
V
V
OH
I
I
= −24 mA
= −75 mA
OH
4.8
4.8
†
3.85
3.85
OH
0.1
0.1
0.1
0.1
0.44
0.44
1.65
1
0.1
0.1
0.44
0.44
1.65
1
I
= 50 µA
OL
0.36
0.36
V
V
OL
I
I
= 24 mA
OL
†
= 75 mA
OL
I
I
I
Control inputs V = V
or GND
1
0.5
8
µA
µA
µA
I
I
CC
‡
A or B ports
V
= V
or GND
5
5
OZ
CC
O
CC
V = V
or GND,
I
O
= 0
80
80
I
CC
One input at 3.4 V,
Other inputs at V
§
∆I
CC
5.5 V
0.9
1
1
mA
or GND
CC
or GND
C
C
Control inputs V = V
CC
5 V
5 V
4.5
16
pF
pF
i
I
A or B ports
V
O
= V or GND
CC
io
†
‡
§
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
6
54ACT16640
74ACT16640
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
2.2
4.1
2.7
3.5
6.1
5.5
MAX
8.3
MIN
2.2
4.1
2.7
3.5
6.1
5.5
MAX
9.1
MIN
2.2
4.1
2.7
3.5
6.1
5.5
MAX
9.1
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
OE
B or A
A or B
A or B
7.6
9.3
10.5
9.8
10.5
9.8
6.9
8.9
ns
8.2
10.4
11.4
10.3
11.5
12.5
11
11.5
12.5
11
9.4
ns
OE
8.7
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
52
9
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per transceiver
C
pF
pd
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ꢞ ꢣ ꢝ ꢜ ꢯ ꢤ ꢨꢛ ꢥ ꢝ ꢣ ꢟꢦ ꢞꢣ ꢰ ꢣ ꢪ ꢟꢨ ꢢꢣ ꢤ ꢚꢫ ꢃ ꢛꢥ ꢧꢥ ꢠꢚ ꢣꢧ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢧ
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS173A - JULY 1990 - REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
500 Ω
Open
GND
t
/t
Open
PLH PHL
/t
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
3 V
0 V
LOAD CIRCUIT
1.5 V
1.5 V
t
PZL
3 V
0 V
t
PLZ
Output
[ V
CC
Input
1.5 V
1.5 V
Waveform 1
S1 at 2 × V
50% V
CC
20% V
CC
CC
V
OL
t
(see Note B)
PHL
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
80% V
CC
50% V
CC
50% V
Output
CC
V
50% V
CC
[ 0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
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