74ACT16646DLG4 [TI]
16-Bit Bus Transceivers And Registers With 3-State Outputs 56-SSOP -40 to 85;
| 型号： | 74ACT16646DLG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Bus Transceivers And Registers With 3-State Outputs 56-SSOP -40 to 85 光电二极管 逻辑集成电路 触发器 |
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54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
54ACT16646 . . . WD PACKAGE
74ACT16646 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
1DIR
1CLKAB
1SAB
GND
1OE
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLKBA
1SBA
GND
1B1
2
3
Flow-Through Architecture Optimizes
PCB Layout
4
1A1
5
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
1A2
1B2
6
V
V
7
CC
CC
EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
8
9
500-mA Typical Latch-Up Immunity at
125°C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16646 are 16-bit bus transceivers
consisting of D-type flip-flops and control circuitry
with 3-state outputs arranged for multiplexed
transmission of data directly from the data bus or
from the internal storage registers. The devices
can be used as two 8-bit transceivers or one 16-bit
transceiver. Data on the A or B bus is clocked into
the registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental bus-
management functions that can be performed
with the bus transceivers and registers.
V
V
CC
CC
2A7
2A8
GND
2B7
2B8
GND
2SBA
2CLKBA
2OE
2SAB
2CLKAB
2DIR
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select
controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE
high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74ACT16646 is packaged in TI’s shrink small-outline package, which provides twice the functionality of
standard small-outline packages in the same printed-circuit-board area.
The 54ACT16646 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16646 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
DIR CLKAB CLKBA SAB
SBA
L
DIR
H
CLKAB CLKBA SAB
SBA
X
OE
L
OE
L
L
X
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
SBA
H
OE
X
OE
L
X
H or L
X
X
H
X
X
X
X
↑
X
X
X
↑
X
L
H
H or L
X
X
X
H
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
FUNCTION TABLE
†
DATA I/O
INPUTS
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
B1–B8
↑
X
Input
Unspecified
Input
Store A, B unspecified
Store B, A unspecified
Store A and B data
X
X
↑
X
X
Unspecified
Input
X
↑
H or L
X
↑
H or L
X
X
X
Input
X
X
X
Input
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B Bus
Stored A data to bus
L
X
L
Output
Output
Input
Input
L
L
X
H or L
X
X
H
Input
L
H
H
X
L
X
Output
Output
L
H or L
X
H
X
Input
†
The data-output functions may be enabled or disabled by various signals at OE or DIR. Data-input functions are always enabled, i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
†
logic symbol
56
G3
1OE
1
1DIR
3 EN1 [BA]
3 EN2 [AB]
55
54
2
1CLKBA
1SBA
C4
G5
1CLKAB
1SAB
C6
3
G7
29
28
G10
2OE
2DIR
10 EN8 [BA]
10 EN9 [AB]
30
31
27
26
2CLKBA
2SBA
C11
G12
2CLKAB
2SAB
C13
G14
52
4D
2
1B1
≥1
5
5
1A1
1
5 1
≥1
6D
7
7
1
6
51
49
48
47
45
44
43
42
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
8
9
10
12
13
14
≥1
12 11D
12 1
15
2A1
8
13D 14
1 14
≥1
9
16
17
19
20
21
23
24
41
40
38
37
36
34
33
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
logic diagram (positive logic)
56
1OE
1
1DIR
1CLKBA
55
54
1SBA
2
1CLKAB
3
1SAB
C1
TG
1D
5
1A1
TG
C1
1D
TG
TG
52
B1
6
1A2
8
51
49
48
47
45
44
43
B2
B3
B4
B5
B6
B7
B8
1A3
9
1A4
10
Seven Channels Identical
to Channel One Above
1A5
12
1A6
13
1A7
14
1A8
29
2OE
28
2DIR
30
2CLKBA
31
2SBA
27
2CLKAB
26
2SAB
C1
1D
TG
15
2A1
TG
C1
1D
TG
42
B1
TG
41
40
38
37
36
34
33
16
17
19
20
21
23
24
B2
B3
B4
B5
B6
B7
B8
2A2
2A3
2A4
2A5
2A6
2A7
2A8
Seven Channels Identical
to Channel One Above
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum package power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
A
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16646
74ACT16646
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage (see Note 4)
High-level input voltage
Low-level input voltage
Input voltage
5.5
5.5
V
V
CC
IH
IL
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
24
–24
24
mA
mA
ns/V
°C
OH
OL
t/ v
0
10
0
10
T
–55
125
–40
85
A
NOTES: 3. Unused inputs must be held high or low to prevent them from floating.
4. All V and GND pins must be connected to the proper voltage power supply.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54ACT16646
74ACT16646
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
5.4
3.8
4.8
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
I
= –50
A
OH
5.4
5.4
3.94
4.94
3.7
= –24 mA
V
OH
V
OH
4.7
I
I
= –50 mA
= –75 mA
3.85
OH
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
I
I
= 50 A
OL
0.36
0.36
0.5
0.44
0.44
= 24 mA
V
OL
V
OL
0.5
I
I
= 50 mA
= 75 mA
1.65
OL
1.65
OL
I
I
I
Control inputs V = V
or GND
±0.1
±0.5
8
±1
±10
160
±1
A
A
A
I
I
CC
A or B ports
V
= V
or GND
5.5 V
5.5 V
±5
OZ
CC
O
CC
V = V
or GND,
I
O
= 0
80
I
CC
One input at 3.4 V,
Other inputs at GND or V
I
5.5 V
0.9
1
1
mA
CC
CC
C
C
Control inputs V = V
or GND
5 V
5 V
4
pF
pF
i
I
CC
= V or GND
CC
A or B ports
V
O
12
io
†
‡
§
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, (unless otherwise noted) (see Figure 2)
T
= 25°C
54ACT16646
74ACT16646
A
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
90
90
90
MHz
ns
clock
Pulse duration, CLKAB or CLKBA high or low
5.5
4
5.5
4
5.5
4
w
Data high
Data low
t
ns
ns
Setup time, A before CLKAB↑ or B before CLKBA↑
Hold time, A before CLKAB↑ or B before CLKBA↑
su
h
6
6
6
t
1.5
1.5
1.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, (unless otherwise noted) (see Figure 2)
T = 25°C
A
54ACT16646
74ACT16646
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
90
TYP
MAX
MIN
90
MAX
MIN
90
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PZH
PZL
PHZ
PLZL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
3.9
3.4
3.2
4.2
5.3
4.9
4.9
5.1
5.2
4.9
4.3
5.9
4.5
4.3
4.5
4.4
7.5
7.6
7.7
9
9.4
10.6
10.8
12.2
9.6
3.9
3.4
3.2
4.2
5.3
4.9
4.9
5.1
5.2
4.9
4.3
5.9
4.5
4.3
4.5
4.4
11.5
12.2
12.9
14.6
10.4
10.3
13.1
13.1
17.2
12.5
12.1
18.2
16.2
14.2
11.2
10.8
3.9
3.4
3.2
4.2
5.3
4.9
4.9
5.1
5.2
4.9
4.3
5.9
4.5
4.3
4.5
4.4
10.6
11.4
11.9
13.5
10.2
9.9
A or B
B or A
A or B
A or B
A or B
A or B
A or B
A or B
A or B
ns
ns
ns
ns
ns
ns
ns
OE
OE
7.7
7.3
8.9
9
9.2
11.1
11
12.2
12.3
15.6
11.7
11.1
16.7
15.2
13.1
10.8
10.4
CLKBA or CLKAB
10.3
8.2
7.8
11.2
9.5
9.2
7.9
7.5
13.8
10.6
9.9
SAB or SBA
(with A or B high)
SBA or SAB
(with A or B high)
14.9
13.6
11.8
10.2
9.8
DIR
DIR
†
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
58
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per transceiver
C
pF
pd
13
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16646, 74ACT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS127B – MARCH 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
/t
t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
h
t
3 V
0 V
su
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
CC
V
OL
OL
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
74ACT16646DL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DL
56
56
56
56
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74ACT16646DLG4
74ACT16646DLR
74ACT16646DLRG4
SSOP
SSOP
SSOP
DL
DL
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
74ACT16646DLR
SSOP
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DL 56
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 49.0
74ACT16646DLR
1000
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
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相关型号：
74ACT16648DL
ACT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56
ROCHESTER
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