74ACT16646SSC [FAIRCHILD]
16-Bit Transceiver/Register with 3-STATE Outputs; 16位收发器/寄存器与3态输出
| 型号： | 74ACT16646SSC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 16-Bit Transceiver/Register with 3-STATE Outputs |
| 文件： | 总6页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1999
Revised October 1999
74ACT16646
16-Bit Transceiver/Register with 3-STATE Outputs
General Description
Features
The ACT16646 contains sixteen non-inverting bidirectional
registered bus transceivers providing multiplexed transmis-
sion of data directly from the input bus or from the internal
storage registers. Each byte has separate control inputs
which can be shorted together for full 16-bit operation. The
DIR inputs determine the direction of data flow through the
device. The CPAB and CPBA inputs load data into the reg-
isters on the LOW-to-HIGH transition.
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data transfers
■ Separate control logic for each byte
■ 16-bit version of the ACT646
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Order Number
74ACT16646SSC
74ACT16646MTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD56
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500345
www.fairchildsemi.com
Function Table
Inputs
DIR1 CPAB1 CPBA1 SAB1 SBA1
Data I/O (Note 1)
Output Operation Mode
G1
A0–7
B0–7
H
H
H
L
L
L
L
L
L
L
L
X
X
X
H
H
H
H
L
H or L H or L
X
X
X
L
X
X
X
X
X
X
X
L
Isolation
X
Input
Input Clock An Data into A Register
Clock Bn Data Into B Register
X
X
X
X
X
X
X
An to Bn—Real Time (Transparent Mode)
Output Clock An Data to A Register
A Register to Bn (Stored Mode)
L
Input
H or L
H
H
X
X
X
X
Clock An Data into A Register and Output to Bn
Bn to An—Real Time (Transparent Mode)
Input Clock Bn Data into B Register
B Register to An (Stored Mode)
X
X
X
X
L
L
Output
L
H or L
H
H
L
Clock Bn into B Register and Output to An
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
= LOW-to-HIGH Transition.
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control pins.
Real Time Transfer
A-Bus to B-Bus
Storage from
Bus to Register
Real Time Transfer
B-Bus to A-Bus
Transfer from
Register to Bus
Logic Diagram
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Output Diode Current (IOK
)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
−40°C to +85°C
125 mV/ns
V
V
O = −0.5V
−20 mA
+20 mA
O = VCC + 0.5V
DC Output Voltage (VO)
−0.5V to VCC + 0.5V
±50 mA
V
CC @ 4.5V, 5.5V
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
per Output Pin
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
±50 mA
Storage Temperature
−65°C to +150°C
DC Electrical Characteristics
V
T
= +25°C
T = −40°C to+85°C
A
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
1.5
1.5
1.5
Guaranteed Limits
V
V
V
Minimum HIGH
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
= 0.1V
IH
OUT
V
V
V
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
2.0
0.8
0.8
4.4
5.4
or V − 0.1V
CC
V
= 0.1V
IL
OUT
or V − 0.1V
CC
4.49
5.49
OH
I
= −50 µA
OUT
V
= V or V
IN
OH
OH
IL
IH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
I
I
= −24 mA
= −24 mA (Note 3)
V
Maximum LOW
Output Voltage
0.001
0.001
OL
I
= 50 µA
OUT
0.1
0.1
V
= V or V
IN
OL
OL
IL
IH
4.5
5.5
0.36
0.36
0.44
0.44
V
I
I
= 24 mA
= 24 mA (Note 3)
= V , V
I
I
Maximum I/O
V
V
OZT
IN
IN
IL
IH
5.5
±0.5
±0.1
±5.0
µA
Leakage Current
Maximum Input
Leakage Current
= V , GND
CC
O
5.5
5.5
5.5
±1.0
1.5
µA
mA
µA
V = V , GND
I CC
I
I
Maximum I /Input
CC
0.6
V = V − 2.1V
CCT
CC
I
CC
Max Quiescent
8.0
80.0
V
= V or GND
CC
IN
Supply Current
I
I
Minimum Dynamic
Output Current (Note 4)
75
mA
mA
V
V
= 1.65V Max
= 3.85V Min
OLD
OHD
OLD
5.5
−75
OHD
Note 3: All outputs loaded; thresholds associated with output under test.
Note 4: Maximum test duration 2.0 ms; one output loaded at a time.
3
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AC Electrical Characteristics
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
Units
L
(Note 5)
Min
4.6
4.3
4.0
4.1
4.0
4.2
Typ
6.9
6.5
6.2
6.4
6.4
6.7
Max
9.4
8.9
8.5
8.6
8.9
9.5
Min
Max
t
t
t
t
t
t
Propagation Delay
3.6
3.3
2.9
3.2
3.1
3.2
10.1
9.7
PHL
5.0
5.0
5.0
ns
ns
ns
Clock to Bus
PLH
PHL
PLH
PHL
PLH
Propagation Delay
Bus to Bus
9.2
9.3
Propagation Delay
Select to Bus
(w/An or Bn HIGH or LOW)
Enable Time
9.6
10.4
t
t
t
t
t
t
t
t
5.3
4.6
3.0
3.4
5.1
4.6
2.9
3.4
7.8
6.9
5.5
5.7
8.2
7.5
5.8
6.1
10.5
9.4
3.8
3.3
2.3
2.6
4.3
3.7
2.0
2.5
11.4
10.2
8.6
PZL
PZH
PLZ
PHZ
PZL
PZH
PLZ
PHZ
5.0
5.0
5.0
5.0
ns
ns
ns
ns
G to An/Bn
Disable Time
G to An/Bn
8.1
8.3
8.6
Enable Time
11.8
10.8
9.2
12.7
11.7
9.8
DIR to An/Bn
Disable Time
DIR to An/Bn
9.2
9.7
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
V
T
= +25°C
= 50 pF
T = −40°C to +85°C
A
CC
A
C
C = 50 pF
L
Symbol
Parameter
(V)
Units
L
(Note 6)
Guaranteed Minimum
3.0
t
Setup Time, H or L
S
5.0
3.0
1.5
4.0
ns
ns
ns
Bus to Clock
Hold Time, H or L
Bus to Clock
Clock Pulse Width
H or L
t
t
H
W
5.0
5.0
1.5
4.0
Note 6: Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
C
Input Capacitance
4.5
95
pF
pF
V
V
= 5.0V
= 5.0V
IN
CC
CC
Power Dissipation Capacitance
PD
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4
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS56A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
相关型号：
74ACT16648DL
ACT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56
ROCHESTER
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