54ACT174FMQB [TI]
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, DFP-16;
| 型号： | 54ACT174FMQB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, DFP-16 CD 输出元件 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2003
54AC174/54ACT174
Hex D Flip-Flop with Master Reset
n ’ACT174 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— 54AC174: 5962-87626
— 54ACT174: 5962-87757
n 54AC174 now qualified to 300Krad RHA designation,
General Description
The ’AC/’ACT174 is a high-speed hex D flip-flop. The device
is used primarily as a 6-bit edge-triggered storage register.
The information on the D inputs is transferred to storage
during the LOW-to-HIGH clock transition. The device has a
Master Reset to simultaneously clear all flip-flops.
refer to the SMD for more information
Features
n ICC reduced by 50%
n Outputs source/sink 24 mA
Logic Symbols
Pin Names
D0–D5
CP
Description
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
MR
Q0–Q5
10027701
IEEE/IEC
10027702
™
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2003 National Semiconductor Corporation
DS100277
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Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
10027703
10027704
Functional Description
Truth Table
The ’AC/’ACT174 consists of six edge-triggered D flip-flops
with individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops. Each D
input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A
LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The ’AC/’ACT174
is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Inputs
Output
MR
L
CP
X
D
X
H
L
Q
L
N
H
H
L
N
H
H
L
X
Q
H = HIGH Voltage Level
L = LOW Voltage Level
N
= LOW-to-HIGH Transition
X = Immaterial
Logic Diagram
10027705
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACT
DC Input Diode Current (IIK
VI = −0.5V
)
Input Voltage (VI)
Output Voltage (VO)
−20 mA
+20 mA
0V to VCC
VI = VCC + 0.5V
Operating Temperature (TA)
54AC/ACT
DC Input Voltage (VI)
−0.5V to VCC +
−55˚C to +125˚C
125 mV/ns
0.5V
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
DC Output Diode Current (IOK
VO = −0.5V
)
−20 mA
+20 mA
VIN from 30% to 70% of VCC
VO = VCC + 0.5V
@
VCC 3.3V, 4.5V, 5.5V
DC Output Voltage (VO)
−0.5V to VCC
+
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
0.5V
DC Output Source
VIN from 0.8V to 2.0V
or Sink Current (IO)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65˚C to +150˚C
™
mend operation of FACT circuits outside databook specifications.
175˚C
DC Characteristics for ’AC Family Devices
54AC
Symbol
Parameter
VCC
(V)
TA
=
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.1
3.15
3.85
0.9
VOUT = 0.1V
V
V
V
or VCC − 0.1V
VIL
Maximum Low Level
Input Voltage
VOUT = 0.1V
1.35
1.65
2.9
or VCC − 0.1V
VOH
Minimum High Level
Output Voltage
IOUT = −50 µA
4.4
5.4
(Note 2)
VIN = VIL or VIH
IOH = −12 mA
IOH = −24 mA
IOH = −24 mA
IOUT = 50 µA
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
V
V
VOL
Maximum Low Level
Output Voltage
(Note 2)
VIN = VIL or VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
VI = VCC, GND
3.0
4.5
5.5
5.5
0.50
0.50
0.50
1.0
V
IIN
Maximum Input
Leakage Current
µA
3
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DC Characteristics for ’AC Family Devices (Continued)
54AC
Symbol
Parameter
VCC
(V)
TA
=
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
IOLD
IOHD
ICC
Minimum Dynamic
5.5
5.5
5.5
50
mA
mA
µA
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
Output Current (Note 3)
−50
80.0
Maximum Quiescent
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 4: I and I
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V
.
CC
IN
CC
@ @
for 54AC 25˚C is identical to 74AC 25˚C.
I
CC
DC Characteristics for ’ACT Family Devices
54ACT
Symbol
Parameter
VCC
(V)
TA
=
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
VIH
VIL
Minimum High Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
Maximum Low Level
Input Voltage
VOH
Minimum High Level
Output Voltage
(Note 5)
VIN = VIL or VIH
IOH = −24 mA
IOH = −24 mA
IOUT = 50 µA
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
VOL
Maximum Low Level
Output Voltage
0.1
(Note 5)
VIN = VIL or VIH
IOL = 24 mA
IOL = 24 mA
VI = VCC, GND
4.5
5.5
5.5
0.50
0.50
1.0
V
IIN
Maximum Input
Leakage Current
Maximum
µA
mA
ICCT
5.5
1.6
VI = VCC − 2.1V
I
CC/Input
IOLD
IOHD
ICC
Minimum Dynamic
5.5
5.5
5.5
50
mA
mA
µA
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC
Output Current (Note 6)
−50
80.0
Maximum Quiescent
Supply Current
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACT 25˚C is identical to 74ACT 25˚C.
Note 7: I
CC
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4
AC Electrical Characteristics
VCC
54AC
(V)
TA = −55˚C to +125˚C
CL = 50 pF
Fig.
No.
Symbol
Parameter
Units
(Note 8)
Min
65
Max
fmax
Maximum Clock
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
MHz
ns
Frequency
90
tPLH
tPHL
tPHL
Propagation Delay
CP to Qn
1.0
1.5
1.0
1.5
1.0
1.5
14.0
10.5
13.0
10.0
13.5
11.0
Propagation Delay
CP to Qn
ns
Propagation Delay
MR to Qn
ns
Note 8: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54AC
VCC
(V)
TA = −55˚C
to +125˚C
CL = 50 pF
Fig.
No.
Symbol
Parameter
Units
(Note 9)
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to CP
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
7.5
5.5
3.0
3.0
7.0
5.0
7.0
5.0
3.0
2.0
ns
ns
ns
ns
ns
th
tw
tw
Hold Time, HIGH or LOW
Dn to CP
MR Pulse Width, LOW
CP Pulse Width
trec
Recovery Time
MR to CP
Note 9: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics
54ACT
VCC
(V)
(Note 10)
TA = −55˚C to +125˚C
CL = 50 pF
Fig.
No.
Symbol
Parameter
Units
Min
Max
fmax
Maximum Clock
5.0
5.0
5.0
5.0
95
MHz
ns
Frequency
tPLH
tPHL
tPHL
Propagation Delay
CP to Qn
1.5
1.5
1.5
12.5
13.0
12.0
Propagation Delay
CP to Qn
ns
Propagation Delay
MR to Qn
ns
Note 10: Voltage Range 5.0 is 5.0V 0.5V
5
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AC Operating Requirements
54ACT
TA = −55˚C
to +125˚C
CL = 50 pF
Guaranteed
Minimum
3.0
VCC
(V)
Fig.
No.
Symbol
Parameter
Units
(Note 11)
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
ns
ns
th
Hold Time, HIGH or LOW
Dn to CP
2.0
tw
MR Pulse Width, LOW
CP Pulse Width, HIGH OR LOW
Recovery Time
5.0
5.0
5.0
5.0
5.0
1.0
ns
ns
ns
tw
trec
MR to CP
Note 11: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
Units
Conditions
CIN
Input Capacitance
Power Dissipation
Capacitance
pF
pF
VCC = OPEN
VCC = 5.0V
CPD
85.0
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
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systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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