54ACT175F [NSC]
Quad D Flip-Flop; QUAD D触发器
| 型号： | 54ACT175F |
| 厂家： | 
National Semiconductor |
| 描述： | Quad D Flip-Flop |
| 文件： | 总8页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54AC175 • 54ACT175
Quad D Flip-Flop
n Buffered positive edge-triggered clock
n Asynchronous common reset
n True and complement output
n Outputs source/sink 24 mA
n ’ACT175 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC175: 5962-89552
General Description
The ’AC/’ACT175 is a high-speed quad D flip-flop. The de-
vice is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D in-
puts is stored during the LOW-to-HIGH clock transition. Both
true and complemented outputs of each flip-flop are pro-
vided. A Master Reset input resets all flip-flops, independent
of the Clock or D inputs, when LOW.
— ’ACT175: 5962-89693
Features
n Edge-triggered D-type inputs
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100278-1
IEEE/IEC
DS100278-3
Pin Assignment for LCC
DS100278-2
DS100278-4
Pin Names
D0–D3
CP
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
MR
Q0–Q3
Q0–Q3
Complement Outputs
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100278
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Functional Description
Truth Table
The ’AC/’ACT175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW-to-HIGH clock
(CP) transition, causing individual Q and Q outputs to follow.
A LOW input on the Master Reset (MR) will force all Q out-
puts LOW and Q outputs HIGH independent of Clock or Data
inputs. The ’AC/’ACT175 is useful for general logic applica-
Inputs
Outputs
=
@
@
tn+1
tn, MR
H
Dn
L
Qn
L
Qn
H
H
H
L
=
=
=
H
L
HIGH Voltage Level
LOW Voltage Level
Bit Time before Clock Pulse
Bit Time after Clock Pulse
tions where
acceptable.
a common Master Reset and Clock are
t
t
n
=
n+1
Logic Diagram
DS100278-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACT
DC Input Diode Current (IIK
)
Input Voltage (VI)
=
VI −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
0V to VCC
=
VI VCC + 0.5V
Operating Temperature (TA)
54AC/ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
=
VO −0.5V
−20 mA
+20 mA
=
VO VCC + 0.5V
% to 70% of V
VIN from 30
CC
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
@
VCC 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
±
±
or Sink Current (IO
)
50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
VIN from 0.8V to 2.0V
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65˚C to +150˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
175˚C
DC Characteristics for ’AC Family Devices
54AC
=
Symbol
Parameter
VCC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
2.1
3.15
3.85
0.9
VOUT 0.1V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
4.4
5.4
(Note 2)
=
VIN VIL or VIH
=
IOH −12 mA
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
=
IOH −24 mA
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
(Note 2)
=
VIN VIL or VIH
=
IOL 12 mA
3.0
4.5
5.5
5.5
0.50
0.50
0.50
=
IOL 24 mA
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
(Note 3)
1.0
µA
VI VCC, GND
=
VOLD 1.65V Max
IOLD
IOHD
Minimum Dynamic
Output Current
5.5
5.5
50
mA
mA
=
VOHD 3.85V Min
−50
3
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DC Characteristics for ’AC Family Devices (Continued)
54AC
=
Symbol
Parameter
VCC
(V)
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
ICC
Maximum Quiescent
Supply Current
5.5
160.0
µA
VIN VCC
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 4:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
@
@
I
for 54AC 25˚C is identical to 74AC 25˚C.
CC
DC Characteristics for ’ACT Family Devices
54ACT
=
Symbol
Parameter
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 5)
=
VIN VIL or VIH
=
IOH −24 mA
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 5)
=
VIN VIL or VIH
=
IOL 24 mA
4.5
5.5
5.5
0.50
0.50
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum
1.0
µA
mA
VI VCC, GND
=
VI VCC − 2.1V
ICCT
5.5
1.6
I
CC/Input
(Note 6)
=
VOLD 1.65V Max
IOLD
IOHD
ICC
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
5.5
50
mA
mA
µA
=
VOHD 3.85V Min
−50
=
160.0
VIN VCC
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
I for 54ACT 25˚C is identical to 74ACT 25˚C.
CC
Note 7:
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4
AC Electrical Characteristics
54AC
TA −55˚C to +125˚C
=
VCC
(V)
Fig.
No.
Symbol
Parameter
Units
=
CL 50 pF
(Note 8)
3.3
Min
95
Max
fmax
Maximum Clock
MHz
ns
Frequency
5.0
95
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CP to Qn or Qn
Propagation Delay
CP to Qn or Qn
Propagation Delay
MR to Qn
3.3
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
14.5
10.5
15.0
11.5
15.0
11.0
13.5
10.5
5.0
3.3
ns
5.0
3.3
ns
5.0
Propagation Delay
MR to Qn
3.3
ns
5.0
±
Note 8: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54AC
=
VCC
(V)
TA −55˚C to +125˚C
Fig.
No.
Symbol
Parameter
Units
=
CL 50 pF
(Note 9)
3.3
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
3.5
2.0
2.5
6.0
5.0
5.5
5.0
1.5
1.5
ns
ns
ns
ns
ns
5.0
th
tw
tw
Hold Time, HIGH or LOW
Dn to CP
3.3
5.0
CP Pulse Width
3.3
HIGH or LOW
5.0
MR Pulse Width, LOW
3.3
5.0
trec
Recovery Time
MR to CP
3.3
5.0
±
Note 9: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
5
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AC Electrical Characteristics
54ACT
TA −55˚C to +125˚C
=
VCC
(V)
Fig.
No.
Symbol
Parameter
Units
=
CL 50 pF
(Note 10)
5.0
Min
Max
fmax
Maximum Clock
95
MHz
ns
Frequency
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CP to Qn or Qn
Propagation Delay
CP to Qn or Qn
Propagation Delay
MR to Qn
5.0
5.0
5.0
5.0
1.5
1.5
1.5
1.5
11.5
12.5
11.5
11.0
ns
ns
Propagation Delay
MR to Qn
ns
±
Note 10: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54ACT
=
VCC
(V)
TA −55˚C to +125˚C
Fig.
No.
Symbol
Parameter
Units
=
CL 50 pF
(Note 11)
5.0
Guaranteed Minimum
ts (H)
Setup Time
3.5
3.5
1.5
ns
ns
ns
ts (L)
th
Dn to CP
Hold Time, HIGH or LOW
Dn to CP
5.0
5.0
tw
CP Pulse Width
5.0
HIGH or LOW
tw
MR Pulse Width, LOW
Recovery Time, MR to CP
5.0
5.0
5.0
1.5
ns
ns
trec
±
Note 11: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
Units
pF
Conditions
=
VCC OPEN
CIN
=
VCC 5.0V
CPD
45.0
pF
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Tel: 1-800-272-9959
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