U3500BM-BFLG3 [TEMIC]

Cordless Telephone Signal Processor; 无绳电话信号处理器
U3500BM-BFLG3
型号: U3500BM-BFLG3
厂家: TEMIC SEMICONDUCTORS    TEMIC SEMICONDUCTORS
描述:

Cordless Telephone Signal Processor
无绳电话信号处理器

电信集成电路 光电二极管 无绳技术 异步传输模式 ATM 电话
文件: 总17页 (文件大小:222K)
中文:  中文翻译
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U3500BM  
Cordless Telephone Signal Processor  
Description  
The programmable cordless phone signal processor such as IF converter, FM demodulator. RSSI and low  
includes all necessary low frequency parts such as noise amplifier.  
microphone- and earphone amplifier, compander, pre- Several gains and mutes in transmit and receive direction  
emphasis, deemphasis, scrambler, data management, are controlled by serial bus while compander, pre- and  
power-supply management, as well as RF receiving parts deemphasis and scrambler can be bypassed.  
Features  
RF Receiver Part  
Compander  
Low-noise amplifier  
Pre- and deemphasis  
Scrambler  
IF converter  
FM demodulator  
Data management  
Power-supply management  
Serial bus  
RSSI  
Low Frequency Part  
Symmetrical input of microphone amplifier  
Symmetrical output of earpiece amplifier  
Application: CT0  
Block Diagram  
MIXO IFIN1 IFIN2  
DACO  
IFAMP  
RGAIN  
ADJ  
MIXIN  
MIXGND  
Deem  
RXO  
Demodulator  
LPF  
LPF  
LOG  
Scrambler  
frequency  
ETC  
Expander  
EXIN  
RECO2  
Oscillator  
11.15 MHz  
LOIN  
Divider  
D/A  
LPF  
REC  
RECO1  
LNA  
LNAIN  
MIC1  
MIC2  
MICO  
RGND  
LNAO  
MIC  
VBATT  
RXDAT  
TXDAT  
Battery low  
detector  
Scrambler  
frequency  
C
D
Serial  
TGAIN  
ADJ.2  
TGAIN  
ADJ.1  
COIN  
LPF  
LPF  
Limiter  
Preem  
GND  
Compressor  
CTC  
Bus  
14678  
VCC TXO  
Figure 1. Block diagram  
Rev. A3, 20-May-98  
1 (17)  
Preliminary Information  
U3500BM  
Pin Description  
Pin Symbol  
Function  
Transmit section analog output  
Compressor time constant  
control analog output  
Compressor analog input  
1
28  
TXO  
TXDAT  
1
2
TXO  
CTC  
CTC  
2
3
4
5
6
7
8
9
27 RXDAT  
3
4
5
COIN  
26  
D
MICO Microphone amplifier output  
MIC2  
COIN  
MICO  
Non-inverting input of  
microphone amplifier  
Inverting input of microphone  
amplifier  
LF analog/ digital ground  
Intermediate receive analog  
output  
25  
C
6
MIC1  
24  
DACO  
MIC2  
MIC1  
7
8
GND  
RXO  
23  
22  
VCC  
9
RECO2 Symmetrical output of receive  
amplifier  
GND  
RXO  
LOIN  
10  
RECO1 Symmetrical output of receive  
amplifier  
21  
20  
19  
VBATT  
LNAO  
11  
12  
EMN  
ETC  
Expander analog input  
Expander time constant control  
analog output  
Symmetrical IF amplifier input  
Symmetrical IF amplifier input  
RECO2  
RECO1  
EXIN  
ETC  
13  
14  
15  
16  
IFIN2  
IFIN1  
MIXO Mixer output  
MIXIN Mixer input  
10  
11  
12  
RGND  
18  
17  
16  
LNAIN  
MIXGND  
MIXIN  
17 MIXGND IF amplifier and mixer ground  
18  
19  
20  
LNAIN Low-noise amplifier input  
RGND Low-noise amplifier ground  
LNAO Low-noise amplifier output/  
External LO input  
13  
14  
IFIN2  
IFIN1  
15 MIXO  
21  
22  
VBATT Battery supply  
LOIN  
96 11791  
Local oscillator input  
(11.15 MHz)  
Figure 2. Pinning  
23  
VCC  
Supply-voltage output for  
peripherals and internal supply  
of digital part  
24  
25  
26  
27  
28  
DACO D/A comparator output  
C
D
Clock input of serial bus  
Data input of serial bus  
RXDAT Receive data digital output  
TXDAT Transmit data input  
Order Information  
Extended Type Number  
U3500BM-BFL  
U3500BM-BFLG3  
Package  
SO28  
SO28  
Remarks  
Taped and reeled  
2 (17)  
Rev. A3, 20-May-98  
Preliminary Information  
U3500BM  
Absolute Maximum Ratings  
Parameters  
Symbol  
, V  
Value  
5.5  
+125  
Unit  
V
°C  
°C  
°C  
W
Supply voltage  
V
Batt  
CC  
Junction temperature  
Ambient temperature  
Storage temperature  
T
j
T
amb  
–25 to +75  
–50 to +125  
1
T
stg  
Power dissipation  
T
= 60°C  
P
tot  
amb  
Thermal Resistance  
Parameters  
Symbol  
R
thJA  
Value  
120  
Unit  
K/W  
Junction ambient  
SO28  
Electrical Characteristics  
Test conditions (unless otherwise specified): V  
= V = 3.6 V, T  
= +25°C  
Batt  
CC  
amb  
Parameters  
Test Conditions / Pins  
Symbol Min.  
Typ.  
Max.  
Unit Fig.  
Current consumption  
ERX2  
0
ELNA  
0
ERXHF  
0
ERX1  
0
ERXO  
0
EEA  
0
EDEE  
ETX  
0
EPREE  
0
0
Operating voltage range  
Inactive mode  
3.1  
30  
3.6  
60  
5.2  
80  
V
A
V
Batt  
= 2.9 V  
Standby mode  
RX waiting for RSSI  
RX waiting for data  
Operating current, RX and  
TX completely active  
100  
2.5  
1.9  
6.5  
120  
3.4  
2.45  
9.5  
A
ELNA = ERXHF = 1  
ELNA = ERXHF = ERX1 = 1  
ERX2 = ELNA = ERXHF =  
ERX1 = ERXO = EEA=  
EDEE = GDEM = ETX = 1  
1.7  
1.45  
4.5  
mA  
mA  
mA  
Low noise amplifier (LNA) f = 41.4 MHz, input level = –50 dBm  
Supply current  
Input impedance  
Output impedance  
Gain  
Noise figure  
1-dB input compression  
point  
Third-order input intercept f = 41.4 MHz  
0.8  
160  
40  
1
200  
80  
23  
4
1.2  
240  
120  
26  
mA  
3
3
3
3
3
3
f = 50 MHz  
Bandwidth = 1 MHz  
20  
dB  
dB  
dBm  
5
–27  
–15  
–24  
–12  
dBm  
MHz  
3
3
point  
f = 41.4125 MHz  
Input level = –60 dBm  
Frequency range FRF  
20  
50  
Rev. A3, 20-May-98  
3 (17)  
Preliminary Information  
U3500BM  
Parameters  
Test Conditions / Pins  
Symbol Min.  
Typ.  
Max.  
Unit Fig.  
Receiver  
IF mixer, f = 10.7 MHz  
Input resistance  
2000  
2.5  
1200  
13  
–17  
–9  
3000  
3
1500  
15  
4000  
3.5  
1800  
17  
4
Input capacitance  
Output impedance  
Gain GVMIX  
Input compression point  
Third-order input intercept  
point  
pF  
4
4
4
4
Input level 7 mV  
G
MIX  
dB  
dBm  
dBm  
rms  
4
Carrier breakthrough from  
internal LO (11.15 MHz) to  
IF output  
Carrier breakthrough from  
internal LO (11.15 MHz) to  
RF input  
300  
10  
V
rms  
4
V
rms  
4
5
IF amplifier: RSSI  
Input resistance  
1.6  
2
2.5  
k
RSSI-sensitivity  
VIF = 0 V  
rms  
starting from 0 increase RSSI-  
level until mean of sampled  
signal at DACO is 0.2  
RSSI-level = CON0  
VIF = 25.4 V  
f = 450 kHz  
rms,  
5
increase RSSI level again  
until mean of sampled signal  
at DACO is 0.2.  
1
RSSI-level = CON1  
RSSI-sensitivity =  
CON1–CON0  
RSSI-input voltage  
dynamic range  
RSSI-level number of  
programmable steps  
RSSI-level step size in the  
logarithmic region  
60  
65  
dB  
dB  
5
5
5
127  
0.46  
*)  
0.35  
0.6  
*) RSSI Level Programming (Typical Values)  
Input Voltage VIF ( V  
)
RSSI Level (Decimal)  
rms  
0
5
8
25.4  
42.4  
424  
14  
54  
97  
111  
4240  
42400  
4 (17)  
Rev. A3, 20-May-98  
Preliminary Information  
U3500BM  
Parameters  
Test Conditions / Pins  
Symbol Min.  
Typ.  
Max.  
Unit Fig.  
RF demodulator  
fIF = 450 kHz, fMOD = 1 kHz, V = 500 V  
IF  
rms  
BSCR  
1
EDEE  
0
GRX0  
1
GRX1  
1
GRX2  
1
GRX3  
ERX1  
ERXO  
1
ERX2  
1
0
1
Recovered audio  
GDEM = 0, fFM = 2.5 kHz  
GDEM = 1, fFM = 5.0 kHz  
0.4  
0.4  
0.8  
0.8  
1.6  
1.6  
Vpp  
6
Vpp  
Recovered audio output  
voltage drop  
V
Batt  
= 3.1 to 5.2 V  
–1  
+1  
dB  
6
AM rejection ratio  
RX audio  
Change of RX0 signal  
deemphasis bypass  
30% AM  
30  
35  
0
dB  
dB  
6
6
EDEE = 0  
–0.5  
0.5  
Gain adjust range  
Gain adjust step  
12  
0.8  
15  
1
17  
1.2  
dB  
dB  
6
6
Output signal vs. frequency 100 Hz  
–7.5  
–2.0  
–1.3  
–0.8  
–6.5  
–1.0  
–0.3  
0.2  
–5.5  
0
0.7  
1.2  
–60  
relative to 1 kHz (0 dB)  
deemphasis bypassed  
300 Hz  
1800 Hz  
3200 Hz  
4100 Hz  
dB  
dB  
6
6
Output signal vs. frequency 100 Hz  
–0.7  
3.7  
–5.7  
–10  
0.3  
4.7  
–4.7  
–9.0  
1.3  
5.7  
–3.7  
–8.0  
–66  
relative to 1 kHz (0 dB)  
deemphasis enable  
EDEE = 1  
300 Hz  
1800 Hz  
3200 Hz  
4100 Hz  
Total harmonic distortion  
Audio mute  
FM = 250 Hz  
FM = 2.50 kHz  
FM = 2.5 kHz, ERXO = 0  
ERX1 = 0, ERX2 = 0  
3.5  
3.5  
%
%
dB  
6
6
65  
Output impedance  
100  
Expander  
EEA  
1
GEA0  
0
GEA1  
0
GEA2  
0
GEA3  
1
GEA4  
1
Gain reference level  
Change of gain when  
expander is bypassed  
VEXIN = –10 dBV  
BCOMP = 1  
G
OREC  
11  
–0.5  
13  
15  
0.5  
dB  
dB  
7
7
rms  
Gain tracking  
VEXIN = –20 dBV  
VEXIN = –30 dBV  
VEXIN = –35 dBV  
VEXIN = –40 dBV  
–21  
–41  
–53  
–19  
–39  
–47  
rms  
rms  
rms  
rms  
dB  
7
–50  
–60  
Input impedance  
Gain change vs. supply  
voltage  
9.5  
–0.5  
14.5  
0.5  
k
dB  
7
7
V
Batt  
= 3.1 to 5.2 V  
Attack time  
VEXIN = step  
–20 dBV  
measure time after step, when  
output voltage has 0.75 times  
the final value  
t
t
16  
16  
ms  
f
–14 dBV  
,
rms  
rms  
7
7
Release time  
VEXIN = step  
ms  
f
14 dBV  
–20 dBV  
,
rms  
rms  
measure time after step, when  
output voltage has 1.5 times of  
the final value  
Rev. A3, 20-May-98  
5 (17)  
Preliminary Information  
U3500BM  
Parameters  
Test Conditions / Pins  
Symbol Min.  
Typ.  
5
Max.  
6
Unit Fig.  
Earpiece amplifier BCOMP = 1, EEA = 1, VEXIN = 100 mV  
Medium gain  
rms  
GEA0 GEA1 GEA2 GEA3  
4
dB  
7
0
0
0
0
GEA4 = 1  
Minimum gain  
GEA0 GEA1 GEA2 GEA3  
–12  
–11  
–10  
0.2  
dB  
7
0
0
0
0
GEA4 = 0  
Gain change versus V  
Gain adjust range  
Gain adjust step  
Output impedance  
Distortion  
V
Batt  
= 3.1 to 5.2 V  
–0.2  
0.8  
dB  
dB  
dB  
7
7
7
7
7
7
S
31  
1
10  
1.2  
30  
2
d
t
%
mV  
Vpp  
Output offset voltage  
Output voltage swing  
VEXIN = 0 mV  
–200  
4.8  
200  
rms  
Increase VEXIN until distor-  
tion (RECO1/ RECO2) is 5%  
GEA0 GEA1 GEA2 GEA3  
5.0  
20  
7
Maximum gain  
19  
21  
dB  
1
1
1
1
7
GEA4 = 1  
Low Frequency Transmitter  
GMIC  
1
EPREE  
1
BSCR  
1
GlTX  
1000  
G2TX  
1000  
BCOMP  
1
ETX  
1
Microphone Amplifier  
VMIC = 10 mV , fIN = 1 kHz  
rms  
Gain  
High gain: GMIC = 1  
Low gain: GMIC = 0  
31  
23  
–0.2  
41  
32  
24  
0
75  
10  
33  
25  
0.2  
103  
35  
1
dB  
dB  
dB  
k
8
Gain change versus V  
Differential input impedance  
Output impedance  
V
Batt  
= 3.1 to 5.2 V  
8
8
8
8
S
Distortion  
VMIC = 10 mV  
d
t
%
rms  
Output noise  
VMIC = 0 V high gain  
50  
V
rmsp  
rms  
8
(psophmetrically weighted)  
TX Audio VCOIN = –20 dBV  
Gain  
(inputs closed across 200  
)
rms  
GTX (COIN, TXO)  
EPREE = 0  
2.5  
–0.5  
–1  
12  
0.8  
5.5  
0
0
15  
1
15  
1
–0.3  
–0.3  
0.2  
0.9  
8.5  
0.5  
+1  
18  
dB  
9
9
9
9
9
9
9
Change of gain TXO  
Gain between 3.2 and 5.2 V  
TX gain adjust range adj. 1  
TX gain adjust step adj. 1  
LIM gain adjust range adj. 2  
LIM gain adjust range adj. 2  
TX gain vs. frequency  
(preemphasis bypassed)  
relative to 1 kHz reference  
level 0 dB  
dB  
dB  
dB  
dB  
dB  
dB  
1.2  
0.8  
1.2  
0.7  
0.7  
1.2  
0.1  
100 Hz  
300 Hz  
1800 Hz  
3200 Hz  
4100 Hz  
–1.3  
–1.3  
–0.8  
–1.9  
dB  
9
–25.9 –23.9 –21.9  
Gain vs. frequency with  
preemphasis relative to 1 kHz 300 Hz  
reference level 0 dB  
100 Hz  
–0.8  
–6.8  
3.3  
6.0  
16.6  
–7.0  
–5.8  
4.3  
–6.0  
–4.8  
5.3  
1800 Hz  
3200 Hz  
4100 Hz  
dB  
dB  
9
9
7.0  
8.0  
–14.6 –12.6  
Total band ripple  
V
= 3.1 to 5.2 V  
2
Batt  
VCOIN = –20 dBV  
6 (17)  
Rev. A3, 20-May-98  
Preliminary Information  
U3500BM  
Parameters  
Test Conditions / Pins  
Symbol Min.  
Typ.  
10  
Max.  
Unit Fig.  
Limiter  
Output voltage  
Increase VCOIN until d = 5%  
at TX0 then measure VTX0  
ETX = 0, VCOIN = –l0 dBV  
attenuation at TX0 output  
1.05  
56  
7
2.0  
Vpp  
9
Mute  
dB  
9
Output impedance TXO  
14  
k
9
Compressor  
BSCR EPREE G2TX0 G2TX1 G2TX2  
G2TX3  
1
EIX  
1
GlTX0  
G1TX1 G1TX2 G1TX3  
1
0
0
1
0
0
0
1
0
Input impedance  
Gain reference level G0TX VCOIN = –10 dBV  
Gain change when  
compressor is bypassed  
BCOMP = 1  
9
1
0.5  
14  
5.5  
22  
10  
0.5  
k
dB  
dB  
9
9
G
0TX  
rms  
VCOIN = –10 dBV  
BCOMP = 1  
rms  
9
Gain tracking  
VCOIN = –30 dBV  
VCOIN = –50 dBV  
VCOIN = –60 dBV  
VCOIN = –70 dBV  
VCOIN= step  
–11  
–21  
–22  
–9  
–19  
–28  
rms  
rms  
rms  
rms  
dB  
ms  
9
–30  
3.5  
Attack time  
t
t
f
–30 dBV  
–18 dBV  
rms  
rms  
measure time after step when  
output voltage has 1.5 times  
the final value  
9
9
Release time  
VCOIN= step  
14.4  
ms  
f
–18 dBV  
–30 dBV  
rms  
rms  
measure time after step when  
output voltage has 0.75 times  
the final value  
Scrambler  
EPREE BSCR  
BCOMP  
0
0
1
Conversion gain versus  
frequency FIN (1 kHz)  
reference level 0 dB  
FIN=1kHz, FOUT=3.1kHz  
FIN=0.1kHz, FOUT=4.0kHz  
FIN=0.3kHz, FOUT=3.8kHz  
FIN=0.7kHz, FOUT=3.4kHz  
FIN=1.8kHz, FOUT=2.3kHz  
FIN=2.6kHz, FOUT=1.5kHz  
FIN=3.2kHz, FOUT=0.9kHz  
FIN=3.4kHz, FOUT=0.7kHz  
–1.0  
–4.4  
–2.1  
–0.8  
–1.1  
–1.1  
–2.5  
–5  
0
1.0  
–3.4  
–1.1  
0.2  
–0.1  
–0.1  
–0.5  
–4  
–2.4  
–0.1  
1.2  
0.9  
0.9  
–0.5  
–3  
dB  
11  
Carrier break through  
10  
20  
mV  
rms  
Descrambler  
EDEE  
0
BSCR  
0
BCOMP  
1
Conversion gain vs.  
frequency  
FIN=4kHz, FOUT=0.1kHz  
–3.6  
–1.3  
–0.4  
–1.5  
–0.4  
–1.7  
–1.9  
–2.6  
–0.3  
0.6  
0.5  
0.6  
–0.3  
–0.9  
0.1  
–1.6  
0.7  
1.6  
0.5  
1.6  
0.7  
0.1  
0.5  
FIN=3.8kHz, FOUT=0.3kHz  
FIN=3.4kHz, FOUT=0.7kHz  
FIN=2.3kHz, FOUT=1.8kHz  
FIN=l.5kHz, FOUT=2.6kHz  
FIN=0.9kHz, FOUT=3.2kHz  
FIN=0.7kHz, FOUT=3.4kHz  
Measure FOUT = 4.099 kHz  
11  
dB  
Carrier break through  
Rev. A3, 20-May-98  
mV  
rms  
7 (17)  
Preliminary Information  
U3500BM  
Parameters  
Data management  
Receive data management  
Test Conditions / Pins  
Symbol  
Min.  
0.4  
Typ.  
0.5  
Max.  
0.6  
Unit Fig.  
GDEM  
1
ERX1 ERXHF  
1
1
Duty cycle RXDAT  
V = 100 V  
IF rms  
f
f
= 450 kHz  
IF  
10  
= 1 kHz  
= 5 kHz  
MIF  
f
IF  
Transmit data management  
Input impedance TXDAT  
Final value of step re-  
sponse  
ETX1  
1
200  
311  
k
mV  
10  
10  
ETDM = 1, BSCR = 1  
= step  
1.5 V 1.75 V  
V
TXDAT  
Measure step at TXO  
Logical Part  
Inputs: C, D  
Low voltage input  
High voltage input  
Input leakage current  
0.2  
0.1  
V
CC  
0.8  
V
CC  
(0 < VI < V )  
CC  
–1  
+5  
A
A
Input LOIN  
Input leakage current  
(0 < VI < V  
–5  
5
)
CC  
Outputs: DACO, RXDAT  
Output low  
lol = 10 A  
V
CC  
Output high  
loh = –10 A  
0.9 V  
CC  
Serial bus  
Data set-up time  
Data hold time  
Clock low time  
Clock high time  
Hold time before transfer  
condition  
tsud  
thd  
tcl  
tch  
teon  
0.1  
0
2
2
0.1  
s
s
s
s
s
14  
Data low pulse on transfer teh  
condition  
0.2  
0.2  
s
s
Data high pulse on  
transfer condition  
teof  
8 (17)  
Rev. A3, 20-May-98  
Preliminary Information  
U3500BM  
Parameters  
Battery Management  
Max bat low  
Test Conditions / Pins  
Symbol  
Min.  
Typ.  
Max.  
Unit Fig.  
DA0 to 6 = 1, RBAT = 1  
DA0 to 6 = 27 BIN,  
RBAT = 1  
3.7  
3.05  
3.95  
3.2  
4.1  
3.35  
V
V
Min bat low over switch  
Max bat high  
Min bat high  
Adjust step  
DA0 to 6 = 1, RBAT = 0  
DA0 to 6 = 0, RBAT = 0  
4.75  
3.83  
3.5  
852.5  
100  
5.05  
4.1  
7.5  
952.5 1052.5  
200  
5.25  
4.27  
11.5  
V
V
mV  
mV  
mV  
Max – Min  
MINBL – SWOFF  
Battery Switch  
Off threshold  
On threshold  
300  
DA0 to 6 = 1, RBAT = 1  
DA0 to 6 = 27 BIN,  
RBAT = 1  
2.9  
3.1  
3.0  
3.2  
3.1  
3.35  
V
V
Hysteresis  
Switch ron  
220  
250  
35  
280  
50  
mV  
DA0 to 6 = 0, RBAT = 0  
Max bat low  
Min bat low  
Max bat high  
Min bat high  
Adjust step  
:
MAXL (battery voltage when all DAC bits are high, low range)  
MINBL (battery voltage when DAC bits are 001 1011, low range)  
MAXBH (battery voltage when all DAC bits are high, high range)  
MINBH (battery voltage when all DAC bits are low, high range)  
Adjust step  
:
:
:
:
:
:
:
:
:
:
Max – Min  
MAXBH – MINBH  
MINBL – SWOFF  
Off threshold  
On threshold  
Hysteresis  
MINBL – SWOFF  
SWOFF (off threshold of the battery switch)  
SWON (on threshold of the battery switch)  
SWON– SWOFF  
Switch ron  
Switch Ron (resistance of the switch transistor, when switch is “ON”)  
LNAIN  
1 nF  
LNAO  
18  
20  
LNA  
100 pF  
MIXIN 16  
15 MIXO  
200  
3 kΩ  
10 nF  
50 Ω  
VFRF  
1.5 kΩ  
VFRF  
11.15 MHz  
RF generator  
100 nF  
VBATT  
RF generator  
11779  
11780  
Figure 3.  
Figure 4.  
Rev. A3, 20-May-98  
9 (17)  
Preliminary Information  
U3500BM  
20 kΩ  
100 nF  
26  
25  
D
C
MICO  
MIC2  
MIC1  
4
5
6
Setup  
IFIN2 13  
26  
25  
D
C
RSSI–level  
programming  
IFIN1  
14  
Setup  
100 nF  
24 DACO  
RSSI–level  
information  
VMIC  
100 Ω  
100 Ω  
V
IF  
100 nF  
11781  
11784  
Figure 5.  
Figure 8.  
2
3
26  
D
C
CTC  
IFIN2  
13  
14  
470 nF  
100 nF  
Setup  
8
RXO  
25  
1
IFIN1  
100 nF  
470 nF  
COIN  
TXO  
VIF  
100 nF  
2.5 kΩ  
14696  
VCOIN  
100 kΩ  
Figure 6.  
11785  
Figure 9.  
RECO2  
9
26  
25  
D
C
28 TXDAT  
27 RXDAT  
TXO  
1
Setup  
1 kΩ  
VTXDAT  
1.5 V  
RECO1 10  
100 kΩ  
EXIN  
ETC  
11  
12  
100 nF  
26  
25  
D
C
IFIN2 13  
IFIN1 14  
100 nF  
Setup  
100 nF  
VEXIN  
470 nF  
VIF  
11783  
14679  
Figure 7.  
Figure 10.  
10 (17)  
Rev. A3, 20-May-98  
Preliminary Information  
U3500BM  
DATA  
F–3 dB=3.35 kHz  
F–3 dB=3.95 kHz  
Output buffer  
Gain stage  
Signal: 4.1 kHz/DC/OFF  
Signal: 1 kHz  
State : SCRON/SCROFF/DATA  
Gain : –4 dB/0 dB/OFF  
State : SCRON/SCROFF  
Gain : 5.9 dB/1.9 dB  
F–3 dB=90 Hz  
F–3 dB=3.95 kHz  
F–3 dB=3.35 kHz  
RGAIN  
ADJ  
Demo–  
dulator  
Deemphasis  
Signal: 4.1 kHz/DC/OFF  
Signal: 1 kHz  
State : DESCRON/DESCROFF/DATA  
Gain : –4 dB/0 dB/OFF  
State : DESCRON/DESCROFF  
Gain : –0.5 dB/–4.5 dB  
F–3 dB=1 kHz  
Comparator  
DATA  
11786  
Figure 11.  
Serial Bus Interface  
The circuit is remoted by an external microcontroller  
through the serial bus (programming can be started 10 s  
after power supply settled).  
The data is an 12-bit word:  
A3 – A0: address of the destination register (0 to 15)  
D7 – D0: contents of register  
Data  
D
Micro-  
processor  
Clock  
C
The data line must be stable when the clock is high and  
data must be serially shifted.  
96 11787  
After 12 clock periods, the transfer to the destination reg-  
ister is (internally) generated by a low-to-high transition  
of the data line when the clock is high.  
Figure 12.  
Rev. A3, 20-May-98  
11 (17)  
Preliminary Information  
U3500BM  
Data  
D0  
D1  
D2  
A1  
A2  
A3  
(D)  
Clock  
(C)  
Ist word  
2nd word  
13317  
Word transmission  
Figure 13.  
Transfer condition  
Data  
8
4
Clock  
0
Address  
decoder  
128 latches  
Commands  
15  
96 11789  
Figure 14.  
Data  
(D)  
A1  
A2  
A3  
D0  
(C)  
Clock  
t
t
hd  
t
ch  
t
cl  
t
t
eh  
t
eoff  
sud  
eon  
13318  
Figure 15.  
12 (17)  
Rev. A3, 20-May-98  
Preliminary Information  
U3500BM  
Content of Internal Registers  
The registers have the following structure:  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
RO: Reference for D/A converter  
MUXDA  
DA6  
DA5  
DA4  
DA3  
DA2  
DA1  
DA0  
MUXDA:  
DA(6:0):  
D/A multiplexing  
Reference voltage D/A  
R1: Gain adjustment RECLF  
GEA3 GEA2  
GEA1  
GEA0  
GRX3  
G1TX3  
ERX1  
GRX2  
GRX1  
G1TX1  
ELNA  
GRX0  
G1TX0  
ERX2  
GEA(3:0): Gain earpiece amplifier (see also R5)  
GRX(3:0): Gain adjustment RX  
R2: Gain adjustment TRANLF  
G2TX3  
G2TX2  
G2TX1  
G2TXO  
G1TX2  
ERXHF  
G2TX(3:0): Gain adjustment TX after limiter  
G1TX(3:0): Gain adjustment TX  
R3: Enable functions receive  
GDEM  
EDDE  
EEA  
ERXO  
GDEM:  
EDDE:  
EEA:  
ERXO:  
ERXHF:  
ELNA:  
ERX(l:0):  
Gain demodulator  
Enable deemphasis (disables bypass)  
Enable earpiece amplifier  
Enable RXO output  
Enable mixer and IF amplifier  
Enable low-noise amplifier  
Enable parts of RXLF  
R4: Enable functions transmit  
SSCCK  
RBAT  
BCOMP  
BSCR  
GMIC  
ETDM  
EPREE  
ETX  
SSCCK:  
RBAT:  
BCOMP:  
BSCR:  
GMIC:  
ETDM:  
EPREE:  
ETX:  
Shift SC-clock (chifts SC-clock by 17/16)  
Battery detection high/low range  
Bypass compressor and expander  
Bypass scrambler and descrambler  
Gain of microphone preamplifier  
Enable transmit data management  
Enable preemphasis (disables bypass)  
Enable TX low frequency part  
R5:  
free  
free  
free  
free  
free  
free  
GEA4  
EXTLO  
GEA4:  
EXTLO:  
Gain earpiece amplifier MSB (see also R1)  
Select input mixer  
R6 – R15: reserved for U3550BM  
Rev. A3, 20-May-98  
13 (17)  
Preliminary Information  
U3500BM  
Example of Mode Setting Using Enable Bits  
(U3500B + U3550B)  
Active Mode  
(Transmission)  
Active Mode  
(PLL  
Convergence  
Waiting)  
Receive Mode Receive Mode Standby Mode Inactive Mode  
(Only Data)  
(RX Waiting)  
(ex. Battery  
Low)  
(Switch Off)  
*PA (VTX PIN),  
EEA  
X
X
*EVCO1 ETX,  
ERX2, ERXO  
X
ERX1  
X
X
X
X
X
X
ERXHF, ELNA  
*EVCO3  
X
RSSI / Battery  
Management  
(MUXDA)  
LOGIC PART  
(Enables when VBatt  
> 3.2 V)  
X
X
X
X
X
X
X
X
X
X
Switch Comparator  
(Always Enabled)  
X
* refer to U3550BM  
14 (17)  
Rev. A3, 20-May-98  
Preliminary Information  
U3500BM  
Application Circuit  
Figure 16.  
Rev. A3, 20-May-98  
15 (17)  
Preliminary Information  
U3500BM  
Package Information  
9.15  
8.65  
Package SO28  
Dimensions in mm  
18.05  
17.80  
7.5  
7.3  
2.35  
0.25  
0.25  
0.10  
0.4  
10.50  
10.20  
1.27  
16.51  
28  
15  
technical drawings  
according to DIN  
specifications  
13033  
1
14  
16 (17)  
Rev. A3, 20-May-98  
Preliminary Information  
U3500BM  
Ozone Depleting Substances Policy Statement  
It is the policy of TEMIC Semiconductor GmbH to  
1. Meet all present and future national and international statutory requirements.  
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems  
with respect to their impact on the health and safety of our employees and the public, as well as their impact on  
the environment.  
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as  
ozone depleting substances (ODSs).  
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and  
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban  
on these substances.  
TEMIC Semiconductor GmbH semiconductor division has been able to use its policy of continuous improvements  
to eliminate the use of ODSs listed in the following documents.  
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively  
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental  
Protection Agency (EPA) in the USA  
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.  
TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting  
substances and do not contain such substances.  
We reserve the right to make changes to improve technical design and may do so without further notice.  
Parameters can vary in different applications. All operating parameters must be validated for each customer  
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized  
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,  
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or  
unauthorized use.  
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany  
Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423  
Rev. A3, 20-May-98  
17 (17)  
Preliminary Information  

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