HV9911_06 [SUPERTEX]
Switch-Mode LED Driver IC with High Current Accuracy; 开关模式LED驱动器IC，具有高电流精度
| 型号： | HV9911_06 |
| 厂家： | 
Supertex, Inc |
| 描述： | Switch-Mode LED Driver IC with High Current Accuracy |
| 文件： | 总14页 (文件大小：728K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV9911
Switch-Mode LED Driver IC with High Current Accuracy
Features
General Description
► Switch mode controller for single switch drivers
The HV9911 is a current mode control LED driver IC
designed to control single switch PWM converters (buck,
boost, buck-boost, or SEPIC), in a constant frequency or
constant off-time mode. The controller uses a peak current
control scheme, (with programmable slope compensation),
and includes an internal transconductance amplifier to
control the output current in closed loop, enabling high
output current accuracy. In the constant frequency mode,
multiple HV9911s can be synchronized to each other, or
to an external clock, using the SYNC pin. Programmable
MOSFET current limit enables current limiting during input
under voltage and output overload conditions. The IC also
includes a 0.2A source and 0.4A sink gate driver for high
power applications. An internal 9 to 250V linear regulator
powers the IC, eliminating the need for a separate power
supply for the IC. HV9911 provides a TTL compatible, PWM
dimming input that can accept an external control signal
with a duty ratio of 0-100% and a frequency of up to a few
kilohertz. The IC also provides a FAULT output which, can
be used to disconnect the LEDs in case of a fault condition,
using an external disconnect FET.
o
o
o
o
Buck
Boost
Buck-boost
SEPIC
► Works with high side current sensing
► Closed loop control of output current
► High PWM dimming ratio
► Internal 250V linear regulator (can be extended
using external zener diodes)
► Internal 2% Voltage Reference (0°C < T < 85°C)
► Constant frequency or constant off-timeAoperation
► Programmable slope compensation
► Enable & PWM dimming
► +0.2A/-0.4A gate drive
► Output short circuit protection
► Output over voltage protection
► Synchronization capability
► Programmable MOSFET current limit
► Soft start
Applications
The HV9911 based LED driver is ideal for RGB backlight
applications with DC inputs. The HV9911 based LED lamp
drivers can achieve efficiency in excess of 90% for buck
and boost applications.
► RGB backlight applications
► Automotive LED driver application
► Battery Powered LED lamps
► Other DC/DC LED drivers
Typical Application Circuit - Boost
L1
D1
Q1
CO
ROVP1
CIN
VIN
GATE
1
3
CDD
RSC
RCS
ROVP2
2
4
5
VDD
GND
CS
OVP
12
11
16
14
13
8
RSLOPE
RT
HV9911
6
7
SC
RT
FAULT
FDBK
COMP
PWMD
SYNC
Q2
CREF
Cc
Rs
REF
10
9
CLIM
IREF
RL2
RL1
RR1
15
RR2
HV9911
Typical Application Circuit - Buck
Rs
HV7800
CO
CIN
D1
VIN
1
12
11
3
OVP
CDD
L1
2
4
VDD
GND
FAULT
GATE
CS
Q1
RSLOPE
RT
HV9911
5
6
7
SC
RT
RSC
Cc
RCS
14
16
13
8
COMP
FDBK
PWMD
SYNC
CREF
REF
10
9
CLIM
IREF
RL2
RL1
RR1
15
RR2
Typical Application Circuit - SEPIC
L1
D1
C1
ROVP1
Q1
CO
CIN
VIN
GATE
1
3
L2
CDD
RSC
RCS
ROVP2
2
4
5
VDD
GND
CS
OVP
12
11
16
14
13
8
RSLOPE
RT
HV9911
6
7
SC
RT
FAULT
FDBK
COMP
PWMD
SYNC
Q2
CREF
Cc
Rs
REF
10
9
CLIM
IREF
RL2
RL1
RR1
15
RR2
2
HV9911
Pin Configuration
Ordering Information
Package Options
16-Lead SOIC
HV9911NG-G
DEVICE
FDBK
IREF
1
2
3
4
5
6
7
8
VIN
16
15
14
13
12
11
10
9
VDD
HV9911
-G indicates package is RoHS compliant (‘Green’)
GATE
GND
CS
COMP
HV9911PWMD
OVP
SC
FAULT
REF
RT
SYNC
CLIM
Absolute Maximum Ratings
Parameter
Value
-0.5V to +250V
VIN to GND
VDD to GND
-0.3V to +13.5V
CS1, CS2 to GND
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
PWMD to GND
GATE to GND
All other pins to GND
Continuous Power Dissipation (TA = +25°C)
16-Pin SOIC (derate 10.0mW/°C above +25°C)
Junction to ambient thermal impedance
Operating ambient temperature range
Junction temperature
1000mW
82OC/W
-40°C to +85°C
+125°C
Storage temperature range
-65°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
3
HV9911
Electrical Characteristics
(Over recommended operating conditions. VIN = 24V, TA = 25°C, unless otherwise specified)
Symbol Parameter
Input
Min
Typ
Max Units Conditions
(1)
VINDC
IINSD
Internal Regulator
Input DC supply voltage range*
-
250
1.5
V
DC input voltage
Shut-down mode supply current*
-
1.0
mA
PWMD connected to GND, VIN = 24V
VIN = 9–250V, IDD(ext) = 0,
VDD
Internally regulated voltage*
7.25
7.75
6.90
500
-
8.25
7.20
-
V
V
PWMD connected to GND
VDD undervoltage lockout
threshold
UVLO
∆UVLO
6.65
VDD rising
VDD undervoltage lockout
hysteresis
-
-
mV
V
---
---
Steady state external voltage that
can be applied at the VDD pin2
VDD(ext)
12
Reference
REF pin voltage
(0°C < TA < 25°C)
1.225
1.25 1.275
REF bypassed with a 0.1µF capacitor
to GND; I = 0; VDD = 7.75V;
PWMD =RGEFND
VREF
V
REF pin voltage
(-40°C < TA < 85°C)
1.2125 1.25 1.275
REF bypassed with a 0.1µF capacitor
to GND; IREF = 0; VDD = 7.25 – 12V;
PWMD = GND
REF bypassed with a 0.1µF
capacitor to GND; IREF = 0-500µ;
PWMD = GND
Line regulation of reference
voltage
VREFLINE
0
0
-
-
20
10
mV
mV
Load regulation of reference
voltage
VREFLOAD
PWM Dimming
VPWMD(lo) PWMD input low voltage*
VPWMD(hi) PWMD input high voltage*
-
-
-
0.80
-
V
V
VDD = 7.25V – 12V
VDD = 7.25V – 12V
VPWMD = 5.0V
2.0
50
RPWMD
GATE
ISOURCE
ISINK
PWMD pull-down resistance
100
150
kΩ
GATE short circuit current
GATE sinking current
GATE output rise time
GATE output fall time
0.2
0.4
-
-
A
A
VGATE = 0V; VDD = 7.75V
VGATE = 7.75V ; VDD = 7.75V
CGATE = 1nF; VDD = 7.75V
CGATE = 1nF; VDD = 7.75V
-
-
-
TRISE
50
25
85
45
ns
ns
TFALL
-
Over Voltage Protection
VOVP
IC shut down voltage*
1.215
1.25
1.285
V
VDD = 7.25 – 12V ; OVP rising
Current Sense
TBLANK
Leading edge blanking
100
-
-
-
375
180
ns
ns
---
COMP = V ; CLIM = REF;
V
CS = 0 tDoD600mV step
TDELAY1
Delay to output of COMP comparator
4
HV9911
Symbol Parameter
Min
-
Typ
Max Units Conditions
COMP = V ; CLIM = 300mV ;
V
CS = 0 DtoD 400mV step
TDELAY2
Delay to output of CLIMIT comparator
-
180
10
ns
VOFFSET
Comparator offset voltage
-10
-
mV
---
Internal Transconductance Opamp
GB
Gain bandwidth product#
-
1.0
-
MHz 75pF capacitance at COMP pin
AV
Open loop DC gain
66
-
-
-
dB
V
Output Open
---
VCM
Input common-mode range#
Output voltage range#
Transconductance
-0.3
0.7
340
-2.0
-
3.0
6.75
530
4.0
1.0
VO
-
-
VDD = 7.75V
gm
435
-
µA/V ---
VOFFSET
IBIAS
Input offset voltage
Input bias current#
mV
nA
---
---
0.5
Oscillator
fOSC1
fOSC2
DMAX
IOUTSYNC
IINSYNC
Oscillator frequency*
Oscillator frequency*
Maximum duty cycle
Sync output current
Sync input current
88
100
350
90
10
-
112
392
-
kHz RT = 909kΩ
kHz RT = 261kΩ
308
-
-
%
---
20
µA
µA
---
0
200
VSYNC < 0.1V
Output Short Circuit
Propagation time for short circuit
detection
IREF = 200mV ; FDBK = 450mV;
FAULT goes from high to low
TOFF
-
-
250
ns
TRISE,FAULT Fault output rise time
TFALL,FAULT Fault output fall time
-
-
-
-
300
200
2.2
ns
ns
1nF capacitor at FAULT pin
1nF capacitor at FAULT pin
IREF = 200mV
GFAULT
Amplifier gain at IREF pin
1.8
2
Soft Start
Current into CLIM pin when pulled
low
FAULT is low ; 06.25k resistor
between REF and CLIM
ICLIM
-
-
200
µA
Slope Compensation
ISLOPE
Current sourced out of SC pin
0
-
100
2.2
µA
-
---
GSLOPE
Internal current mirror ratio
1.8
2
ISLOPE = 50µA ; RCSENSE = 1kΩ
1 See application section for minimum input voltage.
2 Parameters are not guaranteed to be within specifications if the external V voltage is greater than VDD(ext) or if VDD < 7.25V.
* Specifications which apply over the full operating ambient temperature ranDgDe of -40°C < TA < +85°C.
# Guaranteed by design.
5
HV9911
Pin Description
Pin #
Pin
Description
1
VIN
This pin is the input of a 250V high voltage regulator.
This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to
GND (at least 0.1uF).
2
VDD
3
4
GATE
GND
This pin is the output gate driver for an external N-channel power MOSFET.
Ground return for all circuits. This pin must be connected to the return path from the input.
This pin is used to sense the drain current of the external power FET. It includes a built-in 100ns
(min) blanking time.
5
CS
Slope compensation for current sense. A resistor between SC and GND will program the slope
compensation. In case of constant off-time mode of operation, slope compensation is unnecessary
and the pin can be left open.
6
SC
This pin sets the frequency or the off-time of the power circuit. A resistor between RT and GND will
program the circuit in constant frequency mode. A resistor between RT and GATE will program the
circuit in a constant off-time mode.
7
RT
This I/O pin may be connected to the SYNC pin of other HV9911 circuits and will cause the oscillators
to lock to the highest frequency oscillator.
This pin provides a programmable input current limit for the converter. The current limit can be set by
using a resistor divider from the REF pin. Soft start can also be provided using this pin.
8
9
SYNC
CLIM
This pin provides 2% accurate reference voltage. It must be bypassed with at least a 10nF - 0.22µF
capacitor to GND.
10
REF
This pin is pulled to ground when there is an output short circuit condition or output over voltage
condition. This pin can be used to drive an external MOSFET in the case of boost converters to
disconnect the load from the source.
11
12
FAULT
OVP
This pin provides the over voltage protection for the converter. When the voltage at this pin exceeds
1.25V, the gate output of the HV9911 is turned off and FAULT goes low. The IC will turn on when
the power is recycled.
When this pin is pulled to GND (or left open), switching of the HV9911 is disabled. When an external
TTL high level is applied to it, switching will resume.
Stable Closed loop control can be accomplished by connecting a compensation network between
COMP and GND.
13
14
PWMD
COMP
The voltage at this pin sets the output current level. The current reference can be set using a resistor
divider from the REF pin.
15
16
IREF
FDBK
This pin provides output current feedback to the HV9911 by using a current sense resistor.
6
HV9911
Functional Block Diagram
V
VIN
REF
bg
Linear Regulator
POR
VDD
GATE
_
+
CLIM
SS
Blanking
100ns
FAULT
+
_
CS
R
S
Q
1:2
+
ramp
R
S
POR
_
Q
Q
_
+
V
bg
OVP
SC
SS
+
_
FDBK
G
_
+
m
13R
R
SYNC
RT
IREF
One Shot
COMP
SS
2
PWMD
GND
Functional Description
Power Topology
The built in linear regulator of the HV9911 can operate up Note: The equations given below are approximations and are
to 250V at the VIN pin. The linear regulator provides an to be used only for estimation purposes. The actual values
internally regulated voltage of 7.75V (typ) at V if the input will differ somewhat from the computed values.
voltage is in the range of 9V – 250V. This voltaDgDe is used to
power the IC and also provide the power to external circuits Consider the case when the external FET is FDS3692 and
connected at the V and V pins. This linear regulator can the switching frequency is fS = 200kHz with an LED string
be turned off by oDvDerdrivinRgEFthe VDD pin using an external voltage VO = 80V. From the datasheet of the FET, the
boostrap circuit at voltages higher than 8.25V (up to 12V).
following parameters can be determined:
In practice, the input voltage range of the IC is limited by CISS = 746pF
the current drawn by the IC. Thus, it becomes important CGD = CRSS = 27pF
to determine the current drawn by the IC to find out the CGS = CISS - CGD = 719pF
maximum and minimum operating voltages at the V pin. VTH = 3V
The main component of the current drawn by the IC IiNs the
current drawn by the switching FET driver at the GATE pin.
To estimate this current, we need to know a few parameters
of the FET being used in the design and the switching
frequency.
7
HV9911
CGD
HV9911
IPK
RGATE
VDD
I1
CGS
Iavg
t1
t2
t3
0
Fig. 1. Current Sourced out of GATE at
FET turn-on Driver
Fig. 2. Equivalent Circuit
of the Gate Driver
The typical waveform of the current being sourced out of When the external FET is being turned on, current is being
GATE is shown in Fig. 1. Fig. 2 shows the equivalent circuit sourced out of the GATE and that current is being drawn
of the gate driver and the external FET. The values of VDD and from the input. Thus, the average current drawn from VDD
RGATE for the HV9911 are 7.75V and 40 ohms respectively.
(and thus from VIN) needs to be computed. Without going
into the details of the FET operation, the various values in
the graph of Fig. 1 can be computed as follows.
Parameter
Formula
VDD
RGATE
Value (for given example)
IPK
193.75mA
VDD − VTH
RGATE
I1
t1
118.75mA
14.61ns
I1
IPK
-RGATE • CISS • In
V − V
•C
GD
(
)
O
TH
(for a boost converter)
(for a buck converter)
I1
t2
17.5ns
V − VTH • CGD
(
)
IN
I1
t3
2.3 • RGATE • CGS
66ns
Iavg
(I1 • [t1 + t2] + 0.5 • [IPK - I1] • t1 + 0.5 • I1 • t3) • fS
1.66mA
8
HV9911
The total current being drawn from the linear regulator for a ues provided are based on the continuous conduction mode
typical HV9911 circuit can be computed as follows (the val- boost design in the application note - AN-H55).
Current
Quiescent Current
Formula
Typical Value
1000µA
1000µA
VREF
VREF
+
Current sourced out of REF pin
Current sourced out of RT pin
Current sourced out of SC pin
100µA
13.25µA
30.8µA
61.6µA
RL1 +RL2 RR1 +RR2
6V
RT
1 2.5V
•
2 RSLOPE
2.5V
Current sourced out of CS pin
RSLOPE
Current drawn by FET gate driver
IAVG
1660µA
Total Current drawn from the linear
regulator
2.865mA
Note: For a discontinuous mode converter, the currents sourced out of the SC and CS pin will be zero.
Maximum Input Voltage at VIN pin computed
using the Power Dissipation Limit
For this design, at 24V input, the increase in the junction
The maximum input voltage that the HV9911 can withstand
without damage if the regulator is drawing about 2.8mA will
depend on the ambient temperature. If we consider an ambi-
ent temperature of 40°C, the power dissipation in the pack-
age cannot exceed
temperature of the IC (over the ambient) will be
ΔΘ = VIN • ITOTAL • ΘJA
= 5.64OC
where ΘJA is the junction to ambient thermal impedance of
the 16-pin SOIC package of the HV9911.
P
= 1000mW - 10mW • (40OC - 25OC)
MAX = 850mW
Minimum Input Voltage at VIN pin
The above equation is based on package power dissipation
limits as given in the Absolute Maximum Limits section of
this datasheet.
The minimum input voltage at which the converter will start
and stop depends on the minimum voltage drop required for
the linear regulator. The internal linear regulator will regulate
the voltage at the V pin when VIN is between 9 and 250V.
However, when VIN DiDs less than 9V, the converter will still
function as long as V is greater than the under voltage
lockout. Thus, the conDvDerter might be able to start at input
voltages lower than 9V. The start/stop voltages at the VIN pin
can be determined using the minimum voltage drop across
the linear regulator as a function of the current drawn. This
data is shown in Fig. 3 for different junction temperatures.
To dissipate a maximum power of 850mW in the package,
the maximum input voltage cannot exceed
Pmax
ITOTAL
= 296V
V
=
inmax
Since the maximum voltage is far greater than the actual
input voltage (24V), power dissipation will not be a problem
for this design.
9
HV9911
14
13
12
11
10
9
-40°C
25°C
85°C
8
125°C
7
6
5
4
3
2
1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
Minimum drop in Linear Regulator (V)
Fig. 3. Graph of input current vs minimum voltage drop
across linear regulator for different junction temperatures
Assume a maximum junction temperature of 85°C (this give a Note: In order to avoid abnormal startup conditions, the
reasonable temperature rise of 45°C at an ambient tempera- bypass capacitor at the REF pin should not exceed 0.22µF.
ture of 40°C). At 2.86mA input current, the minimum voltage
Oscillator
drop from Fig. 3 can be approximately estimated to be VDROP
= 0.75V. However, before the IC starts switching the current
drawn will be the total current minus the gate drive current.
The oscillator can be set in two ways. Connecting the
oscillator resistor between the RT and GATE pins will
program the off-time. Connecting the resistor between RT
and GND will program the time period.
In this case, that current is I
= 1.2mA. At this current
level, the voltage drop is appQro_TxOiTmALately VDROP1 = 0.4V. Thus,
the start/stop VIN voltages can be computed to be:
In both cases, resistor RT sets the current, which charges
an internal oscillator capacitor. The capacitor voltage ramps
up linearly and when the voltage increases beyond the
internal set voltage, a comparator triggers the SET input of
the internal SR flip-flop. This starts the next switching cycle.
The time period of the oscillator can be computed as:
VINSTART = UVLOMAX + VDROP1
= 7.2V + 0.4V
= 7.60V
VINSTOP = UVLO
- 0.5V + VDROP
= 7.2V -MA0X.5V + 0.75V
= 7.45V
TS ≈ RT x 11pF
Note: In some cases, if the gate drive draws too much cur-
rent, VINSTART might be less than VINSTOP. In such cases, the
control IC will oscillate between ON and OFF if the input volt-
age is between the start and stop voltages. In these circum-
stances, it is recommended that the input voltage be kept
Slope Compensation
For converters operating in the constant frequency mode,
slope compensation becomes necessary to ensure stability
of the peak current mode controller, if the operating duty
cycle is greater than 0.5. Choosing a slope compensation
which is one half of the down slope of the inductor current
ensures that the converter will be stable for all duty cycles.
higher than VINSTOP
.
Reference
HV9911 includes a 2% accurate, 1.25V reference, which can
be used as the reference for the output current as well as
to set the switch current limit. This reference is also used
internally to set the over voltage protection threshold. The
reference is buffered so that it can deliver a maximum of
500µA external current to drive the external circuitry. The
reference should be bypassed with at least a 10nF low ESR
capacitor.
Slope compensation can be programmed by two resistors
inSdLuOPcEtor currSeCnt, the slope compensation resistors can be
R
and R . Assuming a down slope of DS (A/µs) for the
computed as:
10×RSC
R
=
slope
DS×106 ×T × R
s
cs
A typical value for RSC is 499Ω.
10
HV9911
Note: The maximum current that can be sourced out of the pin which goes low during any fault condition. At startup, a
SC pin is limited to 100µA. This limits the minimum value monoshot circuit, (triggered by the POR circuit), resets an
of the R
resistor to 25kΩ. If the equation for slope internal flip-flop which causes FAULT to go high, and remains
compensSaLtOioPEn produces a value of R
less than this high during normal operation. This also allows the gate drive
value, then RSC would have to be increSaLsOPeEd accordingly. It to function normally. This pin can be used to drive an external
is recommended that RSLOPE be chosen in the range of 25kΩ disconnect switch (Q2 in the Typical Boost Application
- 50kΩ.
Circuit on pg.1), which will disconnect the load during a
fault condition. This disconnect switch is very important in a
boost converter, as turning off the switching FET (Q ) during
an output short circuit condition will not remove the 1fault (Q1
is not in the path of the fault current). The disconnect switch
will help to disconnect the shorted load from the input.
Current Sense
The current sense input of the HV9911 includes a built in
100ns (minimum) blanking time to prevent spurious turn off
due to the initial current spike when the FET turns on.
Over Voltage Protection
The HV9911 includes two high-speed comparators – one is
used during normal operation and the other is used to limit Over voltage protection is achieved by connecting the output
the maximum input current during input under voltage or voltage to the OVPpin through a resistive divider. The voltage
overload conditions.
at the OVP pin is constantly compared to the internal 1.25V.
When the voltage at this pin exceeds 1.25V, the IC is turned
The IC includes an internal resistor divider network, which off and FAULT goes low.
steps down the voltage at the COMP pin by a factor of
15. This stepped-down voltage is given to one of the
comparators as the current reference. The reference to the
other comparator, which acts to limit the maximum inductor
current, is given externally.
Output Short Circuit Protection
The output short circuit condition is indicated by FAULT. At
startup, a monoshot circuit, (triggered by the POR circuit),
resets an internal flip-flop, which causes FAULT to go high,
and remains high during normal operation. This also allows
the gate drive to function normally.
It is recommended that the sense resistor RCS be chosen so
as to provide about 250mV current sense signal.
Current Limit
The steady state current is reflected in the reference
voltage connected to the transconductance amplifier. The
instantaneous output current is sensed from the FDBK
terminal of the amplifier. The short circuit threshold current is
internally set to 200% of the steady state current.
Current limit has to be set by a resistor divider from the
1.25V reference available on the IC. Assuming a maximum
operating inductor current I (including the ripple current),
the voltage at the CLIM pin capnk be set as:
5 • RSC
RSLOPE
During short circuit condition, when the current exceeds the
internally set threshold, the SR flip-flop is set and FAULT
goes low. At the same time, the gate driver of the power FET
is inhibited, providing a latching protection. The system can
be reset by cycling the input voltage to the IC.
VCLIM ≥ 1.2 • IPK • RCS
+
• 0.9
Note that this equation assumes a current limit at 120%
of the maximum input current. Also, if VCLIM is greater than
450mV, the saturation of the internal opamp will determine
the limit on the input current rather than the C pin. In such
a case, the sense resistor RCS should be reLdIMuced till VCLIM
reduces below 450mV.
Note: The short circuit FET should be connected before the
current sense resistor as reversing RS and Q2 will affect the
accuracy of the output current (due to the additional voltage
drop across Q2 which will be sensed).
It is recommended that no capacitor be connected between
CLIM and GND. If necessary, the capacitor value must be
chosen to be less than 1000pF.
Synchronization
The SYNC pin is an input/output (I/O) port to a fault tolerant
peer-to-peer and/or master clock synchronization circuit.
For synchronization, the SYNC pins of multiple HV9911
based converters can be connected together, and may also
be connected to the open drain output of a master clock.
When connected in this manner, the oscillators will lock
to the device with the highest operating frequency. When
synchronizing multiple ICs, it is recommended that the same
FAULT Protection
The HV9911 has built-in output over-voltage protection
and output short circuit protection. Both protection features
are latched, which means that the power to the IC must
be recycled to reset the IC. The IC also includes a FAULT
11
HV9911
timing resistor, corresponding to the switching frequency, be recommended that the PWMD pin be used to get zero output
used in all the HV9911 circuits.
current rather than pull the IREF pin to GND.
In rare occasions, given the length of the connecting lines for
the SYNC pins, a resistor between SYNC and GND may be
required to damp any ringing due to parasitic capacitances.
It is recommended that the resistor chosen be greater than
300kΩ.
PWM Dimming
PWM dimming can be achieved by driving the PWMD pin
with a TTL compatible source. The PWM signal is connected
internally to the three different nodes – the transconductance
amplifier, the FAULT output, and the GATE output.
When synchronized in this manner, a permanent HIGH
or LOW condition on the SYNC pin will result in a loss of
synchronization, but the HV9911 based converters will
continue to operate at their individually set operating
frequency. Since loss of synchronization will not result in total
system failure, the SYNC pin is considered fault tolerant.
When the PWMD signal is high, the GATE and FAULT pins
are enabled, and the output of the transconductance opamp
is connected to the external compensation network. Thus,
the internal amplifier controls the output current. When the
PWMD signal goes low, the output of the transconductance
amplifier is disconnected from the compensation network.
Thus, the integrating capacitor maintains the voltage across
it. The GATE is disabled, so the converter stops switching
and the FAULT pin goes low, turning off the disconnect
switch.
Note: The HV9911 is designed to SYNC up to four ICs at a
time without the use of an external buffer. To SYNC more
than four ICs, it is recommended that a buffered external
clock be used.
The output capacitor of the converter determines the
PWM dimming response of the converter, since it has to
get charged and discharged whenever the PWMD signal
Internal 1MHz Transconductance Amplifier
HV9911 includes a built in 1MHz transconductance amplifier, goes high or low. In the case of a buck converter, since the
with tri-state output, which can be used to close the feedback inductor current is continuous, a very small capacitor is used
loop. The output current sense signal is connected to the across the LEDs. This minimizes the effect of the capacitor
FDBK pin and the current reference is connected to the IREF on the PWM dimming response of the converter. However,
pin.
in the case of a boost converter, the output current is
discontinuous, and a very large output capacitor is required
The output of the opamp is controlled by the signal applied to reduce the ripple in the LED current. Thus, this capacitor
to the PWMD pin. When PWMD is high, the output of the will have a significant impact on the PWM dimming response.
opamp is connected to the COMP pin. When PWMD is low, By turning off the disconnect switch when PWMD goes low,
the output is left open. This enables the integrating capacitor the output capacitor is prevented from being discharged,
to hold the charge when the PWMD signal has turned off and thus the PWM dimming response of the boost converter
the gate drive. When the IC is enabled, the voltage on the improves dramatically.
integrating capacitor will force the converter into steady state
almost instantaneously.
Note: Disconnecting the capacitor might cause a sudden
spike in the capacitor voltage as the energy in the inductor
The output of the opamp is buffered and connected to the is dumped into the capacitor. This might trigger the OVP
current sense comparator using a 15:1 divider. The buffer comparator if the OVP point is set too close to the maximum
helps to prevent the integrator capacitor from discharging operating voltage. Thus, either the capacitor has to sized
during the PWM dimming state.
slightly larger or the OVP set point has to be increased.
Note: The HV9911 IC might latch-up if the PWMD pin is
pulled 0.3V below GND, causing failure of the part. This
abnormal condition can happen if there is a long cable be-
tween the PWM signal and the PWMD pin of the IC. It is
recommended that a 1kΩ resistor be connected between
the PWMD pin and the PWM signal input to the HV9911.
This resistor, when placed close to the IC, will damp out any
ringing that might cause the voltage at the PWMD pin to go
below GND.
Linear Dimming
Linear dimming can be accomplished by varying the voltage
at the I
pin, as the output current is proportional to the
voltageRaEFt the IREF pin. This can be done either by using a
potentiometer from the REF pin or by applying an external
voltage source at the IREF pin.
Note: Due to the offset voltage of the transconductance
opamp, pulling the I pin very close to GND will cause the
internal short circuit RcEoFmparator to trigger and shut down the
IC. This limits the linear dimming range of the IC. However,
a 1:10 linear dimming range can be easily obtained. It is
12
HV9911
Avoiding False Shutdowns of the HV9911
The increase in the short circuit response time can be
computed using the various component values of the boost
converter. Consider a boost converter with a nominal output
current IO = 350mA, an output sense resistor RS = 1.24W,
LED string voltage VO = 100V and an output capacitor CO
= 2mF. The disconnect FET is a TN2510N8 from Supertex
which has a saturation current I = 3A (at VGS = 6V). The
increase in the short circuit resSpAoTnse time due to the RC
filter can then be computed as:
The HV9911 has two fault modes which trigger a latched
protection mode - an over current (or short circuit) protection,
and an over voltage protection.
To prevent false triggering due to the tripping of the over
voltage comparator, (due to noise in the GND traces on the
PCB), it is recommended that a 1nF - 10nF capacitor be
connected between the OVP pin and GND. Although this
capacitor will slow down the response of the over voltage
protection circuitry somewhat, it will not affect the overall
performance of the converter, as the large output capacitance
in the boost design will limit the rate of rise of the output
voltage.
Io
∆t ≈ RF •CF • ln 1 -
ISAT −Io
0.35A
3A −0.35A
= 1kΩ•470pF • ln 1 -
⎜
In some cases, the over current protection may be triggered
during PWM dimming, when the FAULT goes high and the
disconnect switch is turned on. This triggering of the over
current protection is related to the parasitic capacitance of
the LED string (shown as a lumped capacitance CLED in Fig.
4).
≈ 66ns
This increase is found to be negligible (note that the equation
is valid for ΔT << RS • CO. In this case, RS • CO = 2.48µs, and
the condition holds.
During normal PWM dimming operation, the HV9911
maintains the voltage across the output capacitor (CO),
by turning off the disconnect switch and preserving the
charge in the output capacitance when the PWM dimming
signal is low. At the same time, the voltage at the drain of
the disconnect FET is some non-zero value VD. When the
PWM dimming signal goes high, FET Q is turned ON. This
causes the voltage at the drain of the FE2T (VD) to instantly go
to zero. Assuming a constant output voltage VO,
Sizing the Output Sense Resistor
To avoid exceeding the peak-current rating of the output
sense resistor during short circuit conditions, the power
rating of the resistor has to be chosen properly.
In this case, the maximum power dissipated in the sense
resistor is:
PSC = IS2AT • RS = 11W
d V − V
(
)
o
d
iSENSE = CLED
= - CLED
•
From the datasheet for a 1.24W, 1/4W resistor, the maximum
power it can dissipate for a single 1ms pulse of current is 11W.
Since the total short circuit time is about 350ns (including the
300ns time for turn off), the resistor should be able to handle
the current.
dt
dVd
dt
•
In this case, the rate of fall of the drain voltage of the
disconnect FET is a large value (since the FET turns on very
quickly) and this causes a spike of current through the sense
resistor, which could trigger the over current protection
(depending on the parasitic capacitance of the LED string).
To prevent this condition, a simple RC low pass filter network
can be added as shown in Fig. 5. Typical values are RF =
1kΩ and CF = 470pF. This filter will block the FDBK pin from
seeing the turn-on spike and normalize the PWM dimming
operation of the HV9911 boost converter. This will have
minimal effect on the stability of the loop but will increase
the response time to an output short. If the increase in the
response time is large, it might damage the output current
sense resistor due to exceeding its peak-current rating.
13
HV9911
VO
VO
CO
CO
CLED
CLED
ROVP2
ROVP2
VD
VD
FAULT
FAULT
FDBK
Q2
RS
Q2
FDBK
i
iSENSE
SENSE
Cf
RS
Fig. 4. Output of the boost converter
showing LED parsed capacitance
Fig. 5. Adding a low-pass filter
to prevent palse triggering.
16-Lead SOIC Package Outline (NG)
9.9 0.10
16
Note 2
6.0 0.20
3.90 0.10
1
Top View
5O - 15O (4 PLCS)
0.25 - 0.50
0.17 - 0.25
45°
Note 3
0O - 8O
1.75 MAX
1.25MIN
0.10 - 0.25
1.27BSC
0.31 - 0.51
0.40 -1.27
End View
Side View
Notes:
1. All dimensions in millimeters; angles in degrees
2. Pin 1 identifier must be located within the indicated area
3. Corner shape may differ from drawing
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9911
NR111406
14
相关型号：
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LED Driver, 1-Segment, 3 X 3 MM, 0.80 MM HEIGHT, 0.65 MM PITCH, GREEN, MO-229WEEC-2, DFN-8
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LED Driver, 1-Segment, PDSO8, 3 X 3 MM, 0.80 MM HEIGHT, 0.65 MM PITCH, GREEN, MO-229WEEC-2, DFN-8
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