HV9912NG-G [SUPERTEX]
Switch-mode LED Driver IC With High Current Accuracy and Hiccup Mode Protection; 开关模式LED驱动器IC，具有高电流精度和打嗝模式保护
| 型号： | HV9912NG-G |
| 厂家： | 
Supertex, Inc |
| 描述： | Switch-mode LED Driver IC With High Current Accuracy and Hiccup Mode Protection |
| 文件： | 总12页 (文件大小：873K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV9912
Preliminary
Switch-mode LED Driver IC
With High Current Accuracy and Hiccup Mode Protection
Features
General Description
► Switch mode controller for single switch
The HV9912 is a current mode control LED driver IC designed
to control single switch PWM converters (buck, boost, buck-boost
or SEPIC) in a constant frequency mode. The controller uses a
peak current-mode control scheme with programmable slope
compensation and includes an internal transconductance amplifier
to control the output current in closed loop enabling high output
current accuracy (in the case of buck and buck-boost converters,
the output current can be sensed using a high side current sensor
like the HV7800). In the constant frequency mode, multiple HV9912
ICs can by synchronized to each other or to an external clock using
the SYNC pin. Programmable MOSFET current limit enables
current limiting during input under voltage and output overload
conditions. The IC also includes a 0.2A source and 0.4A sink gate
driver that makes the HV9912 suitable for high power applications.
An internal 90V linear regulator powers the IC eliminating the need
for a separate power supply for the IC. The IC also provides a
FAULT output, which can be used to disconnect the LEDs in case
of a fault condition using an external disconnect FET. HV9912 also
provides a TTL compatible, low-frequency PWM dimming input that
can accept an external control signal with a duty ratio of 0-100%
and a frequency of up to a few kilohertz. The HV9912 includes
hiccup protection from both short and open circuits, with automatic
recovery after the fault condition is cleared.
drivers
♦
♦
♦
Buck
Boost
Buck-boost and SEPIC
► Works with high side current sensors
► Closed loop control of output current
► High PWM dimming ratio
► Internal 90V linear regulator (can be
extended using external zener diodes)
► Internal 2% voltage reference
(0°C < T < 85°C)
► ConstantAfrequency operation
► Programmable slope compensation
► Linear & PWM dimming
► +0.2A/-0.4A gate drive
► Hiccup Mode Protection for both short circuit
and open circuit conditions
► Synchronization capability
► Pin compatible with HV9911
Applications
► LED backlight applications
► General LED lighting applications
► Battery powered LED lamps
TheHV9912isapincompatiblereplacementtoSupertex’sHV9911.
It is compatible with existing HV9911 designs which have an input
voltage of less than 90V by changing ROVP1, ROVP, and RT.
Typical Application Circuit - Boost
D2
V
IN
L1
D1
Q1
ROVP1
CIN
CO
VIN
GATE
1
3
CDD
RSC
RCS
ROVP2
2
4
5
VDD
GND
CS
OVP
12
11
16
14
13
8
RSLOPE
RT
6
7
SC
RT
FAULT
Q2
HV9912
FDBK
COMP
PWMD
SYNC
CREF
Cc
REF
Rs
10
9
CLIM
IREF
RL1
RR1
15
RL2
RR2
HV9912
Preliminary
Pin Configuration
Ordering Information
Package Options
16-Lead SOIC
HV9912NG-G
FDBK
IREF
VIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DEVICE
VDD
GATE
HV9912
COMP
-G indicates package is RoHS compliant (‘Green’)
HV9912PWMD
GND
CS
OVP
SC
FAULT
REF
RT
Absolute Maximum Ratings
CLIM
SYNC
Parameter
VIN to GND
VDD to GND
Value
-0.5V to +100V
-0.3V to +13.5V
16-Lead SOIC (NG)
(top view)
CS to GND
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
Product Marking
PWMD to GND
GATE to GND
All other pins to GND
Top Marking
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
HV9912NG
YWW LLLLLLLL
Continuous Power Dissipation (TA = +25°C)
Thermal impedance (θja)
1200mW
82OC/W
Bottom Marking
= “Green” Packaging
*May be part of top marking
CCCCCCCCC AAA
Junction temperature
+125°C
Storage temperature range
-65°C to +150°C
16-Lead SOIC (NG)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Electrical Characteristics
(The * denotes the specifications which apply over the full operating ambient temperature range of 0OC < TA < +85OC, otherwise the specifications are at
TA = 25OC. VIN = 12V, unless otherwise noted.)
Sym
Input
VINDC
IINSD
Parameter
Min
Typ
Max
Units Conditions
(1)
Input DC supply voltage range
Shut-down mode supply current
*
*
-
-
90
V
DC input voltage
-
1.5
mA
PWMD connected to GND
Internal Regulator
VIN = 9.0 - 90V,
VDD
Internally regulated voltage
*
7.25
6.5
-
7.75
-
8.25
7.0
-
V
V
PWMD connected to GND
VDD undervoltage lockout
threshold
VDD undervoltage lockout
hysteresis
UVLORISE
UVLOHYST
VDD rising
VDD falling
500
mV
2
HV9912
Preliminary
Electrical Characteristics (cont.)
(The * denotes the specifications which apply over the full operating ambient temperature range of 0OC < TA < +85OC, otherwise the specifications are at
TA = 25OC. VIN = 12V, unless otherwise noted.)
Sym
Parameter
Min
Typ
Max
Units Conditions
Reference
REF bypassed with a 0.1µF
capacitor to GND; IREF = 0;
PWMD = GND
VREF
REF pin voltage
*
1.225 1.25 1.275
V
REF bypassed with a 0.1µF
capacitor to GND; IREF = 0;
VDD = 7.25 – 12V; PWMD = GND
Line regulation of reference
voltage
VREFLINE
0
0
-
-
20
10
mV
mV
REF bypassed with a 0.1µF
capacitor to GND;
IREF = 0-500µA; PWMD = GND
Load regulation of reference
voltage
VREFLOAD
PWM Dimming
VPWMD(lo)
VPWMD(hi)
RPWMD
PWMD input low voltage
*
*
-
-
-
0.8
-
V
V
---
PWMD input high voltage
2.0
50
---
PWMD pull-down resistance
100
150
kΩ
VPWMD = 5.0V
GATE
ISOURCE
ISINK
GATE short circuit current
GATE sinking current
GATE output rise time
GATE output fall time
0.2
0.4
-
-
A
A
VGATE = 0V
-
-
-
VGATE = VDD
CGATE = 1.0nF
CGATE = 1.0nF
TRISE
50
25
85
45
ns
ns
TFALL
-
Over Voltage Protection
VOVP, RISING Over voltage rising trip point
4.75
-
5.00
0.50
5.25
-
V
V
OVP rising
OVP falling
VOVP, HYST Over voltage Hysteresis
Current Sense
TBLANK
Leading edge blanking
*
100
-
-
-
250
200
ns
ns
---
Delay to output of COMP
comparator
COMP = VDD ; CLIM = REF;
CSENSE = 0 to 600mV step
TDELAY1
Delay to output of CLIMIT
comparator
COMP = VDD ; CLIM = 300mV;
CSENSE = 0 to 400mV step
TDELAY2
VOFFSET
-
-
-
200
10
ns
Comparator offset voltage
-10
mV
---
Internal Transconductance Opamp
GB
Gain bandwidth product
Open loop DC gain
Input common-mode range
Output voltage range
Transconductance
#
-
1.0
-
MHz 75pF capacitance at OP pin
AV
60
-
-
-
dB
V
Output open
VCM
VO
#
#
-0.3
0.7
450
-5.0
-
3.0
6.75
650
5.0
1.0
---
---
-
V
Gm
550
-
µA/V ---
VOFFSET
IBIAS
Input offset voltage
Input bias current
mV
nA
---
---
#
0.5
3
HV9912
Preliminary
Electrical Characteristics (cont.)
(Over recommended operating conditions. VIN = 24V, TA = 25°C, unless otherwise specified)
Sym
Parameter
Min
Typ
Max Units Conditions
Oscillator
fOSC1
Oscillator frequency
Oscillator frequency
Maximum duty cycle
SYNC input high
*
*
99
510
87
2.0
-
106
118
650
93
-
kHz
kHz
%
RT = 500kΩ
fOSC2
580
RT = 96kΩ
DMAX
-
-
---
---
---
---
VSYNCH
VSYNCL
IOUTSYNC
V
SYNC input low
-
0.8
-
V
SYNC output current
-
18
µA
Output Short Circuit
GSC
Gain for short circuit comparator
1.9
2.0
-
2.1
V
V
---
Minimum output voltage of the
gain stage
VOMIN
*
0.125
0.25
IREF = GND
PWMD = VDD, IREF = 400mA;
FDBK step from 0 to 900mV;
FAULT goes from high to low
Propagation time for short circuit
detection
TOFF
-
-
-
250
ns
TRISE,FAULT Fault output rise time
TFALL,FAULT Fault output fall time
TBLANK,SC Blanking time
-
-
-
300
300
700
ns
ns
ns
330pF capacitor at FAULT pin
330pF capacitor at FAULT pin
---
*
*
500
Current source at COMP pin used
for hiccup mode protection
IHICCUP
5.0
-
µA
---
Slope Compensation
ISLOPE
Current sourced out of SC pin
0
-
100
2.2
µA
-
---
GSLOPE
Internal current mirror ratio
1.8
2.0
ISLOPE = 50µA ; RSC = 1.0kΩ
Notes:
(1) See Application Information for Minimum Input Voltage.
*
#
The specifications which apply over the full operating temperature range at 0OC < TA < +85OC are guaranteed by design and characterization.
Denotes specifications guaranteed by design.
4
HV9912
Preliminary
Functional Block Diagram
VIN
Linear Regulator
V
REF
bg
VDD
+
_
5.60/6.10V
SS
POR
_
+
CLIM
CS
Blanking
TBLANK
GATE
Q
1:2
+
ramp
R
FAULT
SS
_
S
SC
POR OVD SCD
5V rising
4.5V falling
13R
R
Hiccup/Dimming
Block
COMP
OVPD
OVP
TBLANK,SC
PWMD
SS
SCD
SYNC
RT
_
FDBK
IREF
One Shot
GM
+
2
PWMD
PWMD
GND
Functional Description
Power Topology
hysteretic over-voltage protection and hiccup mode short
The HV9912 is a switch-mode converter LED driver de- circuit protection. The IC includes a blanking network con-
signed to control a continuous conduction mode buck or trolled by the PWMD input to prevent the short circuit protec-
boost in a constant frequency (or constant off-time) mode. tion from triggering prematurely during PWM dimming due
The IC includes an internal linear regulator, which operates to the parasitic capacitance of the LED string. It also allows
from input voltages up to 90V eliminating the need for an the IREF pin to be pulled all the way down to GND without
external power supply for the IC. The IC includes features triggering the short circuit protection. It is a pin compatible
typically required in LED drivers like open LED protection, replacement to the HV9911.
output short circuit protection, linear and PWM dimming,
programmable input current limiting and accurate control of Linear Regulator
the LED current. A high current gate drive output enables the The HV9912 can be powered directly from its VIN pin that
controller to be used in high power converters.
withstands a voltage up to 90V. When a voltage is applied at
the VIN pin, the HV9912 tries to maintain a constant 7.75V
The HV9912 is an enhanced version of the HV9911 with (typ) at the VDD pin. The regulator also has a built in under-
5
HV9912
Preliminary
voltage lockout which shuts off the IC if the voltage at the In this case, the gate drive draws too much current and
VDD pin falls below the UVLO threshold.
VIN
is less than VINSTOP. In such cases, the IC will oscil-
lateSbTAeRtTween ON and OFF if the input voltage is between the
The VDD pin must be bypassed by a low ESR capacitor start and stop voltages. In these circumstances, it is recom-
(≥0.1µF) to provide a low impedance path for the high fre- mended that the input voltage be kept higher than VINSTOP
.
quency current of the output gate driver.
Reference
The input current drawn from the VIN pin is a sum of the HV9912 includes a 2% accurate, 1.25V reference, which
1.5mA current drawn by the internal circuit and the current can be used as the reference for the output current as well
drawn by the gate driver (which in turn depends on the switch- as to set the switch current limit. The reference is buffered
ing frequency and the gate charge of the external FET).
so that it can deliver a maximum of 500µA external current
to drive the external circuitry. The reference should be by-
IIN = 1.5mA + (QG x fS)
(Eqn. 1) passed with at least a 10nF low ESR capacitor.
In the above equation, fs is the switching frequency and Q
Note: In order to avoid abnormal start-up conditions, the by-
is the gate charge of the external FET (which can be obG- pass capacitor at the REF pin should not exceed 0.1μF.
tained from the datasheet of the FET).
Oscillator
Minimum Input Voltage at VIN pin
Connecting a resistor between RT and GND will program the
The minimum input voltage at which the converter will start time period.
and stop depends on the minimum voltage drop required for
the linear regulator. The internal linear regulator will regulate In both cases, resistor RT sets the current which charges
the voltage at the VDD pin when VIN is between 9V and 90V. an internal oscillator capacitor. The capacitor voltage ramps
However, when VIN is less than 9V, the converter will still up linearly and when the voltage increases beyond the
function as long as VDD is greater than the under voltage internal set voltage, a comparator triggers the SET input of
lockout. Thus, the converter might be able to start at lower the internal SR flip-flop. This starts the next switching cycle.
than 9V. The start/stop voltages at the VIN pin can be deter- The time period of the oscillator can be computed as:
mined using the minimum voltage drop across the linear reg-
ulator as a function of the current drawn. This data is shown
in Fig. 1 for ambient temperatures of 25ºC and 85ºC.
TS ≈ RT x 18pF
(Eqn. 3)
Synchronization
Assume an ambient temperature of 85OC. Assuming the IC The SYNC pin is an input/output (I/O) port to a fault toler-
is driving a 15nC gate charge FET at 200kHz, the total input ant peer-to-peer and/or master clock synchronization circuit.
current is estimated to be 4.5mA (using Eqn. 1). At this input For synchronization, the SYNC pins of multiple HV9912
current, the minimum voltage drop from Fig. 1 can be ap- based converters can be connected together and may also
proximately estimated to be VDROP = 1.25V. However, before be connected to the open drain output of a master clock.
the IC starts switching the current drawn will be 1.5mA. At When connected in this manner, the oscillators will lock to
this current level, the voltage drop is approximately VDROP1
=
the device with the highest operating frequency. When syn-
0.3V. Thus, the start/stop VIN voltages can be computed to chronizing multiple ICs, it is recommended that the same
be:
timing resistor be (corresponding to the switching frequency)
(Eqn. 2) be used in all the HV9912 circuits.
VINSTART = UVLOMAX + VDROP1
= 7.0V + 0.3V
= 7.3V
In rare occasions, given the length of the connecting lines for
the SYNC pins, a resistor between SYNC and GND may be
required to damp any ringing due to parasitic capacitances.
It is recommended that the resistor chosen be greater than
300kΩ.
VINSTOP = UVLO
- ΔUVLO + VDROP
= 7.0V -M0A.X5V + 1.25V
= 7.75V
Fig. 1 Headroom vs Input Current
Minimum Voltage Drop vs. IIN
When synchronized in this manner, a permanent HIGH or
LOW condition on the SYNC pin will result in a loss of syn-
chronization, but the HV9912 based converters will continue
to operate at their individually set operating frequency. Since
loss of synchronization will not result in total system failure,
the SYNC pin is considered fault tolerant.
3
2.5
2
O
T
A = 85 C
1.5
1
O
TA = 25 C
0.5
0
0
2
4
6
8
10
IIN (mA)
6
HV9912
Preliminary
Slope Compensation
Note that this equation assumes a current limit at 120%
For continuous conduction mode converters operating in the of the maximum input current. Also, if VCLIM is greater than
constant frequency mode, slope compensation becomes 450mV, the saturation of the internal opamp will determine
necessary to ensure stability of the peak current mode con- the limit on the input current rather than the CLIM pin. In
troller, if the operating duty cycle is greater than 0.5. Choos- such a case, the sense resistor RCS should be reduced till
ing a slope compensation which is one half of the down VCLIM reduces below 550mV.
slope of the inductor current ensures that the converter will
be stable for all duty cycles.
It is recommended that no capacitor be connected between
CLIM and GND.
Slope compensation can be programmed by two resistors
R
and RSC. Assuming a down slope of DS (A/µs) for the Internal 1MHz Transconductance Amplifier
inSdLuOcPEtor current, the slope compensation resistors can be HV9912 includes a built in 1MHz transconductance ampli-
computed as:
RSC = RSLOPE x DS x 106 x TS x RCS
10
fier, with tri-state output, which can be used to close the
feedback loop. The output current sense signal is connected
(Eqn. 4) to the FDBK pin and the current reference is connected to
the IREF pin.
where RCS is the current sense resistor which senses the The output of the opamp is controlled by the signal applied
switching FET current.
to the PWMD pin. When PWMD is high, the output of the
opamp is connected to the COMP pin. When PWMD is low,
Note: The maximum current that can be sourced out of the the output is left open. This enables the integrating capacitor
SC pin is limited to 100µA. This limits the minimum value of to hold the charge when the PWMD signal has turned off the
the RSLOPE resistor to 25kΩ. If the equation for slope com- gate drive. When the IC is enabled, the voltage on the inte-
pensation produces a value of R
mendeSdC that RSLOPE be chosen in the range of 25kΩ - 50kΩ.
less than this value, grating capacitor will force the converter into steady state
then R would have to be reduceSdLOaPcEcordingly. It is recom- almost instantaneously.
The output of the opamp is buffered and connected to the
current sense comparator using a 15:1 divider. The buffer
Current Sense
The current sense input of the HV9912 includes a built in helps to prevent the integrator capacitor from discharging
100ns (minimum) blanking time to prevent spurious turn off during the PWM dimming state.
due to the initial current spike when the FET turns on.
PWM Dimming
The HV9912 includes two high-speed comparators - one is PWM dimming can be achieved by driving the PWMD pin
used during normal operation and the other is used to limit with a TTL compatible square wave source. The PWM sig-
the maximum input current during input under voltage or nal is connected internally to the three different nodes - the
overload conditions.
transconductance amplifier, the FLT output and the GATE
output.
The IC includes an internal resistor divider network, which
steps down the voltage at the COMP pin by a factor of 15. When the PWMD signal is high, the GATE and FLT pins
This stepped-down voltage is given to one of the compara- are enabled and the output of the transconductance opamp
tors as the current reference. The reference to the other is connected to the external compensation network. Thus,
comparator, which acts to limit the maximum inductor cur- the internal amplifier controls the output current. When the
rent, is given externally.
PWMD signal goes low, the output of the transconductance
amplifier is disconnected from the compensation network.
It is recommended that the sense resistor RCS be chosen so Thus, the integrating capacitor maintains the voltage across
as to provide about 250mV current sense signal.
it. The GATE is disabled, so the converter stops switching
and the FLT pin goes low, turning off the disconnect switch.
Current Limit
Current limit has to be set by a resistor divider from the The output capacitor of the converter determines the PWM
1.25V reference available on the IC. Assuming a maximum dimming response of the converter, since it has to get
operating inductor current I (including the ripple current), charged and discharged whenever the PWMD signal goes
the maximum voltage at thePCK LIM pin can be set as:
high or low. In the case of a buck converter, since the in-
ductor current is continuous, a very small capacitor is used
(Eqn. 5) across the LEDs. This minimizes the effect of the capacitor
on the PWM dimming response of the converter. However,
in the case of a boost converter, the output current is dis-
VCLIM ≥ 1.2 x IPK x RCS + 5 x RCS x 0.9
RSLOPE
7
HV9912
Preliminary
continuous and a very large output capacitor is required to the COMP pin is disconnected from the G amplifier and the
reduce the ripple in the LED current. Thus, this capacitor will GATE and FLT pins are pulled low disabliMng the LED driver.
have a significant impact on the PWM dimming response. When the fault has cleared, a 5μAcurrent source is activated
By turning off the disconnect switch when PWMD goes low, which pulls the COMP network up to 5V. Once the voltage
the output capacitor is prevented from being discharged and at the COMP network reaches 5V, the 5μA sourcing current
thus the PWM dimming response of the boost converter is is disconnected and a 5μA sinking current is activated which
greatly improved.
pulls the COMP pin low. When the voltage at the COMP pin
reaches 1V, the sinking current is disconnected and the Gm
Note that in case of continuous conduction mode boost con- amplifier is reconnected to the COMP pin. The FLT pin goes
verters, disconnecting the capacitor might cause a sudden high and the GATE pin is now allowed to switch. The closed
spike in the capacitor voltage as the energy in the inductor loop control then takes over the control of the LED current.
is dumped into the capacitor. This increase in the capacitor
voltage might cause the OVP comparator to trip if the OVP Startup Condition
point is set too close to the maximum operating voltage. The startup waveforms are shown in Fig. 2.
Thus, either the capacitor has to larger to absorb this energy
without increasing the capacitor voltage significantly or the Assuming a pole-zero R-C network at the COMP pin (series
OVP set point has to be increased.
combination of RZ and CZ in parallel with CC), the start-up
delay time can be approximately computed as
False Triggering of the Short Circuit Comparator During
PWM Dimming
During PWM dimming, the parasitic capacitance of the LED
string causes a spike in the output current when the discon-
tdelay ≈ tPOR + ( CC + CZ) x 9V
5µA
(Eqn. 8)
nect FET is turned on. With the HV9911, this parasitic spike This equation assumes that the voltage drop across RZ can
in the output current caused the IC to falsely detect an over be neglected compared to the voltage swing at the COMP
current condition and shut down. To prevent this false shut- pin, which is true in most of the cases (RZ < 100kΩ). The
down, an R-C filter was used at the FDBK pin to filter this POR time (tPOR) for the HV9912 is 10μs.
spike.
To prevent these false triggering in the HV9912, there is a
built-in 500ns blanking network for the short circuit compara-
tor, which eliminates the need for the external R-C low pass
filter. This blanking network is activated when the PWMD
input goes high. Thus, the short circuit comparator will not
see the spike in the LED current during the PWM Dimming
turn-on transition. Once the blanking timer is completed, the
short circuit comparator will start monitoring the output cur-
rent. Thus, the total delay time for detecting a short circuit
will depend on the condition of the PWMD input.
VIN
POR
If the output short circuit exists before the PWMD signal
goes high, the total detection time will be:
Pull-up
with 5µΑ
Pull-down
with 5µΑ Gm control
COMP
5V
tdetect1 = tblank,SC(max)+ t
≈ 700 + 250
(Eqn. 6)
delay(max) ≈ 950ns(max)
1V
If the short circuit occurs when the PWMD signal is already
high, the time to detect will be:
tPOR
FLT
tdetect1 = tdelay(max) ≈ 250ns(max)
(Eqn. 7)
t
delay
Hiccup Timer
The HV9912 reuses the compensation network on the
COMP pin to create a timer which is activated upon startup
or when a detected fault has been cleared. When a fault is
detected (either open circuit or short circuit) or upon startup,
Fig. 2 Waveforms During Startup
8
HV9912
Preliminary
FAULT Condition
When the load is disconnected in a boost converter, the
In the case of a fault condition (either open circuit or short output voltage rises as the output capacitor starts charging.
circuit), the same sequence is repeated with the only differ- When the output voltage reaches the OVP rising threshold,
ence being that the COMP pin voltage does not start from the HV9912 detects an over voltage condition and turns off
zero, but rather from its steady-state condition.
the converter. The converter is turned back on only when the
output voltage falls below the falling OVP threshold (which
is 10% lower than the rising threshold). This time is mostly
Short Circuit Protection
When a short circuit condition is detected (output current be- dictated by the R-C time constant of the output capacitor Co
comes higher than twice the steady state current), the GATE and the resistor network used to sense over voltage (ROVP1
and FLT outputs are pulled low. As soon as the disconnect + R
). In case of a persistent open circuit condition, this
FET is turned off, the output current goes to zero and the cyclOeVPk2eeps repeating maintaining the output voltage within
short circuit condition disappears. At this time, the hiccup a 10% band.
timer is started (Fig. 3). Once the timing is complete, the
converter attempts to restart. If the fault condition still per- In most designs, the lower threshold voltage of the over volt-
sists, the converter shuts down and goes through the cycle age protection when the converter will be turned on will be
again. If the fault condition is cleared (due to a momentary more than the LED string voltage. Thus, when the LED load
output short) the converter will start regulating the output is reconnected to the output of the converter, the voltage
current normally. This allows the LED driver to recover from differential between the actual output voltage and the LED
accidental shorts without having to reset the IC.
string voltage will cause a spike in the output current when
the FLT signal goes high. This causes a short circuit to be
The hiccup time will depend on the steady state voltage of detected and the HV9912 will go into short circuit protec-
the COMP pin (VCOMP). This is typically in the range of 3V - tion. This behavior continues till the output voltage becomes
4V. The hiccup time can be approximately computed as:
lower than the LED string voltage, at which point no fault
will be detected and normal operation of the circuit will com-
(Eqn. 9) mence (Fig. 4).
tHICCUP ≈ (CC + CZ) x 9V - VCOMP
5µA
The various delay times can be computed as follows:
Output Current
tRC ≈ 0.1 x (ROVP1 + ROVP2) x CO
(Eqn. 10)
(Eqn. 11)
(Eqn. 12)
Short Circuit
occurs
NormalOperation
Resumes
tHICCUP1 ≈ (CC + CZ) x 9V - VCOMP
5µA
tHICCUP2-n ≈ (CC + CZ) x 9V
5µA
FLT
Hiccup Time
Note that the number of hiccup cycles might be more than
two.
COMP
5V
1V
thiccup
Fig. 3 Short Circuit Protection
Over Voltage Protection
The HV9912 provides hysteretic over voltage protection
allowing the IC to recover in case the LED load is discon-
nected momentarily.
9
HV9912
Preliminary
Linear Dimming
To overcome this in the HV9912, the minimum output of the
Linear dimming can be accomplished by varying the voltage gain stage is limited to 125 ~ 250mV, allowing the IREF pin
at the IREF pin, as the output current is proportional to the to be pulled all the way to 0V without triggering the short cir-
voltage at the IREF pin. This can be done either by using a cuit comparator. Note: Since this control IC is a peak current
potentiometer from the REF pin or by applying an external mode controller, pulling the IREF pin to zero will not cause
voltage source at the IREF pin.
the LED current to become zero. The converter will still be
operating at its minimum on-time causing a very small cur-
In the HV9911, due to the offset voltage of the short circuit rent to flow through the LEDs. To get zero LED current, the
comparator as well as the non-linearity of the X2 gain stage, PWMD input has to be pulled to GND.
pulling the IREF pin very close to GND will cause the internal
short circuit comparator to trigger and shut down the IC.
LED strin g
reconnects
OVP ON
Output Cap
Voltage
100V
LED string voltage
90V
80V
OVP OFF
LED string
disconnects
FLT
t
RC
t
hiccup2
t
hiccup1
Output Current
COMP
5V
1V
Fig. 4 Open Circuit Protection
10
HV9912
Preliminary
Pin Description
Pin #
Pin
Description
1
VIN
This pin is the input of a 90V high voltage regulator.
This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to
GND (at least 0.1µF).
2
3
4
VDD
GATE
GND
This pin is the output gate driver for an external N-channel power MOSFET.
Ground return for all the low power analog internal circuitry. This pin must be connected to the return
path from the input.
This pin is used to sense the source current of the external power FET. It includes a built-in 100ns
(min) blanking time.
5
6
CS
SC
This pin is used to set the slope compensation.
This pin sets the frequency of the power circuit. A resistor between RT and GND will program the
circuit in constant frequency mode.
7
RT
This I/O pin may be connected to the SYNC pin of other HV9912 circuits and will cause the oscillators
to lock to the highest frequency oscillator.
This pin provides a programmable input current limit for the converter. The current limit can be set
by using a resistor divider from the REF pin.
This pin provides 2% accurate reference voltage. It must be bypassed with a 0.01μF – 0.1μF
capacitor to GND.
8
9
SYNC
CLIM
REF
10
This pin is pulled to ground when there is an output short circuit condition or output over voltage
condition. This pin can be used to drive an external MOSFET in the case of boost converters to
disconnect the load from the source.
11
12
FAULT
OVP
This pin provides the over voltage protection for the converter. When the voltage at this pin exceeds
5V, the gate output of the HV9912 is turned off and FLT goes low. The IC will turn on when the
voltage at the pin goes below 4.5V.
When this pin is pulled to GND (or left open), switching of the HV9912 is disabled. When an external
TTL high level is applied to it, switching will resume.
Stable Closed loop control can be accomplished by connecting a compensation network between
COMP and GND. This capacitor also controls the hiccup time.
13
14
PWMD
COMP
The voltage at this pin sets the output current level. The current reference can be set using a resistor
divider from the REF pin.
15
16
IREF
FDBK
This pin provides output current feedback to the HV9912 by using a current sense resistor.
11
HV9912
Preliminary
16-Lead SOIC (Narrow Body) Package Outline (NG)
9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
θ1
D
16
E1
E
Note 1
(Index Area
D/2 x E1/2)
Gauge
Plane
L2
1
Seating
Plane
L
θ
L1
Top View
View B
A
View
B
h
Note 1
A A2
A1
h
Seating
Plane
e
b
A
Side View
View A-A
Note 1:
This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a
mold, or an embedded metal or marked feature.
Symbol
A
1.35
-
A1
0.10
-
A2
1.25
-
b
0.31
-
D
9.80
9.90
E
5.80
6.00
E1
e
h
0.25
-
L
0.40
-
L1
L2
θ
0O
-
θ1
5O
-
MIN
NOM
MAX
3.80
3.90
4.00
Dimension
(mm)
1.27
BSC
1.04
REF
0.25
BSC
1.75
0.25
1.65
0.51 10.00 6.20
0.50
1.27
8O
15O
JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005.
Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9912
NR092607
12
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