HV514WG-G [SUPERTEX]
Buffer/Inverter Based Peripheral Driver, PDSO20, 12.80 X 7.50 MM, 2.65 MM HEIGHT, 1.27 MM PITCH, GREEN, MS-013AC, SOW-20;
| 型号： | HV514WG-G |
| 厂家： | 
Supertex, Inc |
| 描述： | Buffer/Inverter Based Peripheral Driver, PDSO20, 12.80 X 7.50 MM, 2.65 MM HEIGHT, 1.27 MM PITCH, GREEN, MS-013AC, SOW-20 驱动 光电二极管 接口集成电路 |
| 文件： | 总6页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV514
8-Channel Serial to Parallel Converter
with High Voltage Push-Pull Outputs
Features
General Description
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HVCMOS‚ technology
The HV514 is a low voltage serial to high voltage parallel
converter with 8 high voltage push-pull outputs. This device has
been designed to drive small capacitve loads such as piezoelec-
tric transducers. It can also be used in any application requiring
multiple high voltage outputs, medium current sourcing and
sinking capabilities.
Operating output voltage of 250V
Low power level shifting from 5V to 250V
Shift clock speed 8MHz @ VDD=5V
8 latch data outputs
The device consists of an 8-bit shift register, dual 8-bit latches,
and control logic to latch data, and control blanking of the
outputs. Data is shifted through the shift register on the rising
transition of the clock. A data output buffer is provided for
cascading devices. Operation of the shift register is not affected
by the /LE, SEL, or the /BL inputs. Transfer of data from the shift
register to the latch occurs when the /LE is high. Shift register
data is shifted to the 8-bit Data Latch when SEL is high; and shift
register data is shifted to the 8-bit Polarity Latch when SELis low.
The data is held in the output latches whenever /LE is low.
Output blanking
CMOS compatible inputs
Programmable POL latch
Applications
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Piezoelectric transducer driver
Weaving applications
Braille
The high voltage output state is primarily dependent on the value
in the polarity latch. If the blank, /BL, is low, the output condition
is the result of a 1 being exclusively-NOR’ed with the polarity
latch value. If /BL is high, the output condition is the result of the
data latch being exclusively-NOR’ed with the polarity latch.
Printers
MEMs
Displays
All outputs with have a break-before-make circuitry to reduce
cross-over current during output state changes.
Note: /LE, SEL, and /BL have internal 20k-ohm pull-up resistors.
Top Block Diagram
V
DD
V
PP
HV
1
OUT
D
IN
CLK
D
OUT
•
•
•
•
•
•
8
8
8
HV 8
OUT
GND
LE*
BL*
SEL
08/08/03
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV514
DC Electrical Characteristics (Over operating supply voltages unless otherwise noted)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
IDD
VDD supply current
4
mA
fCLK=8MHz, LE*=LOW
0.1
2.0
100
100
10
All VIN=VDD
IDDQ
Quiescent VDD supply current
mA
All VIN=0V
IPP
IPPQ
IIH
VPP supply current
Quiescent VPP supply current
High-level logic input current
µA
µA
µA
VPP=250V, fOUT=300Hz, no load
VPP=240V, outputs static
VIH=VDD
-10
-350
0.1
VIL=0V
IIL
Low-level logic input current
Dynamic IPP
µA
mA
V
VIL=0V, for inputs w/pull-up resistors
fOUT=100kHz, no load
VPP =200V, IHVOUT=-20mA
IDOUT=-0.1mA
VDD =4.5V, IHVOUT=20mA
IDOUT=0.1mA
IDPP
VOH
HVOUT
Data out
HVOUT
140
VDD-1V
High-level output
60
1.0
VOL
Low-level output
V
Data out
DC Electrical Characteristics (Over operating supply voltages unless otherwise noted)
Symbol
fCLK
fOUT
tW
Parameter
Min
Typ
Max
Units
MHz
Hz
ns
Conditions
Clock frequency
Output switching frequency (SOA limited)
Clock width high and low
0
8
300
CL=50nF, VPP=200V
62
15
30
80
35
40
tSU
tH
Data setup time before clock rises
Data hold time after clock rises
ns
ns
tWLE
tDLE
tSLE
Width of latch enable pulse
/LE delay time after rising edge of clock
/LE setup time before rising edge of clock
ns
ns
ns
tOR, tOF Rise/fall time of HVOUT
td ON/OFF Delay time for output to start rise/fall
1000
500
110
110
5
µs
ns
ns
ns
CL=100nF, VPP=200V
tDHL
tDLH
TR, tF
Delay time clock to DOUT high to low
Delay time clock to DOUT low to high
All logic inputs
CL=15pF
CL=15pF
ns
Absolute Maximum Ratings*
Ordering Information
Supply Voltage, VDD
-0.5V to 6V
275V
Device Part Number
HV514 HV514WG
Package
Die
Supply Voltage, VPP
24 Lead SOW
HV514X
Logic input levels
-0.5V to VDD+0.5V
0.3A
Ground current
High voltage supply current
Continuous total power dissipation
Operating temperature range
Storage temperature range
* All voltages are referenced to device ground.
0.25A
750mW
-40°C to +85°C
-65°C +150°C
2
HV514
Operating Supply Voltages
Symbol
Parameter
Min
4.5
Typ
Max
5.5
Units
V
Conditions
VDD
Logic supply voltage
5.0
VPP
High voltage supply
50
250
VDD
0.9
V
Note 1
VIH
High-level input voltage
Low-level input voltage
Operating free-air temperature
VDD-0.9
0
V
VIL
V
TA
-40
+85
° C
Notes:
1. Below minimum VPP the output may not switch.
2. Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply VPP
Power-down sequence should be the reverse of the above.
.
.
Input and Output Equivalent Circuits
V
DD
V
V
PP
DD
*
20kΩ
Data Out
HV
OUT
Input
GND
GND
HV
GND
Logic Inputs
Logic Data Output
High Voltage Outputs
* BL, SEL, LE
Note: There is an internal output resistor for the high voltage output pin for SOA protection
3
HV514
Switching Waveforms
VIH
VIL
VIH
VIL
Data Input
50%
Data Valid
50%
50%
tSU
tH
CLK
50%
50%
50%
tWL
tWH
VOH
VOL
50%
50%
tDLH
Data Out
VOH
VOL
tDHL
VIH
50%
50%
LE
VOL
tWLE
tSLE
tDLE
VOH
VOL
90%
10%
HVOUT
w/ S/R LOW
td
tR
90%
tF
OFF
VOH
VOL
HVOUT
w/ S/R HIGH
10%
td
ON
/BL, /LE, and SEL hav internal 20kΩ pull-up resistors.
Functional Block Diagram
BL
HVOUT1
SR1
SR8
D1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
L/T
DIN
•
•
•
•
•
•
8-bit
SHIFT
8-bit
DATA
LATCH
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CLK
REGISTER
DOUT
LE
P1
•
•
•
•
•
•
•
•
•
•
8-bit
POLARITY
LATCH
HVOUT8
L/T
LE
SEL
LE
Note: BL, SEL, and LE have internal 20kΩ pull-up resistors.
4
HV514
Function Table
Inputs
Outputs
Function
HV Output
Shift Reg
2....16
Action
2....16
Data CLK /LE SEL /BL
1
Latch
1
Data Out
Load S/R
H or L
H or L *…*
H or L *…*
*
*…*
*
*
*
*
*…*
*…*
*…*
*…*
*
X
X
X
X
X
X
H
H
L
H
L
To data
*
*
*
Transfer S/R
to Latch
H or L *…* To polarity
Hold latch data
Blank Output
*
*
*…*
*…*
*
*
*…*
*…*
1 (XNOR )
POL
X
X
X
X
X
X
X
X
L
*
*
Data (XNOR )
POL
Active Output
H
*
*…*
*
*…*
Latched Information
/BL
HV Output
Data
X
Polarity
L
L
H
L
L
H
L
L
X
H
H
H
H
L
H
L
H
H
L
L
H
H
H
Notes:
H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition
• = dependent on previous stage’s satte before the last CLK or last LE* high.
5
HV514
Pin Configuration
Package Outline
Pin
1
2
3
4
5
6
7
8
Function
1
2
20
19
18
17
16
15
14
13
12
11
CLK
LE
DIN
3
4
LGND
HVGND
HVGND
HVout1
HVout2
HVout3
HVout4
HVout5
HVout6
HVout7
HVout8
VPP
5
6
7
8
9
9
10
10
11
12
13
14
15
16
17
18
19
20
20-Lead SOW Package (WG)
WIde Body
VPP
VDD
DOUT
BL
SEL
08/08/03
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 222-8888 • FAX: (408) 222-4895
www.supertex.com
©2003 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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