HV518P-G [SUPERTEX]
32-Channel Vacuum-Fluorescent Display Driver; 32通道真空荧光显示驱动器
| 型号： | HV518P-G |
| 厂家： | 
Supertex, Inc |
| 描述： | 32-Channel Vacuum-Fluorescent Display Driver |
| 文件： | 总8页 (文件大小：768K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV518
32-Channel Vacuum-Fluorescent
Display Driver
Features
General Description
The HV518 is designed for vacuum fluorescent or DC plasma
applications, where it can serve as a segment, digit or matrix
display driver. Each device has 32 outputs, 32 latches and a
32-bit cascadable shift register.
► 32 output lines
► 90V output swing
► Active pull-down
► Latches on all outputs
► Up to 6MHz @ VDD = 5.0V
► -40°C to +85°C operation
Serial data enters the shift register on the LOW-to-HIGH
transition of the clock input. With latch enable (LE) HIGH,
parallel data is transferred to the output buffers through a
32-bit latch. When LE is low the data is stored in the latch.
When STROBE is LOW, all outputs are enabled; if STROBE
is HIGH, all outputs are LOW.
Applications
► Vacuum flourescent displays
► DC plasma displays
Block Diagram
LE
STB
VPP
HVOUT1
DIN
32-Bit
Shift
Register
Latches
CLK
DOUT
HVOUT32
1
HV518
Pin Configurations
Ordering Information
21
40
Package Options
40-Lead PDIP 44-Lead PLCC
HV518P-G HV518PJ-G
Device
HV518
-G indicates package is RoHS compliant (‘Green’)
20
1
40-Lead PDIP (P)
(top view)
39 38 37 36 35 34 33 32 31 30 29
28
27
26
25
24
23
22
21
20
19
18
40
41
42
43
44
1
Absolute Maximum Ratings
Parameter
Supply voltage, VDD
2
Value
3
4
-0.5V to +6.0V
-0.5V to +90V
-0.5V to VDD+0.5V
1200mW
5
Supply voltage, VPP
6
7
8
9 10 11 12 13 14 15 16 17
Logic input levels
Continuous total power dissipation(1,2)
Operating temperature
Storage temperature
44-Lead PLCC (PJ)
(top view)
-40°C to +85°C
-65°C to +150°C
260°C
Soldering temperature(3)
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to GND.
Product Markings
Top Marking
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
YYWW
HV518P
L L L L L L L L L L
Notes:
(1) Duty cycle is limited by the total power dissipated in the package.
(2) For operation above 25OC ambient, derate linearly to 85OC at 20mW/OC.
(3) Distance of 1.6mm from case for 10 seconds.
Bottom Marking
CCCCCCCCCCC
AAA
40-Lead PDIP (P)
Top Marking
YY = Year Sealed
WW = Week Sealed
L = Lot Number
YYWW
HV518PJ
LLLLLLLLLL
C = Country of Origin*
A = Assembler ID*
Bottom Marking
= “Green” Packaging
CCCCCCCCCCC
AAA
*May be part of top marking
44-Lead PLCC (PJ)
2
HV518
Recommended Operating Conditions(TA = 25°C, unless otherwise noted)
Sym Parameter
Min
4.5
8.0
3.5
-
Max
5.5
80
-
Unit
Conditions
VDD
VPP
VIH
VIL
Logic supply voltage
V
---
High voltage supply
V
---
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
VDD = 4.5V, See Figure 3
1.0
-
V
VDD = 4.5V, See Figure 3
IOH
-25
-
mA
mA
MHz
ns
ns
ns
ns
°C
---
IOL
2.0
6.0
-
---
fCLK
-
VDD = 4.5V, See Figure 3
VDD = 4.5V
VDD = 4.5V
VDD = 4.5V
VDD = 4.5V
---
tw(CKH) Pulse duration, clock high
tw(CKL) Pulse duration, clock low
83
83
75
75
-40
-
tsu
th
Setup time, data before clock
Hold time, data after clock
Operating free-air temperature
-
-
TA
85
Electrical Characteristics
(over recommended ranges of operating free-air temperature and VDD. Unless otherwise noted, VPP = 80V)
Sym
Parameter
Min
Typ
Max
10
Units
mA
mA
µA
Conditions
IDD
IDDQ
IPPQ
Supply current
-
-
-
VDD = 5.0V, fCH = 6.0 MHz
VDD = 5.5V, VIN = 0V
---
Quiescent supply current
Quiescent supply current
-
-
0.5
100
-
-
HV output
70
4.5
-
-
IOH = -25mA
HVIN operating
current
VOH
VOL
V
V
Serial output
HV output
4.9
-
5.0
5.0
0.8
1.0
-1.0
VDD = 5.0V, IOH = -20µA
IOL = 1.0mA
LVIN operating
current
Serial output
-
0.06
0.1
-0.1
IOL = 20µA
VIH = VDD
VIL = 0V
IIH
IIL
Logic input current high
Logic input current low
-
µA
µA
-
Note: The total number of ON outputs times the duty cycle must not exceed the allowable package power disspation.
Switching Characteristics(VPP = 80V, CL = 50pF, TA = 25°C, unless otherwise noted)
Sym Parameter
Max
600
1.5
Unit
Conditions
td
Delay time, clock to data output
ns
VDD = 4.5V, CL = 15pF, See Figure 1
VDD = 4.5V, See Figure 2
Turn-on time when
high voltage is
enabled
from latch enable
from strobe
tDHL
µs
µs
1.0
1.5
VDD = 4.5V, See Figure 3
VDD = 4.5V, See Figure 2
Delay time,
high-to-low-level,
HV output
from latch enable
from strobe
tDLH
1.0
3.0
2.5
VDD = 4.5V, See Figure 3
VDD = 4.5V, See Figure 3
VDD = 4.5V, See Figure 3
tTHL
tTLH
Transition time, high-to-low-level, HV output
Transition time, low-to-high-level, HV output
µs
µs
3
HV518
Power-Up/ Power-Down Sequences
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply VPP.
5. The VPP should not drop below VDD or float during operation.
Power-down sequence should be the reverse of the above.
Input and Output Equivalent Circuits
VDD
VDD
VPP
DATA
OUT
HVOUT
INPUT
GND
GND
GND
Parameter Measurement Information
t
w(CKH)
t
w(CKH)
V
IH
V
IH
Clock
50%
Clock
50%
V
IL
V
IL
t
w(CKL)
t
t
d
t
su
h
V
OH
V
V
Data
Output
IH
IL
50%
Data In
V
OL
Figure 1
Input Timing Voltage Waveforms
V
IH
V
V
50%
t
IH
IL
Strobe
Latch Enable
HV Output
50%
V
IL
t
DLH
DHL
t
or t
DHL
V
DLH
OH
90%
10%
HV Output
V
V
OH
OL
90%
10%
V
OL
t
t
THL
TLH
Figure 3: Input Timing Voltage Waveforms
Figure 2
Note: For testing purposes, all input pulses have maximum rise and fall times of 30 nsec.
4
HV518
Truth Tables
Output
Input
Data In
LE
X
STB
H
HV Outputs
Data In
CLK
Data Out
X
All Low
High
Low
*
H
H
L
*
H
H
H
L
L
L
X
L
X
L
No Change
* Previous state.
L
* Previous state.
Typical Operating Sequence
Clock
● ● ●
Data In
VALID
IRRELEVANT
VALID
SR Contents
INVALID
Latch Enable
Latch
PREVIOUSLY STORED DATA
NEW DATA VALID
Contents
Strobe
HV Output
VALID
5
HV518
Pin Descriptions
40-Lead PDIP (P)
Pin
Function
Pin
Function
Pin
Function
1
2
VPP
15
16
17
18
19
20
21
22
23
24
25
26
27
28
HVOUT20
HVOUT19
HVOUT18
HVOUT17
Strobe
29
30
31
32
33
34
35
36
37
38
39
40
HVOUT10
HVOUT9
HVOUT8
HVOUT7
HVOUT6
HVOUT5
HVOUT4
HVOUT3
HVOUT2
HVOUT1
Data In
Serial Out
HVOUT32
HVOUT31
HVOUT30
HVOUT29
HVOUT28
HVOUT27
HVOUT26
HVOUT25
HVOUT24
HVOUT23
HVOUT22
HVOUT21
3
4
5
6
GND
7
Clock
8
LE
9
HVOUT16
HVOUT15
HVOUT14
HVOUT13
HVOUT12
HVOUT11
10
11
12
13
14
VDD
44-Lead PLCC (PJ)
Pin
Function
Pin
Function
Pin
Function
1
2
VPP
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
HVOUT20
HVOUT19
N/C
31
32
33
34
35
36
37
38
39
40
41
42
43
44
HVOUT12
HVOUT11
HVOUT10
HVOUT9
HVOUT8
HVOUT7
HVOUT6
HVOUT5
HVOUT4
HVOUT3
HVOUT2
HVOUT1
Data In
Serial Out
HVOUT32
HVOUT31
HVOUT30
NC
3
4
HVOUT18
HVOUT17
Strobe
5
6
7
HVOUT29
HVOUT28
HVOUT27
HVOUT26
HVOUT25
HVOUT24
HVOUT23
HVOUT22
HVOUT21
GND
8
Clock
9
LE
10
11
12
13
14
15
HVOUT16
HVOUT15
HVOUT14
N/C
N/C
VDD
HVOUT13
6
HV518
40-Lead PDIP (.600in Row Spacing) Package Outline (P)
D
40
E1
E
Note 1
(Index Area)
B1
1
D1
D1
A2
B
Top View
View B
A
View B
Seating
Plane
A
A1
L
eA
eB
e
A
Front View
View AA
Note 1:
A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol
A
.140
-
A1
.015
-
A2
.125
-
eA
B
.014
-
B1
.030
-
eB
.600
-
D
1.980
-
D1
.005
-
E
.600
-
E1
0.485
-
e
L
.115
-
MIN
NOM
MAX
Dimension
(inches)
.600
BSC
.100
BSC
.250
.125
.195
.022
.070
.700
2.095
.625
.625
0.580
.200
JEDEC Registration MS-011, Variation AC, Issue B, June, 1988.
Drawings not to scale.
7
HV518
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max.), .050in pitch
D
D1
1
.048/.042
.056/.042
x 45O
O
x 45
6
44
40
.150 MAX
Note 1
(Index Area)
.075 MAX
E1
E
Note 2
(3 places)
0.20max
3 Places
Top View
Side View
View B
b1
.020 MIN
Base
Plane
A
A2
Seating
Plane
e
A1
b
Side View
View B
Note:
1. A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
2. Exact shape of this feature is optional.
Symbol
A
A1
A2
.062
-
b
.013
-
b1
.026
-
D
D1
E
E1
e
MIN
NOM
MAX
.165
.172
.180
.090
.105
.120
.685
.690
.695
.650
.653
.656
.685
.690
.695
.650
.653
.656
Dimension
(inches)
.050
BSC
.083
.021
.036
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
Drawings are not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV518
A091007
8
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