VND5025B1K-E [STMICROELECTRONICS]
2 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO24, ROHS COMPLIANT, SSOP-24;
| 型号： | VND5025B1K-E |
| 厂家： | 
ST |
| 描述： | 2 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO24, ROHS COMPLIANT, SSOP-24 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总32页 (文件大小：479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5025BK-E
Double channel high-side driver with analog current sense
for automotive applications
Features
Max transient supply voltage
Operating voltage range
VCC
41 V
VCC 4.5 to 36 V
PowerSSO-24™
Max on-state resistance (per ch.) RON
25 mΩ
60 A
2 µA(1)
– Electrostatic discharge protection
Current limitation (typ)
Off-state supply current
ILIMH
IS
Description
1. Typical value with all loads connected.
The VND5025BK-E s a monolithic device made
using STMicroeectronics™ VIPower™ M0-5
technology, intended for driving resistive or
inductive loads with one side connected to
ground, and suitable for driving LEDs.
■ Features
– In-rush current active management by
power limitation
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
Active V pin voltage clamp protects the device
CC
against low energy spikes (see ISO7637 transient
compatibility table). This device integrates an
analog current sense which delivers a current
proportional to the load current (according to a
known ratio) when CS_DIS is driven low or left
open. When CS_DIS is driven high, the
CURRENT SENSE pin is in a high impedance
condition.
– Two classes with different ‘K@3A’ ranges
– Package: ECOPACK®
■ Diagnostic functis
– 3 A current sense precision of +/-8%
– Proportional load current sense
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
– High current sense precision for wide range
crrents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
■ Protection
Table 1.
Package
Device summary
Order codes
– Undervoltage shutdown
– Overvoltage clamp
Tube
Tape and reel
– Load current limitation
– Self-limiting of fast thermal transients
– Protection against loss of ground and loss
VND5025BKTR-E
VND5025B1KTR-E
VND5025B2KTR-E
VND5025BK-E
VND5025B1K-E
PowerSSO-24™
of V
VND5025B2K-E
CC
– Thermal shutdown
– Reverse battery protection
August 2010
Doc ID 13374 Rev 6
1/32
www.st.com
1
Contents
VND5025BK-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . 22
3.1.1
3.1.2
Solution 1: resistor in the ground line (RGNonly) . . . . . . . . . . . . . . . . 22
Solution 2: diode (DGND) in the ground ine . . . . . . . . . . . . . . . . . . . . . 23
3.2
3.3
3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Maximum demagnetization ergy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 24
4
5
Package and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1
PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package ad packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
5.2
5.3
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
Doc ID 13374 Rev 6
VND5025BK-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (V = 13V; T = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
j
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current sense (8 V < V < 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical transient requirements (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 13374 Rev 6
3/32
List of figures
VND5025BK-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay response time between rising edge of output current and rising edge of current sense
(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6.
Figure 7.
Figure 8.
Figure 9.
I
/I
vs I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT SENSE
OUT
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. On-state resistance vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
case
Figure 18. On-state resistance vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CC
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20.
I
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LIMH
case
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 24. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 26. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. Maximum turn-ocurrent versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 24
Figure 28. PowerSSO-2™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 25
Figure 30. PowerSSO-24™ thermal impedance junction to ambient single pulse (one channel ON) . 26
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 26
Figure 32. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3. PowerSSO-24™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Fgure 34. PowerSSO-24™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/32
Doc ID 13374 Rev 6
VND5025BK-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
V
CC
UNDERVOLTAGE
PwCLAMP 1
V
CC
CLAMP
OUTPUT1
CURRENT
SENSE1
GND
DRIVER 1
I
1
PwCLAMP 2
LIM
INPUT1
DRIVER 2
V
1
LOGIC
OUTPUT2
DSLIM
Pwr
1
LIM
I
2
LIM
CURRENT
SENSE2
OVERTEMP. 1
K 1
V
2
DSLIM
INPUT2
CS_DIS
I
OUT1
OVERTEMP. 2
K 2
I
OUT2
Pwr
2
LIM
Table 2.
Pin functions
Name
Function
VCC
Battery connection.
Power output.
OUTPUT1,2
GND
Ground connection; must be reverse battery protected by an external
diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible; controls
output switch state.
INPU2
Analog current sense pin; delivers a current proportional to the load
current.
CURRENT SENSE1,2
CS_DIS
Active high CMOS compatible pin to disable the current sense pin.
Doc ID 13374 Rev 6
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Block diagram and pin description
VND5025BK-E
Figure 2.
Configuration diagram (top view)
V
CC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
9
10
11
12
CS_DIS.
V
CC
TAB = V
CC
Table 3.
Suggested connections for unused and not cnnected pins
Connection / pin
Current sense
N.C.
Output
Input
CS_DIS
Floating
N.R.(1)
X
X
X
X
Through 10kΩ Through 10kΩ
resistor resistor
To Ground
Through 1kΩ resistor
X
N.R.
1. Not recommended.
6/32
Doc ID 13374 Rev 6
VND5025BK-E
Electrical specification
2
Electrical specification
Figure 3.
Current and voltage conventions
IS
VCC
VF
VCC
IOUT1
ISENSE1
IOUT2
ICSD
IIN1
IIN2
OUTPUT1
CS_DIS
INPUT1
INPUT2
VOUT1
VCSD
CURRENT
SENSE1
VSENSE1
VIN1
OUTPUT2
ISENSE2
VOUT2
VIN2
CURRENT
SENSE2
GND
VSENSE2
IGND
Note: V = V
- V during reverse battery condition.
CC
Fn
OUTn
2.1
Absolute maximum rating
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affedevice reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Tale 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
-VCC
-IGND
IOUT
- IOUT
IIN
DC supply voltage
41
V
mA
A
Reverse DC supply voltage
DC reverse ground pin current
DC output current
0.3
200
Internally limited
24
Reverse DC output current
DC input current
-1 to 10
ICSD
DC current sense disable input current
mA
V
-ICSENSE DC reverse CS pin current
200
VCSENSE Current sense maximum voltage
VCC - 41 to +VCC
Doc ID 13374 Rev 6
7/32
Electrical specification
VND5025BK-E
Table 4.
Symbol
Absolute maximum ratings (continued)
Parameter
Value
Unit
Maximum switching energy (single pulse)
(1)
EMAX
109
mJ
(L = 0.3 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C;
IOUT = IlimL(Typ.))
Electrostatic discharge
(Human Body Model: R = 1.5 kΩ; C = 100 pF)
- Input
4000
2000
4000
5000
5000
V
V
V
V
V
VESD
- Current sense
- CS_DIS
- Output
- VCC
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
Tstg
1. See Section 3.4 for details.
2.2
Thermal data
Table 5.
Symbol
Thermal data
Paramter
Maximum value Unit
Rthj-case Thermal resistance junction-case (with one channel ON)
Rthj-amb Thermal resistance junction-ambient
1.35
°C/W
See Figure 29
8/32
Doc ID 13374 Rev 6
VND5025BK-E
Electrical specification
2.3
Electrical characteristics
8 V < V < 36 V; -40 °C < T < 150 °C, unless otherwise specified.
CC
j
Table 6.
Power section
Parameter
Symbol
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
Undervoltage shutdown
4.5
13
36
VUSD
3.5
4.5
V
Undervoltage shut-down
hysteresis
VUSDhyst
0.5
IOUT = 3 A; Tj = 25 °C
IOUT = 3 A; Tj = 150 °C
OUT = 3 A; VCC = 5 V; Tj = 25 °C
25
50
35
52
RON
On-state resistance(1)
mΩ
I
Vclamp Clamp voltage
IS = 20 mA
4
46
V
Off-state; VCC = 13 V; Tj = 25 °C;
2(2)
5(2)
µA
VIN = VOUT = VSENSE = VCSD 0 V
IS
Supply current
On-state; VCC = 13 V;
VIN = 5 V; IOUT = 0
3
6
mA
µA
V
VIN = VOUT = 0
0
0
0.01
3
VCC = 1; Tj = 25 °C
IL(off)
Off-state output current(1)
VIN OUT = 0 V;
5
VCC = 13 V; Tj = 125 °C
Output - VCC diode
voltage(1)
VF
-IOUT = 4 A; Tj = 150 °C
0.7
1. For each channel.
2. PowerMOS leake included.
Table 7.
Symbol
Switching (V = 13V; T = 25 °C)
CC j
Parameter
Test conditions Min.
Typ.
35
Max. Unit
td(on)
td(off)
Turn-on delay time
Turn-off delay time
—
—
µs
—
RL = 4.3 Ω
(see Figure 8)
—
50
(dVOUT/dt)on Turn-on voltage slope
(dVOUT/dt)off Turn-off voltage slope
—
See Figure 21
See Figure 22
—
RL = 4.3 Ω
V/µs
—
—
Switching energy losses
WON
—
0.45
0.35
—
during tW
ON
RL = 4.3 Ω
(see Figure 8)
mJ
—
Switching energy losses
WOFF
—
during tW
OFF
Doc ID 13374 Rev 6
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Electrical specification
VND5025BK-E
Table 8.
Symbol
Logic input
Parameter
Test conditions
Min. Typ. Max. Unit
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
0.9
V
µA
V
VIN = 0.9 V
VIN = 2.1 V
1
VIH
2.1
IIH
10
7
µA
VI(hyst)
0.25
5.5
I
I
IN = 1 mA
IN = -1 mA
VICL
Input clamp voltage
V
-0.7
VCSDL
ICSDL
VCSDH
ICSDH
CS_DIS low level voltage
Low level CS_DIS current
CS_DIS high level voltage
High level CS_DIS current
0.9
VCSD = 0.9 V
VCSD = 2.1 V
1
µA
V
2.1
10
7
µA
VCSD(hyst) CS_DIS hysteresis voltage
0.25
5.5
I
CSD = 1 mA
V
VCSCL
CS_DIS clamp voltage
ICSD = -1 mA
-0.7
(
Table 9.
Symbol
Protection and diagnoss
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
CC = 13 V
43
60
ILIMH
DC short circuit current
85
5 V < VCC < 36 V
A
Shorcircuit current
durinthermal cycling
VCC = 13 V;
TR < Tj < TTSD
ILIML
24
TTS
TR
Shutdown temperature
Reset temperature
150
175
200
TRS + 1 TRS + 5
135
°C
TRS
Thermal reset of STATUS
Thermal hysteresis
(TTSD-TR)
THYST
7
Turn-off output voltage
clamp
IOUT = 2 A;
VIN = 0; L = 6 mH
VDEMAG
VCC - 41 VCC - 46 VCC - 52
V
IOUT = 0.2 A
Tj = -40 °C to 150 °C
(see Figure 9)
Output voltage drop
limitation
VON
40
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/32
Doc ID 13374 Rev 6
VND5025BK-E
Electrical specification
Table 10. Current sense (8 V < V < 16 V)
CC
Symbol
Parameter
IOUT/ISENSE
IOUT/ISENSE
Test conditions
Min. Typ. Max. Unit
IOUT = 0.05 A; VSENSE = 0.5 V;
VCSD = 0 V; Tj = -40 °C to 150 °C
KLED
1740 3300 4570
IOUT = 0.5 A; VSENSE = 0.5 V;
VCSD = 0 V; Tj = -40 °C to 150 °C
K0
K1
1920 3020 3930
IOUT = 2 A; VSENSE = 4 V;
VCSD = 0 V;
IOUT SENSE
/I
Tj = -40 °C
2090 2810 3440
2320 2810 3200
Tj = 25 °C to 150 °C
IOUT = 2 A; VSENSE = 4 V;
VCSD = 0 V;
Current sense
ratio drift
(1)(2)
dK1/K1
-8
+8
%
Tj = -40 °C to 150 °C
IOUT = 3 A; VSENSE = 4 V;
VCSD = 0 V;
Tj = -40 °C to 150 °C
ClassB
K2
IOUT/ISENSE
2510
2510
2690
3160
2960
3160
ClassB1
ClassB2
IOUT = 3 A; VSENSE = 4 V; VCSD = 0 V;
Tj = -40 °C to 0 °C
Current sense
ratio drift
(1)(2)
dK2/K2
-6
+6
%
IOUT = 10 A; VSENSE = 4 V;
VCSD = 0 V;
K3
IOUT/ISENSE
Tj = -40 °C
2610 2760 2970
2650 2760 2870
Tj = 25 °C to 150 °C
IOUT = 10 A; VSENSE = 4 V; VCSD = 0 V;
Tj = -40 °C to 150 °C
Curent sense
ratidrift
(1)(2)
dK3/K3
-3
0
+3
1
%
IOUT = 0 A; VSENSE = 0 V; VCSD = 5 V;
VIN = 0 V; Tj = -40 °C to 150 °C
µA
µA
µA
Analog sense
VCSD = 0 V; VIN = 5 V;
leakage current Tj = -40 °C to 150 °C
ISENSE0
0
2
I
OUT = 2 A; VSENSE = 0 V; VCSD = 5 V;
0
1
VIN = 5 V; Tj = -40 °C to 150 °C
Max analog
Sense output
voltage
VSENSE
IOUT = 3 A; VCSD = 0 V
5
V
Analog sense
output voltage in
overtemperature
condition
VSENSEH
VCC = 13 V; RSENSE = 3.9 kΩ
9
8
Analog sense
output current in
overtemperature
condition
ISENSEH
VCC = 13 V; VSENSE = 5 V
mA
Doc ID 13374 Rev 6
11/32
Electrical specification
VND5025BK-E
Table 10. Current sense (8 V < V < 16 V) (continued)
CC
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Delay response
time from falling
edge of CS_DIS
pin
V
SENSE < 4 V, 0.5 < IOUT < 10 A
ISENSE = 90 % of ISENSEMAX
tDSENSE1H
50
5
100
20
(see Figure 4)
Delay response
time from rising
edge of CS_DIS
pin
VSENSE < 4 V, 0.5 < IOUT < 10 A
ISENSE = 10 % of ISENSEMAX
tDSENSE1L
(see Figure 4)
Delay response
time from rising
edge of INPUT
pin
V
SENSE < 4 V, 0.5 < IOUT < 10 A
ISENSE = 90 % of ISENSEMAX
tDSENSE2H
70
300
µs
(see Figure 4)
Delay response
time between
rising edge of
output current
VSENSE < 4 V,
ISENSE = 90 % of ISENSEMAX,
IOUT = 90 % of IOUTMAX, IOUTMAX A
ΔtDSENSE2H
110
and rising edge (see Figure 5)
of current sense
Delay response
VSENSE < 4 V, 0.5 < IUT < 10 A
ISENSE = 10 % of ISENSEMAX
time from falling
edge of INPUT
pin
tDSENSE2L
100 250
(see Figure 4
1. Parameter guaranteed by design; it is not tested.
2. Current sense ratio drift is the deviation of factor K for a given device (measured over the range -40 °C to
150 °C and 8 V < VCC < 16 V) from its value measured at Tj = 25 °C, VCC = 13 V.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
12/32
Doc ID 13374 Rev 6
VND5025BK-E
Electrical specification
Figure 5.
Delay response time between rising edge of output current and rising
edge of current sense (CS enabled)
V
IN
Δt
DSENSE2H
t
t
t
I
OUT
I
OUTMAX
90% I
OUTMAX
I
SENSE
I
SENSEMAX
90
SENSEMAX
Doc ID 13374 Rev 6
13/32
Electrical specification
Figure 6.
VND5025BK-E
I
/I
vs I
OUT SENSE OUT
Iout/Isense
3400
Max, Tj = -40 °C to 150 °C
3200
3000
2800
2600
2400
2200
2000
Class B
Min, Tj = -40 °C to 150 °C
2
4
6
8
10
Iout [A]
Iout/Isense
3400
3200
3000
2800
2600
2400
2200
Max, Tj = -40 °C to 15
Class B1
Min, Tj = -40 °C to 150 °C
2000
2
4
6
8
10
Iout [A]
Iout/Isense
3400
3200
3000
2800
2600
2400
2200
Max, Tj = -40 °C to 150 °C
Class B2
Min, Tj = -40 °C to 150 °C
2000
2
4
6
8
10
Iout [A]
Note: See Table 10 for details.
14/32
Doc ID 13374 Rev 6
VND5025BK-E
Electrical specification
Figure 7.
Maximum current sense ratio drift vs load current
dK/K [%]
10
8
6
Max, Tj = -40 °C to 150 °C
4
2
0
-2
-4
-6
-8
-10
Min, Tj = -40 °C to 150 °C
2
3
4
5
6
7
8
9
10
Iout [A]
Note: Parameter guaranteed by design; it is not tested.
Table 11.
Truth table
Conditions
Input
Output
Sense (VCSD = 0 V)(1)
L
H
L
L
0
Normal operation
H
Nominal
0
Overtemperae
Undervoltage
L
L
H
L
VSENSEH
0
H
L
0
Short circuit to GND (RSC ≤ 10mΩ)
L
0 if Tj < TTSD
H
VSENSEH if Tj > TTSD
L
H
L
0
< Nominal
0
Short circuit to VCC
H
L
Negative output voltage clamp
1. If the VCSD is high, the SENSE output is at a high impedance; its potential depends on leakage currents
and external circuit.
Doc ID 13374 Rev 6
15/32
Electrical specification
Figure 8.
VND5025BK-E
Switching characteristics
t
t
V
Woff
Won
OUT
90%
80%
dV
/dt
dV
/dt
OUT (off)
OUT (on)
t
t
10%
r
f
t
INPUT
t
t
d(on)
d(off)
t
Figure 9.
Output voltage drop limitation
V
- V
CC
T = 150 °C
j
T = 25 °C
j
T = -40 °C
j
V
on
I
OUT
V
/R
on on(T)
16/32
Doc ID 13374 Rev 6
VND5025BK-E
Electrical specification
Table 12. Electrical transient requirements (part 1/3)
Burst cycle/pulse
repetition time
Test levels(1)
ISO 7637-2:
2004(E)
Test pulse
Number of
pulses or
test times
Delays and
Impedance
III
IV
Min.
Max.
5s
1
2a
3a
3b
4
-75V
+37V
-100V
+75V
-6V
-100V
+50V
-150V
+100V
-7V
5000 pulses
5000 pulses
1h
0.5s
0.2s
2 ms, 10Ω
50µs, 2Ω
5s
90ms
90ms
100ms
100ms
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
1h
1 pulse
1 pulse
5b(2)
+65V
+87V
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 13. Electrical transient requirements (part 2/3)
ISO 7637-2:
2004E
Test level results
III
C
C
C
C
C
C
VI
C
C
C
C
C
C
Test pulse
1
2a
3a
3b
4
5b(1
1. alid in case of external load dump clamp: 40V maximum referred to ground.
Table 14. Electrical transient requirements (part 3/3)
Class
Contents
C
All functions of the device performed as designed after exposure to disturbance.
One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
Doc ID 13374 Rev 6
17/32
Electrical specification
VND5025BK-E
Figure 10. Waveforms
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
V
USDhyst
V
CC
V
USD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO V
CC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
< Nominal
< Nominal
OVERLOAD OPERATION
TTSD
TRS
TR
T
j
INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
SENSE CURRENT
VSENSEH
Thermal cycling
Current
limitation
Power
limitation
SHORTED LOAD
NORMAL LOAD
18/32
Doc ID 13374 Rev 6
VND5025BK-E
Electrical specification
2.4
Electrical characteristics curves
Figure 11. Off-state output current
Figure 12. High level input current
Iih(uA)
5
Iloff (uA)
0.5
4.5
4
0.45
Off State
Vcc=13V
Vin=Vout=0V
Vin=2.1V
0.4
0.35
0.3
3.5
3
2.5
2
0.25
0.2
1.5
1
0.15
0.1
0.5
0.05
0
0
-50
-25
0
25
50
75
0
125
150
175
-50
-25
0
25
50
75
100 125 150 175
Tc (°
Tc (°C)
Figure 13. Input clamp voltage
Figure 14. Input high level
Vicl (V)
7
Vih (V)
6.75
3.5
3
Iin=1mA
6.5
6.25
6
2.5
2
5.75
5.5
5.25
5
1.5
1
0.5
0
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 5. Input low level
Figure 16. Input hysteresis voltage
Vil (V)
2
Vhyst (V)
1
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Doc ID 13374 Rev 6
19/32
Electrical specification
VND5025BK-E
Figure 17. On-state resistance vs T
Figure 18. On-state resistance vs V
CC
case
Ron (mOhm)
100
Ron (mOhm)
80
90
70
60
50
40
30
20
10
0
Iout=3A
Vcc=13V
80
70
60
50
40
30
20
10
0
Tc=150°C
Tc= 125°C
Tc= 25°C
Tc= -40°C
-50
-25
0
25
50
75
100
125 150
175
0
5
10
15
20
25
30
35
40
Tc (°C)
Vcc (V)
Figure 19. Undervoltage shutdown
Figure 20. I
vs T
LIMH
ase
Ilimh (A)
100
Vusd (V)
16
90
80
70
60
50
40
30
20
10
0
14
12
10
8
Vcc=13V
6
4
2
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 21. Turn-on voltage slope
Figure 22. Turn-off voltage slope
(out/dt)on (V/ms)
1000
(dVout/dt)off (V/ms)
1000
900
900
Vcc=13V
Rl=4.3Ohm
Vcc=13V
Rl=4.3Ohm
800
800
700
700
600
500
400
300
200
100
0
600
500
400
300
200
100
0
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100 125 150 175
Tc (°C)
Tc (°C)
20/32
Doc ID 13374 Rev 6
VND5025BK-E
Electrical specification
Figure 23. CS_DIS high level voltage
Figure 24. CS_DIS low level voltage
Vcsdh (V)
4
Vcsdl (V)
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 25. CS_DIS clamp voltage
Vcsdcl (V)
8
7.5
Icsd=1mA
7
6.5
6
5.5
5
4.5
4
-50
-25
0
50
75
100
125
150
175
Tc (°C)
Doc ID 13374 Rev 6
21/32
Application information
VND5025BK-E
3
Application information
Figure 26. Application schematic
+5V
V
CC
R
prot
CS_DIS
D
ld
R
µC
INPUT
prot
OUTPUT
R
CURRENT SENSE
prot
GND
R
R
GND
SENSE
V
C
D
GND
EXT
GND
Note: Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1
Solution 1: rsistor in the ground line (R
only)
GND
This firt solution can be used with any type of load.
Thfollowing formulas indicate how to dimension the R
resistor:
GND
1.
2.
R
R
≤ 600 mV / (I
≥ (-V ) / (-I
)
S(on)max
GND
GND
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power Dissipation in R
(when V < 0 during reverse battery situations) is:
CC
GND
2
P = (-V ) / R
D
CC
GND
This resistor can be shared among several different HSDs. Please note that the value of this
resistor is calculated with formula (1), where I
state currents of the different devices.
becomes the sum of the maximum on-
S(on)max
Please note that if the microprocessor ground is not shared by the device ground, the R
GND
produces a shift (I
* R
) in the input thresholds and the status output values. This
S(on)max
GND
shift varies depending on how many devices are ON in the case of several high-side drivers
sharing the same R
.
GND
22/32
Doc ID 13374 Rev 6
VND5025BK-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor, then ST suggests to utilize the following Solution 2.
3.1.2
Solution 2: diode (D
) in the ground line
GND
If the device drives an inductive load, insert a resistor (R
= 1 kΩ) in parallel to D
.
GND
GND
This small signal diode can be safely shared among several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
ld
V
maximum DC rating. The same applies if the device is subject to trnsients on the V
CC
CC
line that are greater than the ones shown in the ISO 7637-2:2004E ble.
MCU I/Os protection
If a ground protection network is used and negae transients are present on the V line,
CC
the control pins are pulled negative. ST suggests to insert an in-line resistor (R ) to
prot
prevent the microcontroller I/O pins frlatch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-V
/I
≤ R
≤ (V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND IHmax
Calculation exale:
For V
= -100 V and I
≥ 20 mA; V
≥ 4.5 V
Cpeak
latchup
OHµC
5 kΩ ≤ R
≤ 65 kΩ
prot
Recommended values: R
= 10 kΩ, C
= 10 nF.
EXT
prot
Doc ID 13374 Rev 6
23/32
Application information
VND5025BK-E
3.4
Maximum demagnetization energy (VCC = 13.5 V)
Figure 27. Maximum turn-off current versus inductance (for each channel)
100
10
1
A
B
C
0,1
1
L (mH)
10
100
A:
T
= 150 °C single pulse
jstart
B: Tjstart = 100 °C repetitive pulse
C: = 125 °C repetitive pulse
T
jstart
VIN,
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R = 0 Ω. In case of repetitive pulses, T
pulse must not exceed the temperature specified above for curves A and B.
(at beginning of each demagnetization) of every
L
jstart
24/32
Doc ID 13374 Rev 6
VND5025BK-E
Package and thermal data
4
Package and thermal data
4.1
PowerSSO-24™ thermal data
Figure 28. PowerSSO-24™ PC board
Note:
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 area = mm x 86 mm, PCB
thickness = 1.6 mm, Cu thickness = 70 µm (front and back side), Copper areas: from imum pad layout to 8 cm ).
th
th
2
Figure 29. R
vs PCB copper area in open ox free air condition (one channel
thj-amb
ON)
RTHj_amb(°C/W)
55
50
5
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Doc ID 13374 Rev 6
25/32
Package and thermal data
VND5025BK-E
Figure 30. PowerSSO-24™ thermal impedance junction to ambient single pulse (one
channel ON)
ZTH (°C/W)
1000
100
10
1
Footprint
2 cm2
8 cm2
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Equation 1: pulse calculation formula
= R ⋅ δ + Z (1 – δ)
Z
THδ
TH
THtp
where δ = t /T
P
Figure 1. Thermal fitting model of a double channel HSD in PowerSSO-24™
Note: Values are given inTable 11.
26/32
Doc ID 13374 Rev 6
VND5025BK-E
Package and thermal data
Table 15. Thermal parameters
Area/Island (cm2)
Footprint
0.28
0.9
2
8
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
R7 (°C/W)
0.28
0.9
R8 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
C7 (W.s/°C)
C8 (W.s/°C)
0.001
0.003
0.025
0.75
1
4
5
9
2.2
17
0.001
0.003
Doc ID 13374 Rev 6
27/32
Package and packing information
VND5025BK-E
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
5.2
Package mechanical data
Figure 32. PowerSSO-24™ package dimensions
28/32
Doc ID 13374 Rev 6
VND5025BK-E
Package and packing information
Table 16. PowerSSO-24™ mechanical data
Millimeters
Typ
Symbol
Min
Max
2.45
2.35
0.1
A
A2
a1
b
2.15
0
0.33
0.23
10.10
7.4
0.51
0.32
10.50
7.6
c
D
E
e
0.8
8.8
2.
e3
F
G
H
h
0.1
10.5
0.4
10.1
k
0°
8°
L
0.55
0.85
O
Q
S
T
1.2
0.8
2.9
3.65
1.0
U
N
X
Y
10°
4.7
7.1
4.1
6.5
Doc ID 13374 Rev 6
29/32
Package and packing information
VND5025BK-E
5.3
Packing information
Figure 33. PowerSSO-24™ tube shipment (no suffix)
Base Qty
Bulk Qty
49
1225
532
3.5
Tube length (±0.5)
C
A
B
B
13.8
0.6
C (±0.1)
All dimensions are in mm.
A
Figure 34. PowerSSO-24™ tape and reel shipment (suffix “TR”)
REEL DIMENSNS
Bse Qty
Bulk Qty
A (max)
B (min)
C (±0.2)
F
1000
1000
330
1.5
13
20.2
24.4
100
30.4
G (+2 / -0)
N (min)
T (max)
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hopacing
mponent Spacing
Hole Diameter
P0 (±0.1)
P
12
D (±0.05)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
1.55
1.5
11.5
2.85
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
30/32
Doc ID 13374 Rev 6
VND5025BK-E
Revision history
6
Revision history
Table 17. Document revision history
Date
Revision
Changes
28-Mar-2007
02-Jul-2009
1
2
Initial release
Updated Table 16: PowerSSO-24™ mechanical data
Updated Figure 32: PowerSSO-24™ package dimensions.
Updated Table 16: PowerSSO-24™ mechanical data:
– Deleted G1 row
23-Jul-2009
08-Feb-2010
22-Jul-2010
3
4
5
– Added O, Q, S, T and U rows
Updated ILIMH value from 41 A to 60 A
Updated Table 1: Device summary.
Table 10: Current sense (8 V < VCC < 16 V):
– Updated K2 values and test conditions.
Updated Figure 6: IOUT/ISENSE vs IOUT
Table 10: Current sense (8 V < CC < 16 V):
05-Aug-2010
6
– Updated K1 minimum vae at Tj = 25 °C to 150 °C
Doc ID 13374 Rev 6
31/32
VND5025BK-E
Please Read Carefully:
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Doc ID 13374 Rev 6
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