VND5050AKTR-E [STMICROELECTRONICS]
Double channel high side driver with analog current sense for automotive applications; 具有模拟电流检测用于汽车应用的双通道高侧驱动器
| 型号： | VND5050AKTR-E |
| 厂家： | 
ST |
| 描述： | Double channel high side driver with analog current sense for automotive applications |
| 文件： | 总26页 (文件大小：766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5050AJ-E
VND5050AK-E
Double channel high side driver with analog current sense
for automotive applications
Features
General
Max supply voltage
VCC
41V
PowerSSO-12 PowerSSO-24
Operating voltage range
VCC 4.5 to 36V
Max On-State resistance (per ch.) RON
50 mΩ
18 A
2 µA(*)
■ Self limiting of fast thermal transients
■ Protection against loss of ground and loss of
Current limitation (typ)
Off state supply current
ILIMH
IS
V
CC
■ Thermal shut down
(*) Typical value with all loads connected
■ Reverse battery protection (see Figure 24)
■ Electrostatic discharge protection
Application
■
All types of resistive, inductive and capacitive loads
■ Suitable as LED driver
Description
Main
The VND5050AJ-E, VND5050AK-E is a monolithic
device made using STMicroelectronics VIPower
M0-5 technology. It is intended for driving resistive
or inductive loads with one side connected to
ground. Active VCC pin voltage clamp protects the
device against low energy spikes (see ISO7637
transient compatibility table).
■ Inrush current active management by power
limitation
■ Very low stand-by current
■ 3.0V CMOS compatible input
■ Optimized electromagnetic emission
■ Very low electromagnetic susceptibility
■ In compliance with the 2002/95/ec european
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open.
directive
Diagnostic Functions
■ Proportional load current sense
■ High current sense precision for wide range
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
currents
■ Current sense disable
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears..
■ Thermal shutdown indication
■ Very low current sense leakage
Protections
■ Undervoltage shut-down
■ Overvoltage clamp
■ Load current limitation
Order codes
Package
Part number (Tube)
VND5050AJ-E
Part number (Tape & Reel)
PowerSSO-12
PowerSSO-24
VND5050AJTR-E
VND5050AKTR-E
VND5050AK-E
April 2006
Rev 2
1/26
www.st.com
26
Contents
VND5050AJ-E / VND5050AK-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
2.4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 15
3.1.1
3.1.2
Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
3.3
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
µC I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
5
6
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
4.2
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
5.2
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
VND5050AJ-E / VND5050AK-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block Diagram
V
CC
UNDERVOLTAGE
V
CC
CLAMP
OUTPUT1
PwCLAMP 1
CURRENT
SENSE1
GND
DRIVER 1
I
1
LIM
PwCLAMP 2
OUTPUT2
INPUT1
DRIVER 2
V
1
LOGIC
DSLIM
Pwr
1
LIM
I
2
LIM
CURRENT
SENSE2
OVERTEMP. 1
K 1
V
2
DSLIM
INPUT2
I
OUT1
OVERTEMP. 2
K 2
I
OUT2
Pwr
2
LIM
CS_DIS
Table 1.
Name
Pin Function
Function
VCC
OUTPUT1,2
GND
Battery connection
Power output
Ground connection. Must be reverse battery protected by an external diode/resistor network
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state
INPUT1,2
CURRENT
SENSE1,2
Analog current sense pin, delivers a current proportional to the load current
Active high CMOS compatible pin, to disable the current sense pin
CS_DIS
Figure 2. Configuration diagram (top view) & suggested connections for unused and n.c. pins
TAB = V
cc
V
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
CC
GND
N.C.
INPUT2
N.C.
INPUT1
12
11
10
9
8
7
GND
V
1
2
3
4
5
6
cc
INPUT2
INPUT1
CURRENT SENSE1
CURRENT SENSE2
CS_DIS
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
V
cc
CS_DIS.
V
CC
TAB = VCC
PowerSSO-12
PowerSSO-24
Connection / Pin
Current Sense
N.C.
Output
Input
CS_DIS
Floating
N.R.
X
X
X
X
X
To Ground
Through 1KΩ resistor
N.R.
Through 10KΩ resistor
10KΩ
N.R. = Not recommended
3/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
2
Electrical specifications
Figure 3. Current and Voltage Conventions
IS
VCC
VCC
IOUT1
ICSD
OUTPUT1
CS_DIS
VOUT1
VCSD
ISENSE1
CURRENT
SENSE1
IIN1
VSENSE1
INPUT1
VIN1
IOUT2
IIN2
OUTPUT2
VOUT2
INPUT2
VIN2
ISENSE2
CURRENT
SENSE2
GND
VSENSE2
IGND
V
= V
- V during reverse battery condition
OUTn CC
Fn
2.1
Absolute Maximum Ratings
Table 2.
Symbol
Absolute Maximum Ratings
Parameter
Value
Unit
VCC
DC supply voltage
41
0.3
200
V
V
-VCC
Reverse DC supply voltage
-IGND DC reverse ground pin current
mA
A
IOUT
-IOUT
IIN
DC output current
Internally limited
12
Reverse DC output current
DC input current
A
-1 to 10
-1 to 10
200
mA
mA
mA
ICSD
DC current sense disable input current
-ICSENSE DC Reverse CS pin current
VCC-41
+VCC
V
V
VCSENSE Current sense maximum voltage
Maximum switching energy
EMAX
51
mJ
(L=1.5mH; RL=0Ω; Vbat=13.5V; Tjstart=150°C; IOUT = IlimL(Typ.) )
Electrostatic Discharge (Human Body Model: R=1.5KΩ;
C=100pF)
4000
2000
4000
5000
5000
V
V
V
V
V
– INPUT
– CURRENT SENSE
– CS_DIS
– OUTPUT
– VCC
VESD
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
°C
Tstg
4/26
VND5050AJ-E / VND5050AK-E
Electrical specifications
2.2
Thermal Data
Table 3.
Thermal Data
Value
Symbol
Parameter
Unit
PowerSSO-12
PowerSSO-24
Thermal resistance junction-case (Max.)
(with one channel ON)
Rthj-case
2.7
2.7
°C/W
°C/W
Rthj-amb Thermal resistance junction-ambient (Max.)
See Figure 26
See Figure 30
2.3
Electrical Characteristics
8V<V <36V; -40°C<T <150°C, unless otherwise specified.
CC
j
Table 4.
Symbol
Power section
Parameter
Test Conditions
Min.
4.5
Typ. Max. Unit
VCC
Operating supply voltage
Undervoltage shutdown
13
36
V
V
VUSD
3.5
4.5
Undervoltage shut-down
hysteresis
VUSDhyst
0.5
46
V
IOUT=2A; Tj=25°C
50
100
65
mΩ
mΩ
mΩ
RON
Vclamp
IS
On state resistance(2)
Clamp Voltage
IOUT=2A; Tj=150°C
IOUT=2A; VCC=5V; Tj=25°C
IS=20mA
41
52
V
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V; IOUT=0A
Supply current
2(1)
3
5(1)
6
µA
mA
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
0
0
0.01
3
5
IL(off)
VF
Off state output current(2)
µA
(2)
Output - V diode voltage
-IOUT=4A; Tj=150°C
0.7
V
CC
(1) PowerMOS leakage included.
(2) For each channel
Table 5.
Symbol
td(on)
td(off)
Switching (V =13V)
CC
Parameter
Test Conditions
Min.
Typ. Max. Unit
Turn-on delay time
Turn-off delay time
RL=6.5Ω (see Figure 6)
RL=6.5Ω (see Figure 6)
RL=6.5Ω
25
35
µs
µs
dVOUT/dt(on) Turn-on voltage slope
dVOUT/dt(off) Turn-off voltage slope
see Figure 19
see Figure 20
V/µs
V/µs
RL=6.5Ω
Switching energy losses
during twon
WON
RL=6.5Ω (see Figure 6)
RL=6.5Ω (see Figure 6)
0.24
0.2
mJ
mJ
Switching energy losses
during twoff
WOFF
5/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
Table 6.
Symbol
Logic input
Parameter
Test Conditions
Min.
Typ. Max. Unit
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
0.9
V
µA
V
VIN=0.9V
VIN=2.1V
1
VIH
2.1
IIH
10
µA
V
VI(hyst)
0.25
5.5
IIN=1mA
IIN=-1mA
7
V
V
VICL
Input clamp voltage
-0.7
VCSDL
ICSDL
VCSDH
ICSDH
CS_DIS low level voltage
Low level CS_DIS current
CS_DIS high level voltage
High level CS_DIS current
0.9
V
µA
V
VCSD=0.9V
VCSD=2.1V
1
2.1
10
7
µA
V
VCSD(hyst) CS_DIS hysteresis voltage
0.25
5.5
I
CSD=1mA
V
V
VCSCL
CS_DIS clamp voltage
ICSD=-1mA
-0.7
(1)
Table 7.
Symbol
Protections and Diagnostics
Parameter
Test Conditions
CC=13V
Min.
Typ.
Max.
Unit
V
12
18
24
24
A
A
IlimH
DC Short circuit current
5V<VCC<36V
Short circuit current during
thermal cycling
IlimL
VCC=13V TR<Tj<TTSD
7
A
TTSD
TR
Shutdown temperature
Reset temperature
150
175
200
°C
°C
°C
°C
T
+ 1 TRS + 5
RS
TRS
Thermal reset of STATUS
135
THYST
Thermal hysteresis (T
-T )
7
TSD
R
Turn-off output voltage
clamp
VDEMAG
IOUT=2A; VIN=0; L=6mH
VCC-41 VCC-46 VCC-52
V
Output voltage drop
limitation
IOUT=0.1A; Tj= -40°C...+150°C
VON
25
mV
(see Figure 7)
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must
limit the duration and number of activation cycles
6/26
VND5050AJ-E / VND5050AK-E
Electrical specifications
Table 8.
Symbol
Current Sense (8V<V <16V)
CC
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
IOUT=0.05A; VSENSE=0.5V;VCSD=0V;
Tj= -40°C...150°C
K0
K1
IOUT SENSE
/I
1270
2360
3450
IOUT=1A; VSENSE=0.5V;VCSD=0V;
Tj= -40°C
IOUT SENSE
/I
1470
1570
2020
2020
2610
2470
Tj= 25°C...150°C
IOUT=2A; VSENSE=4V;VCSD=0V;
Tj= -40°C
K2
K3
IOUT SENSE
/I
1740
1790
2020
2020
2320
2250
Tj= 25°C...150°C
IOUT=4A; VSENSE=4V;VCSD=0V;
Tj=-40°C
IOUT SENSE
/I
1880
1900
2010
2010
2160
2120
Tj=25°C...150°C
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj=-40°C...150°C
VCSD=0V; VIN=5V; Tj=-40°C...150°C
0
0
1
2
µA
µA
Analog sense leakage
current
ISENSE0
I
OUT=2A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj=-40°C...150°C
0
5
1
µA
Max analog sense
output voltage
VSENSE
I
OUT=4A; VCSD=0V
V
Analog sense output
voltage in
overtemperature
condition
VSENSEH
VCC=13V; RSENSE=10KΩ
9
8
V
Analog sense output
current in
overtemperature
condition
ISENSEH
VCC=13V; VSENSE=5V
mA
Delay Response time
tDSENSE1H from falling edge of
CS_DIS pin
VSENSE<4V, 0.5A<Iout<4A
50
5
100
20
µs
µs
µs
µs
ISENSE=90% of ISENSE max (see Figure 4)
Delay Response time
tDSENSE1L from rising edge of
CS_DIS pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSE max (see Figure 4)
Delay Response time
tDSENSE2H from rising edge of
INPUT pin
VSENSE<4V, 0.5A<Iout<4A
80
100
300
250
ISENSE=90% of ISENSE max (see Figure 4)
Delay Response time
tDSENSE2L from falling edge of
INPUT pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSE max (see Figure 4)
7/26
Electrical specifications
Figure 4. Current Sense Delay Characteristics
VND5050AJ-E / VND5050AK-E
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
Figure 5.
I
/I
Vs. I
(see Table 8 for details)
OUT SENSE
OUT
Iout/Isense
4000
max Tj= -40ºC to 150ºC
3500
3000
2500
2000
1500
1000
500
max Tj=25...150ºC
typical value
min Tj=25...150ºC
min Tj=-40ºC to 150ºC
0
0
1
2
3
4
5
Iout (A)
8/26
VND5050AJ-E / VND5050AK-E
Electrical specifications
SENSE (VCSD=0V)(1)
Table 9.
Truth table
CONDITIONS
INPUT
OUTPUT
L
L
0
Normal operation
Overtemperature
Undervoltage
H
H
Nominal
L
L
L
0
H
VSENSEH
L
L
L
0
0
H
L
H
H
L
L
L
0
Short circuit to GND
0 if Tj < TTSD
(Rsc ≤ 10 mΩ)
VSENSEH if Tj > TTSD
L
H
H
0
Short circuit to VCC
H
< Nominal
Negative output voltage
clamp
L
L
0
(1) If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Figure 6. Switching characteristics
V
OUT
t
t
Won
Woff
90%
80%
dV
/dt
dV
/dt
OUT (off)
OUT (on)
10%
t
f
t
r
t
INPUT
t
d(on)
t
d(off)
t
Figure 7. Output Voltage Drop Limitation
V
-V
cc out
Tj=150oC
Tj=25oC
Tj=-40oC
V
on
I
out
V
/R
on on(T)
9/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
Table 10. Electrical Transient Requirements
ISO 7637-2:
2004(E)
TEST LEVELS
Number of
pulses or
test times
Burst cycle/pulse repetition
time
Delays and
Impedance
III
IV
Test Pulse
1
2a
3a
3b
4
-75V
+37V
-100V
+75V
-6V
-100V
+50V
-150V
+100V
-7V
5000 pulses
5000 pulses
1h
1h
1 pulse
1 pulse
0.5 s
0.2 s
90 ms
90 ms
5 s
5 s
100 ms
100 ms
2 ms, 10 Ω
50 µs, 2 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
5b(1)
+40V
+40V
ISO 7637-2:
2004(E)
TEST LEVEL RESULTS
III
IV
Test Pulse
1
2a
3a
3b
4
C
C
C
C
C
C
C
C
C
C
C
C
5b(1)
CLASS
CONTENTS
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
E
(1) For load dump exceeding the above value a centralized suppressor must be adopted.
10/26
VND5050AJ-E / VND5050AK-E
Figure 8. Waveforms
Electrical specifications
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO VCC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
<Nominal
OVERLOAD OPERATION
TTSD
TR
Tj
TRS
INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
SENSE CURRENT
VSENSEH
thermal cycling
SHORTED LOAD
current
limitation
power
limitation
NORMAL LOAD
11/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
2.4
Electrical characteristics curves
Figure 9. Off State Output Current
Figure 10. High Level Input Current
Iloff (uA)
1
Iih (uA)
5
4.5
4
0.875
Vin=2.1V
Off State
0.75
0.625
0.5
Vcc=13V
Vin=Vout=0V
3.5
3
2.5
2
0.375
0.25
0.125
0
1.5
1
0.5
0
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C)
Tc (°C)
Figure 11. Input Clamp Voltage
Figure 12. Input High Level
Vih (V)
4
Vicl (V)
7
6.8
3.5
3
Iin=1mA
6.6
6.4
6.2
6
2.5
2
5.8
5.6
5.4
5.2
5
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 13. Input Low Level
Figure 14. Input Hysteresis Voltage
Vil (V)
2
Vhyst (V)
1
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C)
Tc (°C)
12/26
VND5050AJ-E / VND5050AK-E
Electrical specifications
Figure 15. On State Resistance Vs. T
Figure 16. On State Resistance Vs. V
CC
case
Ron (mOhm)
100
Ron (mOhm)
100
90
80
70
60
50
40
30
20
10
0
90
Iout=2A
Vcc=13V
Tc= 150°C
80
70
Tc= 125°C
Tc= 25°C
60
50
40
30
20
10
0
Tc= - 40°C
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125 150
175
Vcc (V)
Tc (°C)
Figure 17. Undervoltage Shutdown
Figure 18. I
Vs. T
LIMH case
Ilimh (A)
25
Vusd (V)
16
22.5
20
14
12
10
8
Vcc=13V
17.5
15
12.5
10
6
4
7.5
5
2
0
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 19. Turn-on Voltage Slope
Figure 20. Turn-off Voltage Slope
(dVout/dt)on (V/ms)
1000
(dVout/dt)off (V/ms)
1000
900
900
Vcc=13V
RI=6.5Ohm
Vcc=13V
RI=6.5Ohm
800
800
700
700
600
500
400
300
200
100
0
600
500
400
300
200
100
0
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100 125 150 175
Tc (°C)
Tc (°C)
13/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
Figure 21. STAT_DIS Clamp Voltage
Figure 22. Low Level STAT_DIS Voltage
Vsdcl(V)
Vsdl(V)
8
14
12
7
6
5
4
3
2
1
Isd=1mA
10
8
6
4
2
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 23. High Level STAT_DIS Voltage
Vsdh(V)
8
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
14/26
VND5050AJ-E / VND5050AK-E
Application information
3
Application information
Figure 24. Application schematic
+5V
V
CC
R
prot
CS_DIS
D
ld
R
µC
INPUT
prot
OUTPUT
R
prot
CURRENT SENSE
GND
R
SENSE
R
GND
V
C
D
GND
EXT
GND
Note: Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1:
Resistor in the ground line (R
only). This can be used with any type of load.
GND
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤ 600mV / (I
).
S(on)max
GND
GND
≥ (−V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power Dissipation in R
(when V <0: during reverse battery situations) is:
CC
GND
2
P = (-V ) /R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
will produce a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
.
GND
15/26
Application information
VND5050AJ-E / VND5050AK-E
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2:
A diode (D
) in the ground line.
GND
A resistor (R
=1kΩ) should be inserted in parallel to D
if the device drives an
GND
GND
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
µC I/Os protection:
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to
prot
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-V
/I
≤ R
≤ (V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND IHmax
Calculation example:
For V = - 100V and I
≥ 20mA; V ≥ 4.5V
OHµC
CCpeak
latchup
5kΩ ≤ R
≤ 180kΩ.
prot
Recommended values: R
=10kΩ, C
=10nF.
EXT
prot
16/26
VND5050AJ-E / VND5050AK-E
Package and PCB thermal data
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 25. PowerSSO-12 PC Board
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm ).
th
th
2
Figure 26. R
Vs. PCB copper area in open box free air condition
thj-amb
RTHj_amb(°C/W)
70
65
60
55
50
45
40
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Figure 27. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse
ZTH (˚C/W)
1000
Footprint
100
2
2 cm
2
8 cm
10
1
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Pulse Calculation Formula
= R ⋅ δ + Z (1 – δ)
Z
THδ
TH
THtp
where δ = t /T
P
17/26
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
Figure 28. Thermal Fitting Model of a Double Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2)
Footprint
2
8
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
0.7
2.8
7
R4 (°C/W)
10
10
15
20
9
R5 (°C/W)
22
10
15
R6 (°C/W)
26
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.001
0.0025
0.05
0.2
0.1
0.8
6
0.1
1
0.27
3
9
18/26
VND5050AJ-E / VND5050AK-E
Package and PCB thermal data
4.2
PowerSSO-24 thermal data
Figure 29. PowerSSO-24 PC Board
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm ).
th
th
2
Figure 30. R
Vs. PCB copper area in open box free air condition
thj-amb
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Figure 31. PowerSSO-24 Thermal Impedance Junction Ambient Single Pulse
ZTH (˚C/W)
1000
Footprint
100
2
2 cm
2
8 cm
10
1
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Pulse Calculation Formula
= R ⋅ δ + Z (1 – δ)
Z
THδ
TH
THtp
where δ = t /T
P
19/26
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
Figure 32. Thermal Fitting Model of a Single Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2)
Footprint
2
8
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
0.4
2
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.001
0.0022
0.025
0.75
1
4
5
9
2.2
17
20/26
VND5050AJ-E / VND5050AK-E
Package information
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.1
Package Mechanical
Figure 33. PowerSSO-12™ Package Dimensions
D
0.25 mm
GAUGE PLANE
C
h x 45˚
A
A2
B
C
C
SEATING
PLANE
L
A1
K
ddd
12
7
X
H
E
BOTTOM
VIEW
Y
1
6
e
Table 11. PowerSSO-12™ Mechanical Data
millimeters
Typ
Symbol
Min
Max
A
A1
A2
B
C
D
1.250
0.000
1.100
0.230
0.190
4.800
3.800
1.620
0.100
1.650
0.410
0.250
5.000
4.000
E
e
0.800
H
h
L
k
5.800
0.250
0.400
0°
6.200
0.500
1.270
8°
X
Y
ddd
1.900
3.600
2.500
4.200
0.100
21/26
Package information
Figure 34. PowerSSO-24™ Package Dimensions
VND5050AJ-E / VND5050AK-E
Table 12. PowerSSO-24™ Mechanical Data
millimeters
Symbol
Min
Typ
Max
2.47
2.40
0.075
0.51
0.32
10.50
7.6
A
A2
a1
b
2.15
2.15
0
0.33
0.23
10.10
7.4
c
D
E
e
0.8
8.8
e3
G
G1
H
h
0.1
0.06
10.5
0.4
10.1
0.55
L
0.85
10deg
4.7
N
X
4.1
6.5
Y
7.1
22/26
VND5050AJ-E / VND5050AK-E
Package information
5.2
Packing information
Figure 35. PowerSSO-12 Tube Shipment (No Suffix)
B
Base Q.ty
100
2000
532
C
Bulk Q.ty
Tube length ( 0.5)
A
1.85
6.75
0.6
A
B
C ( 0.1)
All dimensions are in mm.
Figure 36. PowerSSO-12 Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
8
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.5
1.5
5.5
4.5
2
Compartment Depth
Hole Spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
23/26
Package information
VND5050AJ-E / VND5050AK-E
Figure 37. PowerSSO-24 Tube Shipment (No Suffix)
Base Q.ty
Bulk Q.ty
Tube length ( 0.5)
A
49
1225
532
3.5
C
B
B
13.8
0.6
C ( 0.1)
All dimensions are in mm.
A
Figure 38. PowerSSO-24 Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
P0 ( 0.1)
P
D ( 0.05) 1.55
D1 (min)
F ( 0.1)
24
4
12
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
1.5
11.5
2.85
2
Compartment Depth K (max)
Hole Spacing
P1 ( 0.1)
End
All dimensions are in mm.
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
24/26
VND5050AJ-E / VND5050AK-E
Revision history
6
Revision history
Table 13. Document revision history
Date
Revision
Changes
30-Mar-2006
14-Apr-2006
1
2
Initial release.
PowerSSO-24 dimensions table update.
25/26
VND5050AJ-E / VND5050AK-E
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26/26
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