VND5050KTR-E [STMICROELECTRONICS]
Double channel high side driver for automotive applications; 用于汽车应用的双通道高侧驱动器
| 型号： | VND5050KTR-E |
| 厂家： | 
ST |
| 描述： | Double channel high side driver for automotive applications |
| 文件： | 总37页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5050J-E
VND5050K-E
Double channel high side driver
for automotive applications
Features
Max supply voltage
VCC
41V
Operating voltage range
VCC 4.5 to 36V
Max On-State resistance (per ch.) RON
50 mΩ
18 A
2 µA(1)
PowerSSO-12
PowerSSO-24
Current limitation (typ)
Off state supply current
ILIMH
IS
– Electrostatic discharge protection
(1) Typical value with all loads connected.
Application
■ Main
■ All types of resistive, inductive and capacitive
– Inrush current active management by
power limitation
loads
– Very low stand-by current
– 3.0V CMOS compatible input
Description
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
The VND5050K-E and VND5050J-E are
monolithic devices made using
STMicroelectronics VIPower M0-5 technology.
they are intended for driving resistive or inductive
loads with one side connected to ground. Active
– In compliance with the 2002/95/EC
European directive
■ Diagnostic functions
V
pin voltage clamp protects the devices
CC
– Open drain status output
– On state open load detection
– Off state open load detection
– Thermal shutdown indication
against low energy spikes (see ISO7637 transient
compatibility table). The devices detect open load
condition both in on and off state, when STAT_DIS
is left open or driven low. Output shorted to V is
CC
detected in the off state. When STAT_DIS is
driven high, STATUS pin is in high impedance
state. Output current limitation protects the
devices in overload condition. In case of long
overload duration, the devices limit the dissipated
power to a safe level up to thermal shut-down
intervention. Thermal shut-down with automatic
restart allows the devices to recover normal
operation as soon as fault conditions disappear..
■ Protections
– Undervoltage shut-down
– Overvoltage clamp
– Output stuck to V detection
– Load current limitation
– Self limiting of fast thermal transients
CC
– Protection against loss of ground and loss
of V
CC
– Thermal shut down
– Reverse battery protection (see Figure 27)
Table 1. Device summary
Package
Order codes
Part number (Tube)
VND5050J-E
Part number (Tape & Reel)
VND5050JTR-E
PowerSSO-12
PowerSSO-24
VND5050K-E
VND5050KTR-E
December 2007
Rev 4
1/37
www.st.com
37
Contents
VND5050J-E / VND5050K-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
3.1.1
3.1.2
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20
Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21
3.2
3.3
3.4
3.5
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
4.2
PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1
5.2
5.3
5.4
5.5
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO-24™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-24™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37
VND5050J-E / VND5050K-E
List of tables
List of tables
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and n.c. pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status pin (V =0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SD
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PowerSSO-12™ thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24™ thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
List of figures
VND5050J-E / VND5050K-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. On state resistance vs V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. Openload On state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. Openload Off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20.
I
vs T
LIM case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. Turn- On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 23. Turn- Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 24. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 25. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 26. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 28. Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 29. Maximum turn Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 30. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 31. Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 24
Figure 32. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel ON) . . . 25
Figure 33. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 34. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 35. Rthj-amb Vs. PCB copper area in open box free air condition (one channel ON) . . . . . . . 27
Figure 36. PowerSSO-24™ Thermal impedance junction ambient single pulse (one channel ON) . . 28
Figure 37. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 28
Figure 38. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 39. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 40. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 41. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 42. PowerSS0-24TM tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 43. PowerSSO-24TM tape and reel shipment (suffix “TR”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4/37
VND5050J-E / VND5050K-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
V
CC
VCC
CLAMP
GND
UNDERVOLTAGE
CLAMP 1
INPUT1
STATUS1
DRIVER 1
STAT_DIS
OUTPUT1
LOGIC
OVERTEMP. 1
INPUT2
CURRENT LIMITER 1
OPENLOAD ON 1
STATUS2
V
OPENLOAD OFF 1
CC
INPUT2
CONTROL & PROTECTION
EQUIVALENT TO
STATUS2
OUTPUT2
PWR
1
CHANNEL1
LIM
Table 2.
Pin function
Name
Function
VCC
Battery connection.
Power output.
OUTPUTn
Ground connection. Must be reverse battery protected by an external diode/resistor
network.
GND
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
INPUTn
STATUSn
STAT_DIS
Open drain digital diagnostic pin.
Active high CMOS compatible pin, to disable the STATUS pin.
5/37
Block diagram and pin description
Figure 2. Configuration diagram (top view)
VND5050J-E / VND5050K-E
TAB = V
cc
VCC
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
GND.
N.C.
STAT_DIS
INPUT1
STATUS1
N.C.
STATUS2
N.C.
INPUT2
12
11
10
9
8
7
GND
STAT_DIS
INPUT 1
STATUS 1
STATUS 2
INPUT 2
V
1
2
3
4
5
6
cc
OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
V
cc
N.C.
VCC
TAB = VCC
PowerSSO-12
PowerSSO-24
Table 3.
Suggested connections for unused and n.c. pins
Connection / Pin
STATUS
N.C.
OUTPUT
INPUT
STAT_DIS
Floating
X
X
X
X
X
Through 10KΩ
Through 10KΩ
To ground
N.R.(1)
X
N.R.
resistor
resistor
(1) Not recommended.
6/37
VND5050J-E / VND5050K-E
Electrical specifications
2
Electrical specifications
Figure 3. Current and voltage conventions
IS
V
CC
VCC
Fn
V
ISD
IOUTn
STAT_DIS
INPUTn
OUTPUTn
STATUSn
VSD
VOUTn
IINn
ISTATn
VINn
VSTATn
GND
IGND
Note:
V
= V
- V
during reverse battery condition.
CCn
Fn
OUTn
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
41
Unit
V
VCC
DC supply voltage
- VCC Reverse DC supply voltage
- IGND DC reverse ground pin current
0.3
V
200
mA
A
IOUT
DC output current
Internally limited
15
- IOUT Reverse dc output current
A
IIN
DC input current
DC status current
+10 / -1
+10 / -1
+10 / -1
mA
mA
mA
ISTAT
ISTAT_DIS DC status disable current
Maximum switching energy
EMAX
104
mJ
(L=3mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.))
7/37
Electrical specifications
VND5050J-E / VND5050K-E
Table 4.
Symbol
Absolute maximum ratings (continued)
Parameter
Value
Unit
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
VESD
4000
750
V
V
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
-40 to 150
- 55 to 150
°C
°C
Tstg
2.2
Thermal data
Table 5.
Thermal data
Value
Symbol
Parameter
Unit
PowerSSO-12
PowerSSO-24
Thermal resistance junction-case (Max.)
(with one channel ON)
Rthj-case
2.8
2.8
°C/W
°C/W
Thermal resistance junction-ambient
(Max.)
Rthj-amb
See Figure 31
See Figure 35
8/37
VND5050J-E / VND5050K-E
Electrical specifications
2.3
Electrical characteristics
8V<V <36V; -40°C<T <150°C, unless otherwise specified.
CC
j
.
Table 6.
Power section
Parameter
Symbol
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
Undervoltage shutdown
4.5
13
36
V
V
VUSD
3.5
4.5
Undervoltage shut-down
hysteresis
VUSDhyst
0.5
V
IOUT=2A; Tj=25°C
50
100
65
mΩ
mΩ
mΩ
RON
On state resistance(2)
Clamp Voltage
IOUT=2A; Tj=150°C
IOUT=2A; VCC=5V; Tj=25°C
Vclamp
IS=20mA
41
46
52
V
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
IS
Supply current
2(1)
3
5(1)
6
µA
On State; VCC=13V; VIN=5V;
IOUT=0A
mA
VIN=VOUT=0V; VCC=13V;
Tj=25°C
0
0
0.01
3
5
Off state output
current(2)
IL(off1)
VIN=VOUT=0V; VCC=13V;
Tj=125°C
µA
V
IL(off2)
VF
Off state output current(2) VIN=0V; VOUT=4V
-75
0
Output - V diode
CC
-IOUT=4A; Tj=150°C
0.7
(2)
voltage
(1) PowerMOS leakage included.
(2) For each channel.
Table 7.
Symbol
td(on)
td(off)
Switching (V = 13V; T = 25°C)
CC j
Parameter
Test conditions
Min. Typ. Max. Unit
Turn-On delay time
Turn-Off delay time
RL= 6.5Ω (see Figure 5)
RL= 6.5Ω (see Figure 5)
RL= 6.5Ω
20
µs
µs
40
dVOUT/dt(on) Turn-On voltage slope
dVOUT/dt(off) Turn-Off voltage slope
See Figure 21
See Figure 23
V/ µs
V/ µs
RL= 6.5Ω
Switching energy losses
during twon
WON
RL= 6.5Ω (see Figure 5)
RL= 6.5Ω (see Figure 5)
0.21
0.28
mJ
mJ
Switching energy losses
during twoff
WOFF
9/37
Electrical specifications
VND5050J-E / VND5050K-E
Min. Typ. Max. Unit
Table 8.
Symbol
Status pin (V =0V)
SD
Parameter
Test conditions
Status low output
voltage
VSTAT
ISTAT= 1.6 mA, VSD=0V
0.5
10
V
Normal operation or VSD=5V,
VSTAT= 5V
ILSTAT Status leakage current
µA
pF
Status pin input
CSTAT
Normal operation or VSD=5V,
VSTAT= 5V
100
7
capacitance
ISTAT= 1mA
ISTAT= -1mA
5.5
V
V
VSCL
Status clamp voltage
-0.7
(1)
Table 9.
Symbol
Protections
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
CC=13V
12
18
24
24
A
A
IlimH
DC short circuit current
5V<VCC<36V
VCC=13V
Short circuit current
during thermal cycling
IlimL
7
A
TR<Tj<TTSD
TTSD
TR
Shutdown temperature
Reset temperature
150
175
200
°C
°C
°C
T
+ 1
T
+ 5
RS
RS
TRS
Thermal reset of STATUS
135
Thermal hysteresis
(TTSD-TR)
THYST
tSDL
7
°C
µs
V
Status delay in overload
conditions
Tj>TTSD (see Figure 4)
20
Turn-off output voltage
clamp
VDEMAG
IOUT=2A; VIN=0; L=6mH VCC-41 VCC-46 VCC-52
IOUT= 0.1A;
Output voltage drop
limitation
VON
Tj= -40°C...+150°C
(see Figure 6)
25
mV
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/37
VND5050J-E / VND5050K-E
Electrical specifications
Table 10. Openload detection
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
Openload On state
detection threshold
See
Figure 18
IOL
VIN = 5V ,8V<VCC<18V
10
70
mA
µs
Openload On state
detection delay
I
= 0A, V =13V
OUT CC
tDOL(on)
200
(see Figure 4)
Delay between INPUT
falling edge and STATUS
rising edge in Openload
condition
tPOL
IOUT = 0A (see Figure 4)
200
500
1000
µs
Openload Off state
voltage detection
threshold
See
Figure 19
VOL
VIN = 0V, 8V<VCC<16V
2
4
V
Output short circuit to
tDSTKON VCC detection delay at
turn Off
(see Figure 4)
180
tPOL
µs
Table 11. Logic input
Symbol
Parameter
Input low level
Test conditions
Min. Typ. Max. Unit
VIL
IIL
0.9
V
µA
V
Low level input current
Input high level
VIN =0.9 V
VIN = 2.1 V
1
VIH
2.1
IIH
High level input current
Input hysteresis voltage
10
7
µA
V
VI(hyst)
0.25
5.5
I
IN = 1mA
V
V
VICL
Input clamp voltage
IIN = -1mA
-0.7
STAT_DIS low level
voltage
VSDL
0.9
V
µA
V
Low level STAT_DIS
current
ISDL
VSD = 0.9 V
1
STAT_DIS high level
voltage
VSDH
ISDH
VSD(hyst)
2.1
High level STAT_DIS
current
VSD = 2.1 V
10
7
µA
V
STAT_DIS hysteresis
voltage
0.25
5.5
ISD= 1mA
ISD= -1mA
V
V
VSDCL
STAT_DIS clamp voltage
-0.7
11/37
Electrical specifications
Figure 4. Status timings
VND5050J-E / VND5050K-E
OPEN LOAD STATUS TIMING (with external pull-up)
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
IOUT < IOL
VIN
VIN
VOUT > VOL
VOUT < VOL
VSTAT
VSTAT
tDOL(on)
tDOL(on)
tPOL
OVER TEMP STATUS TIMING
OUTPUT STUCK TO VCC
Tj > TTSD
IOUT > IOL
VIN
VIN
VOUT > VOL
VSTAT
VSTAT
tDOL(on)
tSDL
tDSTKON
tSDL
Table 12. Truth table
Conditions
INPUT
OUTPUT
SENSE (VCSD=0V)(1)
L
L
H
H
Normal operation
H
H
L
L
H
H
Current limitation
Overtemperature
Undervoltage
H
X
L
L
L
H
L
H
L
L
L
X
X
H
L
H
H
L(2)
H
Output voltage > VOL
Output current < IOL
H
L
L
H (3)
L
H
H
(1) If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
(2) The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
(3) The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
12/37
VND5050J-E / VND5050K-E
Figure 5. Switching characteristics
Electrical specifications
VOUT
90%
tf
80%
tr
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
INPUT
td(on)
td(off)
t
Figure 6. Output voltage drop limitation
V -V
cc out
Tj=150oC
Tj=25oC
Tj=-40oC
V
on
I
out
V /R
on on(T)
13/37
Electrical specifications
VND5050J-E / VND5050K-E
Table 13. Electrical transient requirements
ISO 7637-2:
2004(E)
Test levels(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
III
IV
Test pulse
1
-75V
+37V
-100V
+75V
-100V
+50V
5000 pulses
0.5 s
5 s
2 ms, 10 Ω
50 µs, 2 Ω
2a
3a
3b
5000 pulses
0.2 s
90 ms
90 ms
5 s
-150V
+100V
1h
1h
100 ms
100 ms
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01
4
-6V
-7V
1 pulse
1 pulse
Ω
5b(2)
+65V
+87V
400 ms, 2 Ω
Test level results(1)
ISO 7637-2:
2004(E)
III
C
C
C
C
C
C
IV
C
C
C
C
C
C
Test pulse
1
2a
3a
3b
4
5b(2)
(1) The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
(2) Valid in case of external load dump clamp: 40V maximum referred to ground.
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
14/37
VND5050J-E / VND5050K-E
Figure 7. Waveforms
Electrical specifications
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
V
USDhyst
V
CC
V
USD
INPUT
STAT_DIS
LOAD CURRENT
STATUS
undefined
OPEN LOAD with external pull-up
INPUT
STAT_DIS
V
OUT
>V
OL
LOAD VOLTAGE
STATUS
V
OL
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
LOAD CURRENT
STATUS
I
<I
OUT OL
t
POL
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
I >I
OUT OL
V
OUT
>V
OL
LOAD VOLTAGE
STATUS
V
OL
t
DSTKON
OVERLOAD OPERATION
T
TSD
T
T
R
j
T
RS
INPUT
STAT_DIS
I
LIMH
I
LIML
LOAD CURRENT
STATUS
thermal cycling
SHORTED LOAD
current
limitation
power
limitation
NORMAL LOAD
15/37
Electrical specifications
VND5050J-E / VND5050K-E
2.4
Electrical characteristics curves
Figure 8. Off state output current
Figure 9. High level input current
Iloff1 (uA)
1
lih (uA)
5
4.5
4
0.875
Vin=2.1V
Off state
0.75
0.625
0.5
Vcc=13V
Vin=Vout=0V
3.5
3
2.5
2
0.375
0.25
0.125
0
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
125
125
150
150
150
175
175
175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C)
Tc (°C)
Figure 10. Input clamp voltage
Figure 11. Input high level
Vih (V)
4
Vicl (V)
8
3.5
3
7.75
lin=1mA
7.5
2.5
2
7.25
7
1.5
1
6.75
6.5
6.25
6
0.5
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Tc (°C)
Tc (°C )
Figure 12. Input low level
Figure 13. Input hysteresis voltage
Vil (V)
4
Vihyst (V)
2
3.5
3
1.75
1.5
1.25
1
2.5
2
1.5
1
0.75
0.5
0.25
0
0.5
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Tc (°C)
Tc (°C)
16/37
VND5050J-E / VND5050K-E
Electrical specifications
Figure 14. Status low output voltage
On state resistance vs T
case
Ron (mOhm)
100
Vstat (V)
0.9
90
0.8
Io ut=2A
Vcc=13V
Istat=1.6mA
80
0.7
70
0.6
0.5
0.4
0.3
0.2
0.1
0
60
50
40
30
20
10
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 15. Status leakage current
Figure 16. On state resistance vs V
CC
Ron (mOhm)
100
Ilstat (uA)
0.055
90
0.05
Tc=150°C
Tc=125°C
80
70
60
50
40
30
20
10
0
Vstat=5V
0.045
Tc=25°C
Tc=-40°C
0.04
0.035
0.03
0.025
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
150
175
Vcc (V)
Tc (°C )
Figure 17. Status clamp voltage
Figure 18. Openload On state detection
threshold
Vscl (V)
9
Iol (mA)
100
8.5
90
Istat=1mA
Vin=5V
8
80
7.5
7
70
60
50
40
30
20
10
0
6.5
6
5.5
5
4.5
4
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
17/37
Electrical specifications
VND5050J-E / VND5050K-E
Figure 19. Openload Off state voltage
detection threshold
Figure 20. I
vs T
LIM case
Ilimh (A)
25
Vol (V)
5
22.5
20
4.5
Vcc=13V
Vin=0V
4
17.5
15
3.5
3
12.5
10
2.5
2
7.5
5
1.5
1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C )
Tc (°C )
Figure 21. Turn- On voltage slope
Figure 22. Undervoltage shutdown
dVout/dt(on) (V/ms)
1000
Vusd (V)
14
12
10
8
900
Vcc=13V
800
RI=6.5Ohm
700
600
500
400
300
200
100
0
6
4
2
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 23. Turn- Off voltage slope
Figure 24. STAT_DIS clamp voltage
dVout/dt(off) (V/ms)
1000
Vsdcl(V)
14
12
900
Vcc=13V
800
RI=6.5Ohm
Is d=1mA
700
10
600
500
400
300
200
100
0
8
6
4
2
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
18/37
VND5050J-E / VND5050K-E
Electrical specifications
Figure 25. High level STAT_DIS voltage
Figure 26. Low level STAT_DIS voltage
Vsdh(V)
8
Vsdl(V)
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
19/37
Application information
VND5050J-E / VND5050K-E
3
Application information
Figure 27. Application schematic
+5V
+5V
V
CC
R
prot
STAT_DIS
INPUT
D
ld
R
prot
µC
OUTPUT
STATUS
R
prot
GND
R
GND
V
D
GND
GND
Note:
Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (R
only)
GND
This can be used with any type of load.
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤600mV / (I
).
GND
GND
S(on)max
≥ (−V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power Dissipation in R
(when V <0: during reverse battery situations) is:
CC
GND
2
P = (-V ) /R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
will produce a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
.
GND
20/37
VND5050J-E / VND5050K-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2: a diode (D
) in the ground line
GND
A resistor (R
inductive load.
=1kΩ) should be inserted in parallel to D if the device drives an
GND
GND
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to
prot
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-V
/I
≤R
≤(V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND IHmax
Calculation example:
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
CCpeak
latchup
OHµC
5kΩ ≤R
≤180kΩ
prot
Recommended values: R
=10kΩ.
prot
3.4
Open load detection in Off state
Off state open load detection requires an external pull-up resistor (R ) connected between
PU
OUTPUT pin and a positive supply voltage (V ) like the +5V line used to supply the
PU
microprocessor.
The external resistor has to be selected according to the following requirements:
1. no false open load indication when load is connected: in this case we have to avoid
V
V
to be higher than V
; this results in the following condition
OUT
OUT
Olmin
=(V /(R +R ))R <V .
PU
L
PU
L
Olmin
2. no misdetection when load is disconnected: in this case the V
has to be higher than
OUT
V
; this results in the following condition R <(V –V
)/I
.
OLmax
PU
PU OLmax L(off2)
21/37
Application information
Because I
VND5050J-E / VND5050K-E
may significantly increase if V is pulled high (up to several mA), the pull-
s(OFF)
out
up resistor R should be connected to a supply that is switched OFF when the module is in
PU
standby.
The values of V
section.
, V
and I
are available in the Electrical Characteristics
OLmin OLmax
L(off2)
Figure 28. Open load detection in Off state
PU
V batt.
V
CC
V
PU
R
DRIVER
+
L(off2)
I
INP UT
LOGIC
OUT
+
R
-
STATUS
OL
V
L
R
GROUND
22/37
VND5050J-E / VND5050K-E
Application information
3.5
Maximum demagnetization energy (VCC = 13.5V)
Figure 29. Maximum turn Off current versus inductance (for each channel)
100
10
1
A
B
C
0,1
1
10
100
L (mH)
A: T
= 150°C single pulse
jstart
B: T
C: T
= 100°C repetitive pulse
= 125°C repetitive pulse
jstart
jstart
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R =0 Ω. In case of repetitive pulses, T
(at beginning of each
jstart
L
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
23/37
Package and PCB thermal data
VND5050J-E / VND5050K-E
4
Package and PCB thermal data
4.1
PowerSSO-12™ thermal data
Figure 30. PowerSSO-12™ PC board
Note:
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4
th th
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
2
Copper areas: from minimum pad lay-out to 8cm ).
Figure 31. R
Vs. PCB copper area in open box free air condition (one channel
thj-amb
ON)
RTHj_amb(°C/W)
70
65
60
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
24/37
VND5050J-E / VND5050K-E
Package and PCB thermal data
Figure 32. PowerSSO-12™ thermal impedance junction ambient single pulse (one
channel ON)
ZTH (°C/W)
Footprint
100
10
1
2 cm2
8 cm2
0,1
0,0001
0,001
0,01
0,1
Time (s)
1
10
100
1000
Equation 1: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THδ
TH
THtp
where δ = t /T
P
(a)
Figure 33. Thermal fitting model of a double channel HSD in PowerSSO-12™
(a )The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/37
Package and PCB thermal data
Table 14. PowerSSO-12™ thermal parameters
VND5050J-E / VND5050K-E
Area/island (cm2)
Footprint
2
8
R1= R7 (°C/W)
R2= R8 (°C/W)
R3 (°C/W)
0.7
2.8
4
R4 (°C/W)
8
8
7
R5 (°C/W)
22
15
20
10
15
R6 (°C/W)
26
C1= C7 (W.s/°C)
C2= C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.001
0.0025
0.05
0.2
0.1
0.8
6
0.1
1
0.27
3
9
26/37
VND5050J-E / VND5050K-E
Package and PCB thermal data
4.2
PowerSSO-24™ thermal data
Figure 34. PowerSSO-24™ PC board
Note:
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4
th th
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
2
Copper areas: from minimum pad lay-out to 8cm ).
Figure 35. R
Vs. PCB copper area in open box free air condition (one channel
thj-amb
ON)
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
27/37
Package and PCB thermal data
VND5050J-E / VND5050K-E
Figure 36. PowerSSO-24™ Thermal impedance junction ambient single pulse (one
channel ON)
Equation 2: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THδ
TH
THtp
where δ = t /T
P
(b)
Figure 37. Thermal fitting model of a double channel HSD in PowerSSO-24™
(b )The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
28/37
VND5050J-E / VND5050K-E
Table 15. PowerSSO-24™ thermal parameters
Package and PCB thermal data
Area/island (cm2)
Footprint
2
8
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
0.4
2
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.001
0.0022
0.025
0.75
1
4
5
9
2.2
17
29/37
Package and packing information
VND5050J-E / VND5050K-E
5
Package and packing information
5.1
ECOPACK® packages
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
PowerSSO-12™ package information
Figure 38. PowerSSO-12™ package dimensions
30/37
VND5050J-E / VND5050K-E
Package and packing information
Table 16. PowerSSO-12™ mechanical data
Millimeters
Typ.
Symbol
Min.
1.25
0
Max.
1.62
0.1
A
A1
A2
B
1.10
0.23
0.19
4.8
1.65
0.41
0.25
5.0
C
D
E
3.8
4.0
e
0.8
H
5.8
0.25
0.4
0°
6.2
0.5
1.27
8°
h
L
k
X
1.9
3.6
2.5
4.2
0.1
Y
ddd
31/37
Package and packing information
VND5050J-E / VND5050K-E
5.3
PowerSSO-24™ package information
Figure 39. PowerSSO-24™ package dimensions
Table 17. PowerSSO-24™ mechanical data
Millimeters
Symbol
Min.
2.15
2.15
0
Typ.
Max.
2.47
2.40
0.075
0.51
0.32
10.50
7.6
A
A2
a1
b
0.33
0.23
10.10
7.4
c
D
E
e
0.8
8.8
e3
G
0.1
G1
0.06
32/37
VND5050J-E / VND5050K-E
Package and packing information
Table 17. PowerSSO-24™ mechanical data (continued)
Millimeters
Typ.
Symbol
Min.
Max.
10.5
0.4
H
h
10.1
L
0.55
0.85
10deg
4.7
N
X
Y
4.1
6.5
7.1
33/37
Package and packing information
VND5050J-E / VND5050K-E
5.4
PowerSSO-12™ packing information
Figure 40. PowerSSO-12™ tube shipment (no suffix)
B
Base Q.ty
100
2000
532
C
Bulk Q.ty
Tube length ( 0.5)
A
1.85
6.75
0.6
A
B
C ( 0.1)
All dimensions are in mm.
Figure 41. PowerSSO-12™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
8
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.5
1.5
5.5
4.5
2
Compartment Depth
Hole Spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
34/37
VND5050J-E / VND5050K-E
Package and packing information
5.5
PowerSSO-24™ packing information
Figure 42. PowerSS0-24TM tube shipment (no suffix)
Base Qty
49
Bulk Qty
1225
C
Tube length ( 0.5)
A
532
3.5
B
B
13.8
0.6
C ( 0.1)
All dimensions are in mm.
A
Figure 43. PowerSSO-24TM tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
C ( 0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
12
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.55
1.5
11.5
2.85
2
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
No components
500mm min
Top
cover
tape
No components Components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
35/37
Revision history
VND5050J-E / VND5050K-E
6
Revision history
Table 18. Document revision history
Date
Revision
Changes
30-Mar-2006
1
Initial release.
Minor formatting changes.
New disclaimer attached.
11-Jan-2007
2
Reformatted and restructured.
Contents and lists of tables and figures added.
Section 3.5: Maximum demagnetization energy (VCC = 13.5V)
added.
Table 4: Absolute maximum ratings: EMAX entries updated.
31-May-2007
3
Table 13: Electrical transient requirements :Test level values III
and IV for test pulse 5b and notes updated
Figure 33: Thermal fitting model of a double channel HSD in
PowerSSO-12™ , Figure 37: Thermal fitting model of a double
channel HSD in PowerSSO-24™ : added notes.
Features table updated: ILIMH changed from 19 to 18A.
Updated Section 4.1: PowerSSO-12™ thermal data:
– Changed Figure 31: Rthj-amb Vs. PCB copper area in open
box free air condition (one channel ON).
– Changed Figure 32: PowerSSO-12™ thermal impedance
junction ambient single pulse (one channel ON).
3-Dec-2007
4
– Updated Table 14: PowerSSO-12™ thermal parameters:
R3 value changed from 7 to 4 °C/W.
R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.
36/37
VND5050J-E / VND5050K-E
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