VND5025LAK-E [STMICROELECTRONICS]
Double channel high side driver with analog current sense for automotive applications; 具有模拟电流检测用于汽车应用的双通道高侧驱动器
| 型号： | VND5025LAK-E |
| 厂家： | 
ST |
| 描述： | Double channel high side driver with analog current sense for automotive applications |
| 文件： | 总31页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND5025LAK-E
Double channel high side driver with analog
current sense for automotive applications
Features
Max supply voltage
VCC
41V
Operating voltage range
VCC 4.5 to 36V
PowerSSO-24™
Max on-state resistance (per ch.)
Current limitation (typ)
RON
ILIMH
IS
25mΩ
60A
2µA(1)
– Thermal shut down
– Reverse battery protection
(a)
Off state supply current
– Electrostatic discharge protection
1. Typical value with all loads connected
■ Features
Description
– In-rush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
The VND5025LAK-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology, intended for driving resistive or
inductive loads with one side connected to
ground, and suitable for driving LEDs.
– In compliance with the 2002/95/EC
Active V pin voltage clamp protects the device
European directive
CC
– Package: ECOPACK®
■ Diagnostic functions
against low energy spikes (see ISO7637 transient
compatibility table).
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open.
– Proportional load current sense
– High current sense precision for wide range
currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
■ Protection
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self-limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
Table 1.
Order codes
Package
PowerSSO-24™
Tube
VND5025LAK-E
Tape and Reel
VND5025LAKTR-E
a. See Figure 26: Application schematic
March 2007
Rev 3
1/31
www.st.com
1
Contents
VND5025LAK-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
2.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1
3.1.2
Solution 1: Resistor in the ground line (R
only) . . . . . . . . . . . . . . . . 21
GND
Solution 2: Diode (D
) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
GND
3.2
3.3
3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
µC I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . . 23
4
5
Package and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
5.2
5.3
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
VND5025LAK-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power section (8V < V < 36V; -40°C < T < 150°C, unless otherwise specified) . . . . . . . 8
CC
j
Switching (V = 13V; T = 25°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
j
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current sense (8V < V < 16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
VND5025LAK-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) and suggested connections for unused and N.C. pins . 5
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Delay response time between rising edge of ouput current and rising edge of current
sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6.
Figure 7.
Figure 8.
Figure 9.
I
/I
vs I
(see Table 9 for details) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OUT SENSE
OUT
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. On state resistance vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
case
Figure 18. On state resistance vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20.
I
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
LIMH
case
Figure 21. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. Maximum turn off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 28. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29.
R
vs PCB copper area in open box free air condition (with one channel ON). . . . . . 24
thj-amb
Figure 30. PowerSSO-24™ thermal impedance junction to ambient single pulse
(with one channel ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24™(1) . . . . . . . . . . . . . . . 26
Figure 32. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33. PowerSSO-24™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 34. PowerSSO-24™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/31
VND5025LAK-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
UNDERVOLTAGE
PwCLAMP 1
V
CC
CLAMP
OUTPUT1
CURRENT
SENSE1
GND
DRIVER 1
I
1
PwCLAMP 2
LIM
INPUT1
DRIVER 2
V
1
LOGIC
OUTPUT2
DSLIM
Pwr
1
LIM
I
2
LIM
CURRENT
SENSE2
OVERTEMP. 1
K 1
V
2
DSLIM
INPUT2
CS_DIS
I
OUT1
OVERTEMP. 2
K 2
I
OUT2
Pwr
2
LIM
Table 2.
Pin functions
Name
VCC
Function
Battery connection
Power output
OUTPUT1,2
GND
Ground connection; must be reverse battery protected by an external
diode/resistor network
Voltage controlled input pin with hysteresis, CMOS compatible; controls
output switch state
INPUT1,2
Analog current sense pin; delivers a current proportional to the load
current
CURRENT SENSE1,2
CS_DIS
Active high CMOS compatible pin to disable the current sense pin
Figure 2.
Configuration diagram (top view) and suggested connections for unused
and N.C. pins
V
CC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
9
10
11
12
CS_DIS.
V
CC
TAB = V
CC
Connection / Pin Current Sense
N.C.
X
Output
X
Input
CS_DIS
X
Floating
N.R.
X
To Ground
1kΩ resistor
X
N.R.
10kΩ resistor
10kΩ resistor
N.R. = Not recommended
5/31
Electrical characteristics
VND5025LAK-E
2
Electrical characteristics
Figure 3.
Current and voltage conventions
I
S
V
CC
V
(*)
F
V
CC
I
OUT1
I
I
I
CSD
OUTPUT1
CS_DIS
INPUT1
INPUT2
I
I
V
OUT1
V
SENSE1
CSD
IN1
CURRENT
SENSE1
I
V
OUT2
V
SENSE1
IN1
IN2
OUTPUT2
V
SENSE2
OUT2
V
IN2
CURRENT
SENSE2
GND
V
SENSE2
I
GND
(*) V = V
- V during reverse battery condition
CC
Fn
OUTn
6/31
VND5025LAK-E
Electrical characteristics
2.1
Absolute maximum ratings
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
-VCC
-IGND
IOUT
- IOUT
IIN
DC supply voltage
41
V
mA
A
Reverse DC supply voltage
DC reverse ground pin current
DC output current
0.3
200
Internally limited
24
Reverse DC output current
DC input current
-1 to 10
ICSD
DC current sense disable input current
mA
-ICSENSE DC reverse CS pin current
200
VCSENSE Current sense maximum voltage
VCC - 41 to +VCC
V
Maximum switching energy (single pulse)
(1)
EMAX
109
mJ
(L = 0.3mH; RL = 0Ω; Vbat = 13.5V; Tjstart = 150°C;
IOUT = IlimL(Typ.) )
Electrostatic Discharge
(Human Body Model: R = 1.5kΩ; C = 100pF)
- Input
4000
2000
4000
5000
5000
V
V
V
V
V
VESD
- Current sense
- CS_DIS
- Output
- VCC
VESD
Tj
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
Tstg
1. See Section 3.4 for details.
2.2
Thermal data
Table 4.
Symbol
Thermal data
Parameter
Max Value
Unit
Rthj-case Thermal resistance junction-case (MAX) (with one channel ON)
Rthj-amb Thermal resistance junction-ambient (MAX)
1.35
°C/W
See Figure 29
7/31
Electrical characteristics
Table 5.
VND5025LAK-E
Power section (8V < V < 36V; -40°C < T < 150°C, unless otherwise
CC
j
specified)
Symbol
Parameter
Test conditions
Min Typ Max Unit
Operating supply
voltage
VCC
VUSD
4.5 13
36
Undervoltage shutdown
3.5 4.5
0.5
V
Undervoltage shut-
down hysteresis
VUSDhyst
IOUT = 3A; Tj = 25°C
OUT = 3A; Tj = 150°C
25
RON
On state resistance(1)
I
50 mΩ
IOUT = 3A; VCC = 5V; Tj = 25°C
IS = 20 mA
35
Vclamp Clamp voltage
41 46
52
V
Off State; VCC = 13V; Tj = 25°C;
VIN = VOUT = VSENSE = VCSD = 0V
2(2) 5(2) µA
IS
Supply current
On State; VCC = 13V; VIN = 5V;
3
6
mA
µA
V
I
OUT = 0A
VIN = VOUT = 0V; VCC = 13V; Tj = 25°C
VIN = VOUT = 0V; VCC = 13V; Tj = 125°C
0
0
0.01
3
5
Off state output
current(1)
IL(off)
Output - VCC diode
voltage(1)
VF
-IOUT = 4A; Tj = 150°C
0.7
1. For each channel
2. PowerMOS leakage included
Table 6.
Symbol
td(on)
td(off)
Switching (V = 13V; T = 25°C)
CC j
Parameter
Test conditions Min
Typ
Max Unit
Turn-on delay time
Turn-off delay time
35
50
RL = 4.3Ω
(see Figure 8)
µs
(dVOUT/dt)on Turn-on voltage slope
(dVOUT/dt)off Turn-off voltage slope
(see Figure 21)
(see Figure 22)
RL = 4.3Ω
V/µs
mJ
Switching energy losses
WON
0.45
0.35
during tW
ON
RL = 4.3Ω
(see Figure 8)
Switching energy losses
WOFF
during tW
OFF
8/31
VND5025LAK-E
Electrical characteristics
Min Typ Max Unit
Table 7.
Logic input
Parameter
Symbol
Test conditions
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
0.9
V
µA
V
VIN = 0.9V
VIN = 2.1V
1
VIH
2.1
IIH
10
7
µA
VI(hyst)
0.25
5.5
I
IN = 1mA
IN = -1mA
VICL
Input clamp voltage
V
I
-0.7
VCSDL
ICSDL
VCSDH
ICSDH
CS_DIS low level voltage
Low level CS_DIS current
CS_DIS high level voltage
High level CS_DIS current
0.9
VCSD = 0.9V
VCSD = 2.1V
1
µA
V
2.1
10
7
µA
VCSD(hyst) CS_DIS hysteresis voltage
0.25
5.5
ICSD = 1mA
V
VCSCL
CS_DIS clamp voltage
ICSD = -1mA
-0.7
(1)
Table 8.
Symbol
Protection and diagnostics
Parameter
Test conditions
Min
Typ
Max
Unit
V
CC = 13V
43
60
ILIMH
DC short circuit current
85
5V < VCC < 36V
A
Short circuit current
during thermal cycling
VCC = 13V;
TR < Tj < TTSD
ILIML
24
TTSD
TR
Shutdown temperature
Reset temperature
150
175
200
TRS + 1 TRS + 5
135
°C
TRS
Thermal reset of STATUS
Thermal hysteresis
(TTSD-TR)
THYST
7
IOUT = 2A;
VIN = 0;
L = 6mH
Turn-off output voltage
clamp
VDEMAG
VCC - 41 VCC - 46 VCC - 52
V
IOUT = 0.2A;
Tj = -40°C to +150°C
(see Figure 9)
Output voltage drop
limitation
VON
40
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
9/31
Electrical characteristics
VND5025LAK-E
Table 9.
Symbol
Current sense (8V < V < 16V)
CC
Parameter
IOUT/ISENSE
IOUT/ISENSE
Test conditions
Min Typ Max Unit
IOUT = 0.05A; VSENSE = 0.5V; VCSD = 0V;
Tj = -40°C to 150°C
KLED
K0
1450 3300 5180
IOUT = 0.5A; VSENSE = 0.5V; VCSD = 0V;
Tj = -40°C to 150°C
1720 3020 4360
IOUT = 2A; VSENSE = 4V;
VCSD = 0V;
K1
IOUT/ISENSE
Tj = -40°C
1940 2810 3740
2230 2810 3390
Tj = 25°C to 150°C
IOUT = 2A; VSENSE = 4V;
VCSD = 0V;
Current sense
ratio drift
(1)
dK1/K1
-10
+10
%
Tj = -40°C to 150°C
IOUT = 3A; VSENSE = 4V;
VCSD = 0V;
K2
IOUT/ISENSE
Tj = -40°C
2250 2790 3450
2400 2790 3180
Tj = 25°C to150°C
IOUT = 3A; VSENSE = 4V; VCSD = 0V;
Tj = -40°C to 150°C
Current sense
ratio drift
(1)
dK2/K2
-7
+7
%
%
IOUT = 10A; VSENSE = 4V;
VCSD = 0V;
K3
IOUT/ISENSE
Tj = -40°C
2610 2760 2970
2650 2760 2870
Tj = 25°C to 150°C
IOUT = 10A; VSENSE = 4V; VCSD = 0V;
Tj = -40°C to 150°C
Current sense
ratio drift
(1)
dK3/K3
-3
+3
IOUT = 0A; VSENSE = 0V;
VCSD = 5V; VIN = 0V; Tj = -40°C to 150°C
VCSD = 0V; VIN = 5V; Tj = -40°C to 150°C
0
0
1
2
µA
µA
Analog sense
leakage current
ISENSE0
I
OUT = 2A; VSENSE = 0V;
VCSD = 5V; VIN = 5V; Tj = -40°C to 150°C
0
5
1
µA
V
Max analog
sense output
voltage
VSENSE
IOUT = 3A; VCSD = 0V
Analog sense
output voltage in
overtemperature
condition
VSENSEH
VCC = 13V; RSENSE = 3.9kΩ
9
8
Analog sense
output current in
overtemperature
condition
ISENSEH
VCC = 13V; VSENSE = 5V
mA
10/31
VND5025LAK-E
Electrical characteristics
Min Typ Max Unit
Table 9.
Symbol
Current sense (8V < V < 16V) (continued)
CC
Parameter
Test conditions
Delay response
time from falling
edge of CS_DIS
pin
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 90% of ISENSEMAX (see
Figure 4)
tDSENSE1H
tDSENSE1L
tDSENSE2H
50
5
100
20
Delay response
time from rising
edge of CS_DIS
pin
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 10% of ISENSEMAX (see
Figure 4)
Delay response
time from rising
edge of INPUT
pin
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 90% of ISENSEMAX (see
Figure 4)
70
300
µs
Delay response
time between
rising edge of
output current
VSENSE < 4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX, IOUTMAX = 3A
∆tDSENSE2H
110
and rising edge (see Figure 5)
of current sense
Delay response
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 10% of ISENSEMAX (see
Figure 4)
time from falling
edge of INPUT
pin
tDSENSE2L
100 250
1. Parameter guaranteed by design; it is not tested.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
t
t
t
t
DSENSE2L
DSENSE2H
DSENSE1L
DSENSE1H
11/31
Electrical characteristics
VND5025LAK-E
Delay response time between rising edge of ouput current and rising
Figure 5.
edge of current sense (CS enabled)
VIN
∆tDSENSE2H
t
t
t
IOUT
IOUTMAX
90% IOUTMAX
ISENSE
ISENSEMAX
90% ISENSEMAX
12/31
VND5025LAK-E
Figure 6.
Electrical characteristics
I
/I
vs I
(see Table 9 for details)
OUT SENSE
OUT
IOUT/ISENSE
4000
3500
3000
2500
2000
1500
1000
500
M ax -40°C to 150°C
M ax 25°C to 150°C
Typ 25°C
M in 25°C to 150°C
M in -40°C to 150°C
0
2
3
4
5
6
8
10
IOUT (A)
13/31
Electrical characteristics
Figure 7.
VND5025LAK-E
Maximum current sense ratio drift vs load current
dK/K (%)
15
10
5
0
-5
-10
-15
2
3
4
5
6
7
8
9
10
I
OUT (A)
Note: Parameter guaranteed by design; it is not tested.
Table 10. Truth table
Conditions
Input
Output
Sense (VCSD = 0V)(1)
L
H
L
L
0
Normal operation
H
Nominal
0
Overtemperature
Undervoltage
L
L
H
L
VSENSEH
0
H
L
0
Short circuit to GND (RSC ≤ 10mΩ)
L
0 if Tj < TTSD
H
VSENSEH if Tj > TTSD
L
H
L
0
< Nominal
0
Short circuit to VCC
H
L
Negative output voltage clamp
1. If the VCSD is high, the SENSE output is at a high impedance; its potential depends on leakage currents
and external circuit.
14/31
VND5025LAK-E
Figure 8.
Electrical characteristics
Switching characteristics
t
t
V
Woff
Won
OUT
90%
80%
dV
/dt
dV
/dt
OUT (off)
OUT (on)
t
t
10%
r
f
t
INPUT
t
t
d(on)
d(off)
t
Figure 9.
Output voltage drop limitation
- V
V
CC
OUT
o
o
T = 150 C
j
T = 25 C
j
o
T = -40 C
j
V
on
I
OUT
V /R
on on(T)
15/31
Electrical characteristics
VND5025LAK-E
Table 11. Electrical transient requirements
Burst cycle/pulse
repetition time
Test levels(1)
ISO 7637-2:
2004(E)
Test pulse
Number of
pulses or
test times
Delays and
Impedance
III
IV
Min
Max
1
2a
3a
3b
4
-75V
+37V
-100V
+75V
-6V
-100V
+50V
-150V
+100V
-7V
5000 pulses
5000 pulses
1h
0.5s
0.2s
5s
2 ms, 10Ω
50µs, 2Ω
5s
90ms
90ms
100ms
100ms
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
1h
1 pulse
1 pulse
5b(2)
+65V
+87V
ISO 7637-2:
2004E
Test pulse
Test level results
III
VI
1
2a
3a
3b
4
C
C
C
C
C
C
C
C
C
C
C
C
5b(2)
Class
Contents
C
All functions of the device performed as designed after exposure to disturbance.
One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
16/31
VND5025LAK-E
Figure 10. Waveforms
Electrical characteristics
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
V
USDhyst
V
CC
V
USD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO V
CC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
< Nominal
< Nominal
OVERLOAD OPERATION
T
T
TSD
T
R
RS
T
j
INPUT
CS_DIS
I
I
LIMH
LIML
LOAD CURRENT
V
SENSEH
SENSE CURRENT
Thermal cycling
Current
limitation
Power
limitation
SHORTED LOAD
NORMAL LOAD
17/31
Electrical characteristics
VND5025LAK-E
Figure 11. Off state output current
Figure 12. High level input current
Iih(uA)
5
Iloff (uA)
0.5
4.5
4
0.45
Off State
Vcc=13V
Vin=Vout=0V
Vin=2.1V
0.4
0.35
0.3
3.5
3
2.5
2
0.25
0.2
1.5
1
0.15
0.1
0.5
0.05
0
0
-50
-25
0
25
50
75
100
125
150
175
175
175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C)
Tc (°C)
Figure 13. Input clamp voltage
Figure 14. Input high level
Vicl (V)
7
Vih (V)
4
6.75
3.5
3
Iin=1mA
6.5
6.25
6
2.5
2
5.75
5.5
5.25
5
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
150
Tc (°C)
Tc (°C)
Figure 15. Input low level
Figure 16. Input hysteresis voltage
Vil (V)
2
Vhyst (V)
1
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
150
Tc (°C)
Tc (°C)
18/31
VND5025LAK-E
Electrical characteristics
Figure 17. On state resistance vs T
Figure 18. On state resistance vs V
CC
case
Ron (mOhm)
100
Ron (mOhm)
80
90
70
60
50
40
30
20
10
0
Iout=3A
Vcc=13V
80
70
60
50
40
30
20
10
0
Tc=150°C
Tc= 125°C
Tc= 25°C
Tc= -40°C
-50
-25
0
25
50
75
100
125
150
175
0
5
10
15
20
25
30
35
40
Tc (°C)
Vcc (V)
Figure 19. Undervoltage shutdown
Figure 20. I
vs T
LIMH case
Vusd (V)
16
Ilimh (A)
100
90
80
70
60
50
40
30
20
10
14
12
10
8
Vcc=13V
6
4
2
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 21. Turn-on voltage slope
Figure 22. Turn-off voltage slope
(dVout/dt)on (V/ms)
1000
(dVout/dt)off (V/ms)
1000
900
900
Vcc=13V
Rl=4.3Ohm
Vcc=13V
Rl=4.3Ohm
800
800
700
700
600
500
400
300
200
100
0
600
500
400
300
200
100
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
19/31
Electrical characteristics
VND5025LAK-E
Figure 23. CS_DIS high level voltage
Figure 24. CS_DIS low level voltage
Vcsdh (V)
4
Vcsdl (V)
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 25. CS_DIS clamp voltage
Vcsdcl (V)
8
7.5
Icsd=1mA
7
6.5
6
5.5
5
4.5
4
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
20/31
VND5025LAK-E
Application information
3
Application information
Figure 26. Application schematic
+5V
V
CC
R
prot
CS_DIS
D
ld
R
µC
INPUT
prot
OUTPUT
R
CURRENT SENSE
prot
GND
R
R
GND
SENSE
V
C
D
GND
EXT
GND
Note: Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1
Solution 1: Resistor in the ground line (R
only)
GND
This first solution can be used with any type of load.
The following formulas indicate how to dimension the R
resistor:
GND
1.
2.
R
R
≤ 600mV / (I
)
S(on)max
GND
GND
≥ (-V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power Dissipation in R
(when V < 0 during reverse battery situations) is:
GND
CC
2
P = (-V ) / R
D
CC
GND
This resistor can be shared among several different HSDs. Please note that the value of this
resistor is calculated with formula (1), where I
state currents of the different devices.
becomes the sum of the maximum on-
S(on)max
Please note that if the microprocessor ground is not shared by the device ground, the R
GND
produces a shift (I
* R
) in the input thresholds and the status output values. This
S(on)max
GND
shift varies depending on how many devices are ON in the case of several high-side drivers
sharing the same R
.
GND
21/31
Application information
VND5025LAK-E
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor, then ST suggests to utilize the following Solution 2.
3.1.2
Solution 2: Diode (D
) in the ground line
GND
If the device drives an inductive load, insert a resistor (R
= 1kΩ) in parallel to D
.
GND
GND
This small signal diode can be safely shared among several different HSDs. Also in this
case, the presence of the ground network produces a shift (j600mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
ld
V
maximum DC rating. The same applies if the device is subject to transients on the V
CC
CC
line that are greater than the ones shown in the ISO 7637-2:2004E table.
µC I/Os protection
If a ground protection network is used and negative transients are present on the V line,
CC
the control pins are pulled negative. ST suggests to insert an in-line resistor (R ) to
prot
prevent the µC I/Os pins from latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (input levels compatibility) with the latch-up limit of µC
I/Os.
-V
/I
≤ R
≤ (V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND IHmax
Calculation example:
For V = -100V and I
≥ 20mA; V ≥ 4.5V
OHµC
CCpeak
latchup
5kΩ ≤ R
≤ 65kΩ
prot
Recommended values: R
= 10kΩ, C
= 10nF
EXT
prot
22/31
VND5025LAK-E
Application information
3.4
Maximum demagnetization energy (VCC = 13.5V)
Figure 27. Maximum turn off current versus inductance (for each channel)
ILMAX (A)
100
10
1
A
B
C
0.1
1
10
100
L (mH)
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R = 0Ω
L
In case of repetitive pulses, T
(at beginning of each demagnetization) of every pulse
jstart
must not exceed the temperature specified above for curves A and B.
23/31
Package and thermal data
VND5025LAK-E
4
Package and thermal data
4.1
PowerSSO-24™ thermal data
Figure 28. PowerSSO-24™ PC board
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 area = 77mm x 86mm, PCB
th
th
2
thickness = 1.6mm, Cu thickness = 70µm (front and back side), Copper areas: from minimum pad layout to 8cm ).
Figure 29. R
vs PCB copper area in open box free air condition (with one
thj-amb
channel ON)
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
24/31
VND5025LAK-E
Package and thermal data
Figure 30. PowerSSO-24™ thermal impedance junction to ambient single pulse
(with one channel ON)
ZTH (°C/W)
1000
100
10
1
Footprint
2 cm2
8 cm2
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Pulse calculation formula:
= RTH ⋅ δ + ZTHtp(1 – δ)
Z
THδ
δ = t ⁄ T
where
p
25/31
Package and thermal data
VND5025LAK-E
(1)
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24™
1. Values are given in Table 12
Table 12. Thermal parameters
Area/Island (cm2)
Footprint
2
8
R1 (°C/W)
0.28
0.9
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
R7 (°C/W)
R8 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
C7 (W.s/°C)
C8 (W.s/°C)
6
7.7
9
9
8
28
17
10
0.28
0.9
0.001
0.003
0.025
0.75
1
4
5
9
2.2
17
0.001
0.003
26/31
VND5025LAK-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
®
packages. ECOPACK packages are lead-free. The category of Second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
5.2
Package mechanical
Table 13. PowerSSO-24™ mechanical data
Millimeters
Symbol
Min
Typ
Max
A
A2
a1
b
1.9
1.9
2.22
2.15
0.07
0.46
0.32
10.4
7.6
0
0.34
0.23
10.2
7.4
0.4
c
D
E
e
0.8
8.8
e3
G
G1
H
h
0.1
0.06
10.5
0.4
10.1
0.55
L
0.85
10°
4.3
N
X
3.9
6.1
Y
6.5
27/31
Package and packing information
Figure 32. PowerSSO-24™ package dimensions
VND5025LAK-E
28/31
VND5025LAK-E
Package and packing information
5.3
Packing information
Figure 33. PowerSSO-24™ tube shipment (no suffix)
Base Qty
Bulk Qty
Tube length ( 0.5)
A
49
1225
532
3.5
C
B
B
13.8
0.6
C ( 0.1)
All dimensions are in mm.
A
Figure 34. PowerSSO-24™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
C ( 0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
12
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.55
1.5
11.5
2.85
2
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
No components
500mm min
Top
cover
tape
No components Components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
29/31
Revision history
VND5025LAK-E
6
Revision history
Table 14. Document revision history
Date
Revision
Changes
16-Feb-2007
1
Initial release
Table 9: Current sense (8V < VCC < 16V): Error in dK3/K3 current
sense ratio drift row corrected.
23-Feb-2007
28-Mar-2007
2
3
Protection section updated to correct editing error.
30/31
VND5025LAK-E
Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
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Information in this document supersedes and replaces all information previously supplied.
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31/31
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