VN800PT [STMICROELECTRONICS]
HIGH SIDE DRIVER; 高端驱动器
| 型号： | VN800PT |
| 厂家： | 
ST |
| 描述： | HIGH SIDE DRIVER |
| 文件： | 总22页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VN800S(8961)
/ VN800PT(8961)
®
HIGH SIDE DRIVER
TYPE
R
I
V
CC
DS(on)
OUT
VN800S(8961)
VN800PT(8961)
135 mΩ
1.2 A
36 V
■ CMOS COMPATIBLE INPUT
■ THERMAL SHUTDOWN
■ CURRENT LIMITATION
■ SHORTED LOAD PROTECTION
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ PROTECTION AGAINST LOSS OF GROUND
■ VERY LOW STAND-BY CURRENT
SO-8
ORDER CODES
PPAK
PACKAGE
TUBE
T&R
SO-8
PPAK
VN800S(8961) VN800S(8961)TR
VN800PT(8961) VN800PT(8961)TR
■ REVERSE BATTERY PROTECTION (*)
DESCRIPTION
compatibility table). Active current limitation
combined with thermal shutdown and automatic
restart protect the device against overload.
Device automatically turns off in case of ground
pin disconnection.
The VN800S(8961), VN800PT(8961) are
monolithic
devices
made
by
using
STMicroelectronics VIPower M0-3 Technology,
intended for driving any kind of load with one side
connected to ground.
Active VCC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
BLOCK DIAGRAM
V
CC
OVERVOLTAGE
DETECTION
V
CC
CLAMP
UNDERVOLTAGE
DETECTION
GND
Power CLAMP
DRIVER
OUTPUT
LOGIC
INPUT
CURRENT LIMITER
STATUS
OVERTEMPERATURE
DETECTION
(*) See note at page 8
July 2002
1/22
VN800S(8961) / VN800PT(8961)
ABSOLUTE MAXIMUM RATING
Value
Symbol
Parameter
Unit
SO-8
PPAK
V
DC Supply Voltage
41
V
V
CC
- V
Reverse DC Supply Voltage
DC Reverse Ground Pin Current
DC Output Current
- 0.3
- 200
CC
GND
OUT
- I
mA
A
I
Internally Limited
- I
Reverse DC Output Current
DC Input Current
- 6
A
OUT
I
+/- 10
mA
V
IN
V
Input Voltage Range
-3/+V
CC
IN
V
DC Status Voltage
+ V
V
STAT
CC
Electrostatic Discharge (Human Body Model: R=1.5KΩ; C=100pF)
- INPUT
4000
4000
5000
5000
V
V
V
V
V
- STATUS
ESD
- OUTPUT
- V
CC
Maximum Switching Energy
(L=77.5mH; R =0Ω; V =13.5V; T
E
121
4.2
mJ
mJ
MAX
=150ºC; I =1.5A)
L
bat
jstart
L
Maximum Switching Energy
(L=125mH; R =0Ω; V =13.5V; T
E
195
MAX
=150ºC; I =1.5A)
L
bat
jstart
L
P
Power Dissipation T =25°C
41.7
W
°C
°C
°C
tot
C
T
Junction Operating Temperature
Case Operating Temperature
Storage Temperature
Internally Limited
- 40 to 150
j
T
c
T
- 55 to 150
stg
Max Inductive Load (V =30V; R
=48Ω; T
=100°C;
amb
CC
LOAD
L
2
H
max
Rth
≤25°C/W)
case>ambient
CONNECTION DIAGRAM (TOP VIEW)
VCC
5
4
3
2
OUTPUT
STATUS
VCC
N.C.
5
4
STATUS
INPUT
GND
OUTPUT
OUTPUT
VCC
INPUT
GND
1
8
1
SO-8
PPAK
CURRENT AND VOLTAGE CONVENTIONS
IS
IIN
VCC
GND
INPUT
ISTAT
IOUT
STATUS
VCC
OUTPUT
VIN
VOUT
VSTAT
IGND
2/22
VN800S(8961) / VN800PT(8961)
THERMAL DATA
Symbol
Value
Unit
Parameter
SO-8
-
PPAK
R
Thermal Resistance Junction-case
Thermal Resistance Junction-lead
3
-
°C/W
°C/W
°C/W
Max
Max
Max
thj-case
R
R
30
thj-lead
thj-amb
Thermal Resistance Junction-ambient
93 (*)
78 (**)
2
(*) When mounted on FR4 printed circuit board with 0.5 cm of copper area (at least 35µ thick) connected to all V pins.
CC
2
(**) When mounted on FR4 printed circuit board with 0.5 cm of copper area (at least 35µ thick).
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified)
POWER
Symbol
Parameter
Test Conditions
Min
5.5
3
Typ
Max
36
Unit
V
V
Operating Supply Voltage
Undervoltage Shut-down
Overvoltage Shut-down
CC
V
4
5.5
V
USD
V
36
V
OV
I
I
=0.5A; T =25°C
135
270
20
mΩ
mΩ
µA
mA
mA
OUT
OUT
j
R
On State Resistance
ON
=0.5A
Off State; V =24V; T
=25°C
10
CC
case
I
Supply Current
On State; V =24V
1.5
3.5
2.6
S
CC
On State; V =24V; T
=100°C
CC
case
V
V
V
V
V
=V
=V =V
=24V
CC
STAT
IN
GND
I
Output Current at turn-off
1
mA
LGND
=0V
OUT
I
Off State Output Current
Off State Output Current
Off State Output Current
=V
=0V
0
50
5
µA
µA
µA
L(off1)
IN
IN
IN
OUT
OUT
OUT
I
=V
=V
=0V; Vcc=13V; T =125°C
j
L(off2)
I
=0V; Vcc=13V; T =25°C
3
L(off3)
j
SWITCHING (VCC=24V)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
R =48Ω from V rising edge to
L
IN
t
t
Turn-on Delay Time
Turn-off Delay Time
10
µs
d(on)
d(off)
V
=2.4V
OUT
R =48Ω from V falling edge to
L
IN
40
µs
V
=21.6V
OUT
See
relative
diagram
dV
dt
/
/
R =48Ω from V
=2.4V to
OUT
(on)
L
OUT
Turn-on Voltage Slope
Turn-off Voltage Slope
V/µs
V
=19.2V
OUT
See
relative
diagram
dV
dt
R =48Ω from V
=21.6V to
OUT
(off)
L
OUT
V/µs
V
=2.4V
OUT
INPUT PIN
Symbol
Parameter
Input Low Level
Test Conditions
Min
Typ
Max
Unit
V
V
1.25
INL
I
Low Level Input Current
Input High Level
V
V
V
=1.25V
1
µA
V
INL
IN
IN
IN
V
3.25
INH
INH
I
High Level Input Current
Input Hysteresis Voltage
Input Current
=3.25V
=V =36V
10
µA
V
V
0.5
I(hyst)
I
200
µA
IN
CC
3/22
1
VN800S(8961) / VN800PT(8961)
ELECTRICAL CHARACTERISTICS (continued)
STATUS PIN
Symbol
Parameter
Test Conditions
=1.6 mA
STAT
Min
Typ
Max
0.5
10
Unit
V
V
Status Low Output Voltage I
Status Leakage Current
STAT
I
Normal Operation; V
=V =36 V
µA
LSTAT
STAT
CC
Status Pin Input
Capacitance
C
Normal Operation; V
= 5V
30
pF
STAT
STAT
PROTECTIONS
Symbol
Parameter
Test Conditions
Min
150
135
7
Typ
Max
Unit
°C
T
Shut-down Temperature
Reset Temperature
Thermal Hysteresis
175
200
TSD
T
°C
R
T
15
°C
hyst
Status Delay in Overload
Condition
T
T >T
20
2
µs
A
SDL
j
jsh
I
DC Short Circuit Current
Turn-off Output Clamp
Voltage
V
=16V; R =10mΩ
LOAD
1.2
lim
CC
V
I
=0.5 A; L=6mH
V
-47
V
-52
V -57
CC
V
demag
OUT
CC
CC
OVERTEMP STATUS TIMING
T >T
V
j
jsh
IN
V
STAT
t
t
SDL
SDL
4/22
2
VN800S(8961) / VN800PT(8961)
Switching time Waveforms
V
OUT
90%
80%
dV
/dt
dV
/dt
OUT (off)
OUT (on)
10%
t
t
f
r
t
V
IN
t
d(on)
t
d(off)
t
TRUTH TABLE
CONDITIONS
INPUT
OUTPUT
STATUS
L
H
L
H
H
H
Normal Operation
L
H
H
L
X
X
H
) H
) L
Current Limitation
(T < T
j
TSD
TSD
(T > T
j
L
H
L
L
H
L
Overtemperature
Undervoltage
Overvoltage
L
H
L
L
X
X
L
H
L
L
H
H
5/22
VN800S(8961) / VN800PT(8961)
Figure 1: Peak Short Circuit Current Test Circuit
+V
CC
10kΩ
V
CC
STATUS
INPUT
CONTROL
UNIT
OUTPUT
R
IN
GND
R =10mΩ
L
GND
Figure 2: Avalanche Energy Test Circuit
+V
CC
10kΩ
V
CC
STATUS
INPUT
CONTROL
UNIT
OUTPUT
R
IN
GND
LOAD
GND
6/22
VN800S(8961) / VN800PT(8961)
ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN
TEST LEVELS
ISO T/R 7637/1
Test Pulse
Delays and
Impedance
I
II
III
IV
1
2
-25 V
+25 V
-25 V
-50 V
+50 V
-50 V
-75 V
+75 V
-100 V
+75 V
-6 V
-100 V
+100 V
-150 V
+100 V
-7 V
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
3a
3b
4
+25 V
-4 V
+50 V
-5 V
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
ISO T/R 7637/1
TEST LEVELS RESULTS
I
II
III
C
C
C
C
C
E
IV
C
C
C
C
C
E
Test Pulse
1
2
C
C
C
C
C
C
C
C
C
C
C
E
3a
3b
4
5
CLASS
CONTENTS
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
7/22
VN800S(8961) / VN800PT(8961)
APPLICATION SCHEMATIC
VCC
VCC
24VDC
5V
Vol t.
Reg
Rprot
STATUS
D
id
INPUT
OUTPUT
R
Rprot
BUS
ASIC
LOAD
GND
L
DGND
RGND
VGND
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift ( 600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
GND PROTECTION NETWORK AGAINST
REVERSE BATTERY
Solution 1: Resistor in the ground line (R
can be used with any type of load.
only). This
GND
The following is an indication on how to dimension the
R
resistor.
GND
1) R
2) R
where -I
≤ 600mV / (I
).
S(on)max
LOAD DUMP PROTECTION
GND
GND
≥ (−V ) / (-I
)
CC
GND
D
is necessary (Voltage Transient Suppressor) if the
ld
is the DC reverse ground pin current and can
load dump peak voltage exceeds V max DC rating. The
GND
CC
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in R
battery situations) is:
same applies if the device will be subject to transients on
the V
line that are greater than the ones shown in the
CC
ISO T/R 7637/1 table.
(when V <0: during reverse
CC
GND
µC I/Os PROTECTION:
2
P = (-V ) /R
D
CC
GND
If a ground protection network is used and negative
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
transients are present on the V line, the control pins will
CC
be pulled negative. ST suggests to insert a resistor (R
)
prot
calculated with formula (1) where I
becomes the
in line to prevent the µC I/Os pins to latch-up.
S(on)max
sum of the maximum on-state currents of the different
devices.
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up limit
of µC I/Os.
Please note that if the microprocessor ground is not
common with the device ground then the R
will
GND
produce a shift (I
* R
) in the input thresholds
S(on)max
GND
-V
/I
≤ R
≤ (V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND
IHmax
and the status output values. This shift will vary
depending on many devices are ON in the case of several
Calculation example:
high side drivers sharing the same R
.
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
CCpeak
latchup
OHµC
GND
If the calculated power dissipation leads to a large resistor
or several devices have to share the same resistor then
the ST suggests to utilize Solution 2 (see below).
5kΩ ≤ R
Recommended R
≤ 65kΩ.
prot
value is 10kΩ.
prot
Solution 2: A diode (D
) in the ground line.
GND
A resistor (R
GND
=1kΩ) should be inserted in parallel to
GND
D
if the device will be driving an inductive load.
8/22
VN800S(8961) / VN800PT(8961)
Figure 3: Waveforms
NORMAL OPERATION
UNDERVOLTAGE
INPUT
LOAD VOLTAGE
STATUS
V
V
USDhyst
CC
V
USD
INPUT
LOAD VOLTAGE
STATUS
undefined
OVERVOLTAGE
V
<V
OV
V
>V
OV
CC
CC
V
CC
INPUT
LOAD VOLTAGE
STATUS
OVERTEMPERATURE
T
T
TSD
R
T
j
INPUT
LOAD CURRENT
STATUS
9/22
VN800S(8961) / VN800PT(8961)
High Level Input Current
Off State Output Current
IL(off1) (µA)
Iih (µA)
2.5
8
2.25
7
Off state
Vin=3.25V
2
Vcc=36V
Vin=Vout=0V
6
1.75
5
4
3
2
1
0
1.5
1.25
1
0.75
0.5
0.25
0
-50
-25
0
25
50
75
100 125 150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
ILIM Vs Tcase
Status Leakage Current
Ilim (A)
Ilstat (µA)
2.5
0.1
2.25
2
0.09
Vstat=Vcc=36V
Vcc=24V
Rl=10mOhm
0.08
1.75
1.5
1.25
1
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.75
0.5
0.25
0
-50
-25
0
25
50
75
100 125 150
175
-50
-25
0
25
50
75
100 125 150
175
Tc (ºC)
Tc (ºC)
On State Resistance Vs Tcase
On State Resistance Vs VCC
Ron (mOhm)
Ron (mOhm)
400
400
350
350
Iout=0.5A
Iout=0.5A
Vcc=8V; 13V; 36V
300
300
250
200
150
100
50
250
200
150
100
50
Tc= 150ºC
Tc= 25ºC
Tc= - 40ºC
0
0
-50
-25
0
25
50
75
100 125
150
175
5
10
15
20
25
30
35
40
Tc (ºC)
Vcc (V)
10/22
VN800S(8961) / VN800PT(8961)
Input High Level
Input Low Level
Vil (V)
Vih (V)
3.6
2.6
2.4
2.2
2
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Input Hysteresis Voltage
Overvoltage Shutdown
Vov (V)
Vhyst (V)
50
1.5
48
46
44
42
40
38
36
34
32
30
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Turn-on Voltage Slope
Turn-off Voltage Slope
dVout/dt(off) (V/ms)
dVout/dt(on) (V/ms)
800
1600
700
1400
Vcc=24V
Vcc=24V
Rl=48Ohm
Rl=48Ohm
600
1200
500
400
300
200
100
0
1000
800
600
400
200
0
-50
-25
0
25
50
75
100 125
150
175
-50
-25
0
25
50
75
100 125 150 175
Tc (ºC)
Tc (ºC)
11/22
VN800S(8961) / VN800PT(8961)
PPAK Maximum turn off current versus load inductance
LMAX (A)
I
10
A
B
1
C
0.1
1
10
100
1000
L(mH)
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
12/22
VN800S(8961) / VN800PT(8961)
SO-8 Maximum turn off current versus load inductance
LMAX (A)
I
10
A
B
1
C
0.1
1
10
100
1000
L(mH)
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
13/22
VN800S(8961) / VN800PT(8961)
SO-8 THERMAL DATA
SO-8 PC Board
Layout condition of R and Z measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
th
th
2
2
Cu thickness=35µm, Copper areas: 0.14cm , 2cm ).
Rthj-amb Vs PCB copper area in open box free air condition
RTHj_amb (ºC/W)
SO8 at 2 pins connected to TAB
110
105
100
95
90
85
80
75
70
0
0.5
1
1.5
2
2.5
PCB Cu heatsink area (cm^2)
14/22
VN800S(8961) / VN800PT(8961)
PPAK THERMAL DATA
PPAK PC Board
Layout condition of R and Z measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm,
th
th
2
2
Cu thickness=35µm, Copper areas: 0.44cm , 8cm ).
Rthj-amb Vs PCB copper area in open box free air condition
(ºC/W)
RTHj_amb
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
15/22
VN800S(8961) / VN800PT(8961)
PPAK Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
2
100
10
1
0.44 cm
2
6 cm
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Thermal fitting model of a single channel HSD
in PPAK
Pulse calculation formula
ZTHδ = RTH δ + ZTHtp(1 – δ)
δ = tp ⁄ T
where
Thermal Parameter
2
Area/island (cm )
R1 (°C/W)
0.44
0.04
0.25
0.3
6
24
5
Tj
R2 (°C/W)
C1
R1
C2
R2
C3
R3
C4
R4
C5
R5
C6
R6
R3 ( °C/W)
R4 (°C/W)
2
R5 (°C/W)
15
Pd
R6 (°C/W)
61
T_amb
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.0008
0.007
0.02
0.3
0.45
0.8
16/22
VN800S(8961) / VN800PT(8961)
SO-8 Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
2
0.5 cm
100
10
1
2
2 cm
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Thermal fitting model of a single channel HSD
in SO-8
Pulse calculation formula
ZTHδ = RTH δ + ZTHtp(1 – δ)
δ = tp ⁄ T
where
Thermal Parameter
2
Area/island (cm )
R1 (°C/W)
0.14
0.24
2
28
2
Tj
R2 (°C/W)
1.2
C1
R1
C2
R2
C3
R3
C4
R4
C5
R5
C6
R6
R3 ( °C/W)
R4 (°C/W)
4.5
21
R5 (°C/W)
16
Pd
R6 (°C/W)
58
T_amb
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.00015
0.0005
7.50E-03
0.045
0.35
1.05
17/22
VN800S(8961) / VN800PT(8961)
SO-8 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
1.75
0.25
1.65
0.85
0.48
0.25
0.5
MIN.
MAX.
0.068
0.009
0.064
0.033
0.018
0.010
0.019
A
a1
a2
a3
b
0.1
0.003
0.65
0.35
0.19
0.25
0.025
0.013
0.007
0.010
b1
C
c1
D
45 (typ.)
4.8
5.8
5
0.188
0.228
0.196
0.244
E
6.2
e
1.27
3.81
0.050
0.150
e3
F
3.8
0.4
4
0.14
0.157
0.050
0.023
L
1.27
0.6
0.015
M
S
8 (max.)
L1
0.8
1.2
0.031
0.047
18/22
VN800S(8961) / VN800PT(8961)
PPAK MECHANICAL DATA
DIM.
MIN.
2.20
0.90
0.03
0.40
5.20
0.45
0.48
TYP
MAX.
2.40
1.10
0.23
0.60
5.40
0.60
0.60
A
A1
A2
B
B2
C
C2
D1
5.1
D
6.00
6.40
6.20
6.60
E
E1
4.7
e
1.27
G
4.90
2.38
9.35
5.25
2.70
10.10
1.00
1.00
G1
H
L2
0.8
0.2
L4
0.60
R
V2
0º
8º
Package Weight
Gr. 0.3
P032T1
19/22
VN800S(8961) / VN800PT(8961)
SO-8 TUBE SHIPMENT (no suffix)
B
Base Q.ty
100
2000
532
3.2
6
C
A
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
0.6
All dimensions are in mm.
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
W
P0 (± 0.1)
P
12
4
Tape Hole Spacing
Component Spacing
Hole Diameter
8
D (± 0.1/-0) 1.5
Hole Diameter
D1 (min)
F (± 0.05)
K (max)
1.5
5.5
4.5
2
Hole Position
Compartment Depth
Hole Spacing
P1 (± 0.1)
End
All dimensions are in mm.
Start
Top
No components
500mm min
Components
No components
cover
tape
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
20/22
VN800S(8961) / VN800PT(8961)
PPAK TUBE SHIPMENT (no suffix)
A
C
Base Q.ty
75
3000
532
6
Bulk Q.ty
Tube length (± 0.5)
A
B
B
21.3
0.6
C (± 0.1)
All dimensions are in mm.
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
Base Q.ty
2500
2500
330
1.5
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
13
20.2
16.4
60
G (+ 2 / -0)
N (min)
T (max)
22.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
W
P0 (± 0.1)
P
16
4
Tape Hole Spacing
Component Spacing
Hole Diameter
8
D (± 0.1/-0) 1.5
Hole Diameter
D1 (min)
F (± 0.05)
K (max)
1.5
7.5
6.5
2
Hole Position
Compartment Depth
Hole Spacing
P1 (± 0.1)
End
All dimensions are in mm.
Start
Top
No components
500mm min
Components
No components
cover
tape
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
21/22
1
VN800S(8961) / VN800PT(8961)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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2002 STMicroelectronics - Printed in ITALY- All Rights Reserved.
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22/22
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