TSA1041IF [STMICROELECTRONICS]
4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48, 7 X 7 MM, TQFP-48;
| 型号： | TSA1041IF |
| 厂家： | 
ST |
| 描述： | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48, 7 X 7 MM, TQFP-48 转换器 |
| 文件： | 总14页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSA1041
OPTIMWATTTM 4-CHANNEL 10-BIT 50MSPS A/D CONVERTER
PRELIMINARY DATA
FEATURES
ORDER CODE
TM
1
■ OPTIMWATT features
Temperature
Range
- Power down device
Part Number
Package
Conditioning
Marking
- Adjustable consumption versus speed.
TSA1041IF
-40°C to +85°C
-40°C to +85C
TQFP48
TQFP48
Tray
SA1041I
SA1041I
- Ultra low power consumption:
TSA1041IFT
EVAL1041/AA
Tape & Reel
440mW@50Msps,
380mW @40Msps.
Evaluation board
■ 4 differential analog inputs
■ Input voltage range: typ 2Vpp differential
■ 69dBFS SFDR at Fin=10MHz
■ 9.5 ENOB at Fin=10MHz
PIN DESCRIPTION
■ Serial Data Outputs, LVDS Ouputs
■ Mode Pattern for test/synchronisation
■ Built-in reference voltage with external bias
capability
index
corner
37
48 47 46 45 44 43 42 41 40 39 38
1
36 AVDD
AVDD
REFP
REFM
INCM
AGND
AVDD
35
2
AGND
■ Single supply voltage: 2.5V
3
4
5
PDD
34
33
32
1) OPTIMWATT(TM) is a ST deposited trademark for products features allowing
optimization of power efficiency at chip/application level.
SPEED
DVDD
DESCRIPTION
31
30
29
28
6
7
DGND
CLK
TSA1041
TQFP48
REFMODE
The TSA1041 uses a high density advanced deep
submicron CMOS process, to integrate four High
Speed A/D converters in one circuit. It achieves
simultaneous conversion of four differential inputs
with a resolution of 10 bits at 50MHz maximum
sampling frequency.
SYNCMODE
8
LOCK
DGND
DVDD
VSS
VSS
VDD
9
10
11
12
27
26
VSS
VDD
25
VDD
13 14 15 16 17 18 19 20 21 22 23 24
The device has an internal PLL to generate 10
times the sampling frequency, used for the
serialization of the 10 bits wide data per channel.
Thus it delivers 40 data on only 8 wires
corresponding to four serialized data LVDS
outputs. The number of pins is limited and the four
ADCs of the TSA1041 fit in a small TQFP48,
reducing board size and simplifying PCB layout.
Moreover the use of LVDS outputs reduces the
noise.
PACKAGE
7 x 7 mm TQFP48
Special care is given to minimize power
consumption at the application by selecting the
proper consumption for
frequency.
a
given sampling
The TSA1041 is available in extended (-40 to
+85°C) temperature range.
APPLICATIONS
■ Medical imaging and ultrasound
■ Portable instrumentation
■ Cable Modem Receivers
■ High resolution fax and scanners
■ High speed DSP interface
■ Particle detector
■ High-end cameras
December 2003
1/14
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TSA1041
BLOCK DIAGRAM
2/14
TSA1041
PIN DIAGRAM
index
corner
37
48 47 46 45 44 43 42 41 40 39 38
1
36 AVDD
AVDD
REFP
REFM
INCM
AGND
AVDD
35
AGND
2
3
PDD
34
33
32
4
5
SPEED
DVDD
TSA1041
TQFP48
31
30
29
28
6
7
DGND
CLK
REFMODE
SYNCMODE
8
9
LOCK
DGND
DVDD
VSS
VSS
VDD
10
11
12
27
26
VSS
VDD
25
VDD
13 14 15 16 17 18 19 20 21 22 23 24
TSA1041 PINS DESCRIPTION
Pin Name
I/O
No
Pin Description
IN1+
IN1-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
47
Analog Input Channel 1
48
Inverted Analog Input Channel 1
Analog Input Channel 2
IN2+
44
IN2-
45
40
Inverted Analog Input Channel 2
Analog Input Channel 3
IN3+
IN3-
41
Inverted Analog Input Channel 3
Analog Input Channel 4
IN4+
37
IN4-
38
Inverted Analog Input Channel 4
Analog Power Supply (2.5V).
Analog Ground
AVDD
AGND
VDD
1,6,36,42
5,35,39,43,46
10,12,25
9,11,26
30
Digital Power supply (2.5V) - I/O LVDS.
Digital Ground - I/O LVDS
VSS
CLK
CMOS Clock Input
DVDD
DGND
SYNCMODE
27,32
28,31
8
Digital Power Supply (2.5V).
Digital ground
High level enables test pattern(1000101010).
REFMODE=’0’, internal references active.
REFMODE=‘1’, external references must be applied.
REFMODE
I
7
Internal Common Mode - may be used as a voltage generator
output for input signal common mode (Refmode=0) or used as an
input to force the internal common mode (Refmode=1)
INCM
RefM
I/O
I
4
3
Bottom Reference Voltage. Usually connected to GND (may be
forced to another value to adjust the full scale)
3/14
TSA1041
Top Reference Voltage - may be used as a voltage generator output
(1V) or used as an input to adjust the input dynamic range
(VIN-VINB=2x(VREFP-VREFM)).
RefP
I/O
2
PDD
I
34
Power-Down Device active when PDD=’1’
Programming Pin for’Power Adaptation versus Speed’:
SPEED=’1’ Fs<40MHz, SPEED=’0’ 40MHz<Fs<50MHz
PLL is locked when ’LOCK’ level is ’high’.
+ Serial Data Output Channel 1
SPEED
I
33
LOCK
D1+
O
O
O
O
O
O
O
O
O
O
O
O
O
29
13
14
15
16
21
22
24
23
17
18
19
20
D1-
- Serial Data Output Channel 1
D2+
+ Serial Data Output Channel 2
D2-
- Serial Data Output Channel 2
D3+
+ Serial Data Output Channel 3
D3-
- Serial Data Output Channel 3
D4+
+ Serial Data Output Channel 4
D4-
- Serial Data Output Channel 4
SCLK+
SCLK-
FCLK+
FCLK-
+ Serial Clock - 250MHz max
- Serial Clock - 250MHz max
+ Frame Clock - 50MHz max
- Frame Clock - 50MHz max
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Values
Unit
1)
AVDD, DVDD, VDD
-0.3 to 3.3
V
Analog, digital, digital buffer Supply voltage
Electrical Static Discharge
- HBM
ESD
KV
KV
- CDM-JEDEC Standard
2)
Latch-up
A
Class
1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3V or
VDD
2) Corporate ST Microelectronics procedure number 0018695
OPERATING CONDITIONS
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
AVDD Analog Supply voltage
DVDD Digital Supply voltage
2.25
2.25
2.25
2.5
2.5
2.5
2.7
2.7
2.7
V
V
V
VDD
Digital buffer Supply voltage
4/14
TSA1041
CONDITIONS
AVDD = DVDD = VDD = 2.5V, Fs= 50Msps,Fin= 10MHz, VINpp@ -1.0dBFS, VREFM= 0V, Internal
references
Tamb = 25°C (unless otherwise specified)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
CLK
DC
Input Frequency
TBD
50
Msps
%
Clock Duty Cycle
50
10
TC1
TC2
Tlock
Fsfr
Clock pulse width (high)
Clock pulse width (low)
Rising edge of LOCK
Sweep Frequency Rate
Fs=50MHz
Fs=50MHz
ns
10
ns
1.5
500
ns
Hz/s
Wake-up
time
Power-down-to-active
20
ns
CONVERSION AND SERIALIZATION TIMING CHARACTERISTICS
Tpd
Data Pipeline Delay
5.5
44
cycles
ns
Fs=50MHz
Tsd
Serializer Delay
(1/Fs)+12*(1/10Fs)
Rload = 100 ohms
Cload = 4pF
LVDS Propagation Delay up to
up (50% to 50%)
Tpduu
530
ps
Rload = 100 ohms
Cload = 4pF
LVDS Propagation Delay down
to down
Tpddd
Tjit
530
150
ps
ps
Jitter PLL and LVDS
LVDS OUTPUTS TIMING CHARACTERISTICS
Tsklpd Skew between LVDS buffer
100
280
280
ps
ps
ps
Tr
Tf
Rise time 20%-80%
Fall time 20%-80%
Rload = 100 ohms
Cload = 4pF
5/14
TSA1041
TIMING DIAGRAM: General description
N+1
N+4
N+6
N+7
N+3
N+2
N
N+8
N+5
CLK
Sample N+1
Sample N
Data
ch1...ch4
NON VALID DATA
SCLK
NON VALID SIGNAL
NON VALID SIGNAL
FCLK
LOCK
DETAILED TIMING: data, clock positioning
FCLK
SCLK
DATA
LSB MSB
D8
D1
D7
LSB
6/14
TSA1041
CONDITIONS
AVDD = DVDD = VDD = 2.5V, Fs= 50Msps,Fin= 10MHz, VINpp@ -1.0dBFS, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ANALOG INPUTS
VINpp
Zin
Differential analog input signal
Equivalent input resistance
Input capacitance
2
Vpp
kΩ
Fs=50Msps
10.6
5.0
Cin
pF
BW
Analog Input Bandwidth
Effective Resolution Bandwidth
VINpp@ Full scale, Fs=50Msps
1000
60
MHz
MHz
ERB
INTERNAL REFERENCE VOLTAGE
INREFP Top internal reference voltage
1
V
V
INCM
Internal common mode voltage
0.5
EXTERNAL REFERENCE VOLTAGE
VREFP Forced top reference voltage
VREFM Forced bottom reference voltage
1
0
V
V
Forced internal common mode volt-
VINCM
age
0.5
V
DIGITAL INPUTS AND OUTPUTS
2.5V CMOS Inputs/Outputs
VIL
VIH
Logic "0" voltage
Logic "1" voltage
Logic "0" voltage
Logic "1" voltage
0.8
V
V
V
V
2.0
VOL
VOH
Iol=10µA
0.4
Ioh=-10µA
2.4
2.5V LVDS Outputs
VOD
Differential Output Voltage
330
mV
mV
RL=100Ω
∆VOD
Output Differential Voltage Unbal-
ance
15
15
VOS
Output Offset Voltage
1.22
V
∆VOS
Offset Voltage Unbalance
mV
POWER CONSUMPTION
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
PDD = 0
Power consumption in normal
operation mode and power
down mode
- Fs= 50Msps
- Fs=40Msps
440
380
20
460
400
100
mW
mW
µW
Pd
PDD = 1
Junction-ambient thermal resis-
tor (TQFP48)
Rthja
80
°C/W
7/14
TSA1041
CONDITIONS
AVDD = DVDD = VDD = 2.5V, Fs= 50Msps,Fin= 10MHz, VINpp@ -1.0dBFS, internal references,
VREFM= 0V
Tamb = 25°C (unless otherwise specified)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ACCURACY
Fin= 10MHz, VINpp@+1dBFS
Fin= 10MHz, VINpp@+1dBFS
Fin= 10MHz, VINpp@+1dBFS
Fin= 10MHz, VINpp@+1dBFS
OE
GE
Offset Error
Gain error
-1.5
±0.3
±0.6
tbd
LSB
%
DNL
INL
Differential Non Linearity
Integral Non Linearity
LSB
LSB
Monotonicity and no missing
codes
-
Guaranteed
DYNAMIC CHARACTERISTICS
SFDR Spurious Free Dynamic Range
69.5
58.9
67.5
dBFS
dBc
SNR
THD
Signal to Noise Ratio
Total Harmonics Distortion
dBc
Signal to Noise and Distortion
Ratio
SINAD
58.4
9.6
dBc
bits
ENOB Effective Number of Bits
MATCHING BETWEEN CHANNELS
GM
OM
Gain match
0.04
0.5
%
Channels Offset mismatch
Crosstalk
LSB
Xtalk
-80
dBFS
Equivalents circuits:
LVDS outputs
VDD
ADC inputs:
3.5mA
AVcc
V-
V+
Zin=1/(2ΠCs.Fs)=3.3kΩ (Fs=20MHz)
Di- SCLK-,FCLK-
Di+, SCLK+,FCLK+
VIN
Cin=4pF
INCM
V-
V+
AGND
3.5mA
VCC
8/14
TSA1041
Figure 1 : Static parameter: Differential Non Linearity
Fs=50MSPS; Fin=10MHz; N=131072pts
1
0 . 8
D
D
N
N
L
L
m
m
i n
a
=
=
- 0 . 4 5 0 l s b
0 . 2 7 4 l s b
x
0 . 6
0 . 4
0 . 2
0
- 0 . 2
- 0 . 4
- 0 . 6
- 0 . 8
- 1
0
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
1 0 0 0
Figure 2 : Static parameter: Integral Non Linearity
Fs=50MSPS; Fin=10MHz; N=131072pts
1 . 5
I N L
I N L
m
m
i n
a x
=
=
-1 . 2 5 4 l s b
1 . 2 2 7 l s b
1
0 . 5
0
-0 . 5
- 1
-1 . 5
0
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
1 0 0 0
9/14
TSA1041
Figure 3 : Single-tone 16K FFT at Fs=50 Msps, Internal references
Fin=10MHz, Vin@-1dBFS, SFDR=-70.7dBc, THD=-69.32dBc, SNR=59.6dB, SINAD=59.2dB, ENOB=9.7 bits
0
-10
-20
SFSR = -0.95dBFS
ENOB = 9.697 Bits
SINAD = 59.18dBc
SNR = 59.62dBc
THD = -69.32dBc
SFDR = -70.70dBFS
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
2.5
5
7.5
10
12.5
15
17.5
20
22.5
25
10/14
TSA1041 APPLICATION NOTE
Detailed information:
Test Pattern (SYNCMODE):
An internal register in the TSA1041 delivers a
Synchronization pattern (1000101010) to secure
the data transmission between the 4-channels.
When the CMOS input SYNCMODE is high, the
Synchronization pattern is delivered at the output
of the TSA1041.
The TSA1041 contains four High Speed Analog to
Digital converters, able to convert simultaneously
four differential inputs. Each of the single ADC is
based on a pipeline architecture implemented in a
submicron CMOS process to achieve the best
performances in terms of linearity and power
consumption.
Data Synchronization (SCLK, FCLK):
To ease the application, the TSA1041 provides
common internal references and a common
mode, related to all channels. External references
can also be applied to adjust the input scale
according application needs and improve dynamic
performances.
The TSA1041 delivers the Serial-Clock (5 times
the sampling frequency Fs, edges on middle of
data) and the Frame-Clock (same frequency as
the sampling clock, edges aligned with data) for
deserialization (see figure.’Detailed timing’ p6).
A PLL and one serializer per channel are
integrated in the design of the TSA1041 to allow
the serialization of the 10-bits wide data output
per channel. At these high data bits rate
(500Mbits/s for a sampling frequency at 50Msps),
the data transmission is done through single
differential LVDS buses. The use of LVDS output
buffers allows to reduce I/O noise and optimize
the ratio’number of channels/consumption’,
compared to CMOS parallel output buses.
Moreover it allows to reduce board size and
simplify PCB layout.
The serial clock SCLK can be used with DDR
(double data registers) to deserialize on both
rising and falling edge of the SCLK. The first bit is
detected by using the FCLK or the
synchronization pattern.
For
systems
integrating
SERDES,
the
deserialisation is done by using the frame clock
FCLK.
Data Serialization (LOCK):
An internal PLL and a serializer serialize the 10-bit
wide output data.
At 50Msps sampling frequency the overall
consumption of the four-channels TSA1041 is
only 440mW
Before the internal PLL of the TSA1041 is locked
on the sampling frequencyx10, the CMOS output
LOCK remains low. When the internal PLL is
locked, the output LOCK goes high.
Operating modes:
For a proper use of the LOCK and if the sampling
frequency varies during operation it is strongly
advised to put the device on power-down before
increasing/cdecreasing the sampling frequency.
Mode Ref ext/int (REFMODE):
When REFMODE is let to 0, the TSA1041 uses
the internal reference voltages to set up the
dynamic range for the four channels. When
REFMODE is set to 1, external references
VREFP and VINCM must be applied to adjust the
dynamic range.
If the sampling frequency is 50MHz, the
transmitted data bit rate is 500Mbps. The
serialization provides first MSB(D9), D8...D1, and
at the end LSB(D0).
Power Down Device (PDD):
Power adaptation vs Fs (SPEED):
When PDD is set to low level, the device is active.
When set to high level the circuit is inactive.
The power consumption of the device may be
optimized versus the sampling frequency with one
11/14
TSA1041
programming digit, pin SPEED as shown in Table
1:.
- the differential impedance between the 2 traces
must be 100 ohms to avoid reflection. The surface
mounted termination resistor must be 100 ohms
(1%) as close as possible to the receiver inputs
Fs (Msps)
SPEED
Pd (mW)
- to avoid crosstalk, LVDS pairs should not be
placed too closed from each other.
<40
1
0
380
440
- Same lengths between LVDS traces and as
short as possible (driver-receiver) to limit the skew
between channels and clocks.
40-50
- Isolation of LVDS lines with ground plane.
Table 1 : : Programming for power
optimization versus speed
- Minimization of discontinuities on LVDS traces.
LVDS outputs:
The LVDS (Low-voltage differential signaling)
specifications of the TSA1041 are based on the
ANSI/TIA/EIA-644 LVDS standard. The low
voltage swing (300mV) of LVDS reduces noise
generation. Moreover well-balanced and close
data transmission lines, such as twisted pairs
obtain the maximum common mode rejection.
A termination resistor of 100 ohms must be
added.
Layout precautions:
Grounding and bypassing:
To obtain the best performances from the
TSA1041, a proper grounding and bypassing of
all power supplies and references is very
important. Bypass capacitors (470nF and 10nF
surface mounted capacitors) must be placed as
close as possible to the ADC pins in order to
improve high frequency bypassing and reduce
harmonic distortion (see figure 4). It will prevent
the high frequency transient current and noise
from going through power supplies and
references lines.
It is recommended to use a four-layer PCB board
with top and bottom layers for signals, a ground
and a power layer. The use of multiple via to
connect power and ground traces to appropriate
planes will increase noise immunity.
Analog Channel matching:
The Differential analog input lines should be as
short as possible and be of equal lengths. The
length of each pair addressing the four A/D
converters should be very close. To minimize
crosstalk between channels, each analog pair
must respect a certain distance from other pair.
LVDS outputs and channels matching:
For these high data throughput (up to 500Mb/s),
the layout of LVDS traces must follow some rules:
12/14
TSA1041
Figure 4 : TSA1041 Evaluation board schematic
13/14
TSA1041
PACKAGE MECHANICAL DATA
TQFP48 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.6
MIN.
MAX.
0.063
0.006
0.057
0.011
0.0079
A
A1
A2
B
0.05
1.35
0.17
0.09
0.15
1.45
0.27
0.20
0.002
0.053
0.007
0.0035
1.40
0.22
0.055
0.009
C
D
9.00
7.00
5.50
0.50
9.00
7.00
5.50
0.60
1.00
3.5˚
0.354
0.276
0.216
0.020
0.354
0.276
0.216
0.024
0.039
3.5˚
D1
D3
e
E
E1
E3
L
0.45
0˚
0.75
7˚
0.018
0˚
0.030
7˚
L1
K
0110596/C
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners.
© 2003 STMicroelectronics - All Rights Reserved
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14/14
相关型号：
TSA1041IFT
4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48, 7 X 7 MM, TQFP-48
STMICROELECTR
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