STP75NS04Z [STMICROELECTRONICS]

N-channel Clamped - 7mohm - 80A - TO-220 Fully protected MESH Overlay III Power MOSFET; N沟道钳位 - 7mohm - 80A - TO- 220完全保护MESH覆盖III功率MOSFET
STP75NS04Z
型号: STP75NS04Z
厂家: ST    ST
描述:

N-channel Clamped - 7mohm - 80A - TO-220 Fully protected MESH Overlay III Power MOSFET
N沟道钳位 - 7mohm - 80A - TO- 220完全保护MESH覆盖III功率MOSFET

晶体 晶体管 功率场效应晶体管 开关 脉冲 局域网
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STP75NS04Z  
N-channel Clamped - 7m- 80A - TO-220  
Fully protected MESH Overlay™ III Power MOSFET  
General features  
Type  
VDSS  
RDS(on)  
ID  
STP75NS04Z  
Clamped  
< 11mΩ  
80A  
Low capacitance and gate charge  
100% avalanche tested  
3
2
175°C maximum junction temperature  
1
TO-220  
Description  
This fully clamped MOSFET is produced by using  
the latest advanced Company’s Mesh Overlay  
process which is based on a novel strip layout.  
The inherent benefits of a new technology  
coupled with the extra clamping capabilities make  
this product particularly suitable for the harshest  
operation conditions such as those encoured in  
power tools. Any other application requiring extra  
ruggedness is also recommended.  
Internal schematic diagram  
Applications  
Switching application  
Power tools  
Order codes  
Part number  
Marking  
Package  
Packaging  
STP75NS04Z  
P75NS04Z  
TO-220  
Tube  
June 2006  
Rev 1  
1/12  
www.st.com  
12  
Contents  
STP75NS04Z  
Contents  
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
2.1  
Electrical characteristics (curves)  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3
4
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
2/12  
STP75NS04Z  
Electrical ratings  
1
Electrical ratings  
Table 1.  
Symbol  
Absolute maximum ratings  
Parameter  
Value  
Unit  
VDS  
VDG  
VGS  
Drain-source voltage (VGS = 0)  
Drain-gate voltage (VGS = 0)  
Clamped  
Clamped  
Clamped  
80  
V
V
Gate-source voltage  
V
(1)  
Drain current (continuous) at TC = 25°C  
Drain current (continuous) at TC = 100°C  
Drain gate current (continuos)  
Gate source current (continuos)  
A
ID  
ID  
63  
A
IDG  
IGS  
50  
mA  
mA  
A
50  
(2)  
Drain current (pulsed)  
320  
IDM  
PTOT  
Total dissipation at TC = 25°C  
Derating factor  
110  
0.73  
8
W
W/°C  
kV  
VESD  
Gate-source ESD (HBM-C=100pF, R=1.5K)  
Tj  
Operating junction temperature  
Storage temperature  
-55 to 175  
°C  
Tstg  
1. Current limited by wire bonding  
2. Pulse with limited by safe operating area  
Table 2.  
Symbol  
Thermal data  
Parameter  
Value  
Unit  
Rthj-case  
Rthj-amb  
Tl  
Thermal resistance junction-case Max  
1.36  
62.5  
300  
°C/W  
°C/W  
°C  
Thermal resistance junction-ambient Max  
Maximum lead temperature for soldering purpose  
Table 3.  
Symbol  
Avalanche data  
Parameter  
Value  
Unit  
Single pulse avalanche energy (starting Tj=25°C,  
ID=IAR, VDD=25V)  
EAS  
470  
mJ  
3/12  
Electrical characteristics  
STP75NS04Z  
2
Electrical characteristics  
(T  
=25°C unless otherwise specified)  
CASE  
Table 4.  
Symbol  
On/off states  
Parameter  
Test condictions  
ID = 1mA, VGS= 0  
Min. Typ. Max. Unit  
Drain-source breakdown  
voltage  
V(BR)DSS  
33  
V
Zero gate voltage drain  
current (VGS = 0)  
IDSS  
VDS = 16V  
1
µA  
Gate body leakage current  
(VDS = 0)  
IGSS  
VGS = 10V  
2
µA  
Gate threshold breakdown  
voltage  
VGSS  
VGS(th)  
RDS(on)  
IGS= 100µA  
18  
2
V
V
VDS= VGS, ID = 250µA  
VGS= 10V, ID= 40A  
Gate threshold voltage  
3
7
4
Static drain-source on  
resistance  
11  
mΩ  
Table 5.  
Symbol  
Dynamic  
Parameter  
Test condictions  
Min. Typ. Max. Unit  
(1)  
VDS =15V, ID = 15A  
Forward transconductance  
50  
S
gfs  
Input capacitance  
Ciss  
Coss  
Crss  
1860  
628  
pF  
pF  
pF  
VDS = 25V, f = 1 MHz,  
VGS =0  
Output capacitance  
Reverse transfer  
capacitance  
196  
Qg  
Qgs  
Qgd  
VDD= 20V, ID= 80 A,  
VGS= 10 V  
Total gate charge  
Gate-source charge  
Gate-drain charge  
50  
14  
16  
nC  
nC  
nC  
(see Figure 13)  
1. Pulsed: pulse duration=300µs, duty cycle 1.5%  
4/12  
STP75NS04Z  
Electrical characteristics  
Min. Typ. Max. Unit  
Table 6.  
Switching on/off  
Parameter  
Symbol  
Test condictions  
VDD= 20V, ID = 40A  
RG= 4.7 , VGS= 10V,  
(see Figure 12)  
td(on)  
tr  
Turn-on delay time  
Rise time  
16  
ns  
ns  
248  
V
DD= 20V, ID = 40A  
td(off)  
tf  
Turn-off delay time  
Fall time  
53  
85  
ns  
ns  
RG= 4.7 , VGS= 10V,  
(see Figure 12)  
Table 7.  
Symbol  
Source drain diode  
Parameter  
Test condictions  
Min. Typ. Max. Unit  
ISD  
Source-drain current  
80  
A
A
(1)  
Source-drain current (pulsed)  
320  
ISDM  
(2)  
I
SD=80A, VGS=0  
Forward on Voltage  
1.5  
V
VSD  
trr  
ISD=80A, di/dt = 100A/µs,  
VDD=30V, Tj=150°C  
Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
53  
91  
ns  
nC  
A
Qrr  
3.4  
(see Figure 17)  
IRRM  
1. Pulse width limited by safe operating area  
2. Pulsed: pulse duration=300µs, duty cycle 1.5%  
5/12  
Electrical characteristics  
STP75NS04Z  
2.1  
Electrical characteristics (curves)  
Figure 1. Safe operating area  
Figure 2. Thermal impedance  
Figure 3. Output characterisics  
Figure 4. Transfer characteristics  
Figure 5. Normalized B  
vs temperature  
Figure 6. Static drain-source on resistance  
VDSS  
6/12  
STP75NS04Z  
Electrical characteristics  
Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations  
Figure 9. Normalized gate threshold voltage Figure 10. Normalized on resistance vs  
vs temperature  
temperature  
Figure 11. Source-drain diode forward  
characteristics  
7/12  
Test circuit  
STP75NS04Z  
3
Test circuit  
Figure 12. Switching times test circuit for  
resistive load  
Figure 13. Gate charge test circuit  
Figure 14. Test circuit for inductive load  
switching and diode recovery times  
Figure 15. Unclamped inductive load test  
circuit  
Figure 16. Unclamped inductive waveform  
Figure 17. Switching time waveform  
8/12  
STP75NS04Z  
Package mechanical data  
4
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages. These packages have a Lead-free second level interconnect . The category of  
second level interconnect is marked on the package and on the inner box label, in  
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering  
conditions are also marked on the inner box label. ECOPACK is an ST trademark.  
ECOPACK specifications are available at: www.st.com  
9/12  
Package mechanical data  
STP75NS04Z  
TO-220 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
4.40  
0.61  
1.15  
0.49  
15.25  
10  
TYP  
MAX.  
4.60  
0.88  
1.70  
0.70  
15.75  
10.40  
2.70  
5.15  
1.32  
6.60  
2.72  
14  
MIN.  
0.173  
0.024  
0.045  
0.019  
0.60  
MAX.  
0.181  
0.034  
0.066  
0.027  
0.620  
0.409  
0.106  
0.202  
0.052  
0.256  
0.107  
0.551  
0.154  
A
b
b1  
c
D
E
0.393  
0.094  
0.194  
0.048  
0.244  
0.094  
0.511  
0.137  
e
2.40  
4.95  
1.23  
6.20  
2.40  
13  
e1  
F
H1  
J1  
L
L1  
L20  
L30  
øP  
Q
3.50  
3.93  
16.40  
28.90  
0.645  
1.137  
3.75  
2.65  
3.85  
2.95  
0.147  
0.104  
0.151  
0.116  
10/12  
STP75NS04Z  
Revision history  
5
Revision history  
Table 8.  
Date  
06-Jun-2006  
Revision history  
Revision  
Changes  
1
First release  
11/12  
STP75NS04Z  
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12/12  

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