STP08DP05B1R [STMICROELECTRONICS]
Low voltage 8-Bit constant current Led sink with full outputs error detection; 低电压8位恒流LED全输出错误检测片
| 型号： | STP08DP05B1R |
| 厂家： | 
ST |
| 描述： | Low voltage 8-Bit constant current Led sink with full outputs error detection |
| 文件： | 总30页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STP08DP05
Low voltage 8-Bit constant current
Led sink with full outputs error detection
Features
■ Low voltage power supply down to 3V
■ 8 constant current output channels
Dip-16
■ Adjustable output current through external
TSSOP16
(Exposed pad)
resistor
■ Short and open output error detection
■ Serial Data IN/Parallel data OUT
■ 3.3V micro driver-able
■ Output current: 5-100mA
TSSOP16
SO-16
■ 30MHz clock frequency
The detection functionality is implemented without
increasing the pin number, through a secondary
function of the output enable and latch pin (DM1
and DM2 respectively), a dedicated logic
■ Available in high thermal efficiency TSSOP
exposed pad
■ ESD protection 2.5kV HBM, 200V MM
sequence allows the device to enter or leave from
detection mode. Through an external resistor,
users can adjust the STP08DP05 output current,
controlling in this way the light intensity of LEDs,
in addition, user can adjust LED’s brightness
intensity from 0% to 100% via OE/DM2 pin.
Description
The STP08DP05 is a monolithic, low voltage, low
current power 8-bit shift register designed for LED
panel displays. The STP08DP05 contains a 8-bit
serial-in, parallel-out shift register that feeds a 8-
bitD-type storage register. In the output stage,
eight regulated current sources were designed to
provide 5-100mA constant current to drive the
LEDs.
The STP08DP05 guarantees a 20V output driving
capability, allowing users to connect more LEDs in
series. The high clock frequency, 30MHz, also
satisfies the system requirement of high volume
data transmission. The 3.3V of voltage supply is
well useful for applications that interface any
micro from 3.3V. Compared with a standard
TSSOP package, the TSSOP exposed pad
increases heat dissipation capability by a 2.5
factor..
The STP08DP05 is backward compatible in the
functionality and footprint with STP8C/L596 and
extends its functionality with open and short
detection on the outputs. The detection circuit
checks 3 different conditions that can occur on the
output line: short to GND, short to V or open line.
O
The data detection results are loaded in the shift
register and shifted out via the serial line output.
Table 1. Device summary
Part Number
Package
DIP-16
Packaging
STP08DP05B1R
STP08DP05MTR
STP08DP05TTR
STP08DP05XTTR
25 parts per tube
SO-16 (Tape & Reel)
TSSOP16 (Tape & Reel)
2500 parts per reel
2500 parts per reel
2500 parts per reel
TSSOP16 Exposed-Pad (Tape & Reel)
May 2007
Rev 2
1/30
www.st.com
30
Contents
STP08DP05
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
3.2
3.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
5
6
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Truth table and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1
7.2
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9
10
Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1 Phase one: “entering in detection mode“ . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2 Phase two: “error detection“ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10.3 Phase three: “resuming to normal mode” . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.4 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11
12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/30
STP08DP05
Summary description
1
Summary description
Table 2. Typical current accuracy
Output voltage
Current accuracy
Output current
Between bits
Between ICs
≥1.3V
1.5%
5%
20 to 100mA
1.1
Pin connection and description
Figure 1. Connections diagram
Note:
The Exposed-pad is electrically not connected
Table 3. Pin description
PIN N°
Symbol
Name and function
1
2
GND
SDI
Ground terminal
Serial data input terminal
Clock input terminal
3
CLK
4
LE/DM1
OUT 0-7
OE/DM2
SDO
Latch input terminal
5-12
13
14
15
16
Output terminal
Output enable input terminal (active low)
Serial data out terminal
Constant current programming
5V Supply voltage terminal
R-EXT
VDD
3/30
Block diagram
STP08DP05
2
Block diagram
Figure 2. Normal mode - block diagram
4/30
STP08DP05
Maximum rating
3
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
3.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol
VDD
VO
Parameter
Value
Unit
Supply voltage IGND
Output voltage
0 to 7
-0.5 to 20
100
V
V
IO
Output current
mA
mA
MHz
°C
IGND
fCLK
TOPR
GND terminal current
Clock frequency
800
50
Operating temperature range
Storage temperature range
-40 to +125
-55 to +150
TSTG
°C
3.2
Thermal data
Table 5. Thermal data
TSSOP-16 (1)
(exposed pad)
Symbol
Parameter
DIP-16 SO-16 TSSOP-16
Unit
RthJA
Thermal resistance junction-ambient
60
75
85
37.5
°C/W
1. The Exposed-Pad should be soldered to the PBC to realize the thermal benefits
5/30
Maximum rating
STP08DP05
3.3
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
VDD
Parameter
Supply voltage
Test conditions
Min
Typ
Max
Unit
V
3.0
5.5
20
VO
Output voltage
V
IO
Output current
OUTn
5
100
mA
mA
mA
V
IOH
Output current
SERIAL-OUT
SERIAL-OUT
+1
IOL
Output current
-1
VIH
0.7VDD
-0.3
20
VDD+0.3
0.3VDD
Input voltage
VIL
Input voltage
V
twLAT
twCLK
twEN
LE/DM1 pulse width
CLK pulse width
OE/DM2 pulse width
Setup time for DATA
Hold time for DATA
Setup time for LATCH
Clock frequency
ns
20
ns
200
7
ns
VDD = 3.0 to 5.0V
tSETUP(D)
tHOLD(D)
tSETUP(L)
fCLK
ns
4
ns
15
ns
Cascade operation (1)
30
MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please
consider the timings carefully.
6/30
STP08DP05
Electrical characteristics
4
Electrical characteristics
Table 7. Electrical characteristics
(V =3.3V to 5V, T = 25°C, unless otherwise specified.)
DD
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
VIH
VIL
IOH
Input voltage high level
Input voltage low level
Output leakage current
0.7VDD
GND
VDD
0.3VDD
10
V
V
VOH = 20V
IOL = 1mA
OH = -1mA
0.5
µA
Output voltage
(Serial-OUT)
VOL
VOH
0.03
0.4
V
V
Output voltage
(Serial-OUT)
I
VOH - VDD =- 0.4V
IOL1
IOL2
VO = 0.3V, Rext = 3.9kΩ
VO = 0.3V, Rext = 970Ω
VO = 1.3V, Rext = 190Ω
VO = 0.3VREXT = 3.9kΩ
VO = 0.3VREXT = 970Ω
VO = 1.3VREXT =190Ω
4.25
19
5
5.75
21
104
8
Output current
20
mA
%
IOL3
96
100
5
∆IOL1
∆IOL2
∆IOL3
Output current error
between bit
(All Output ON)
1.5
1.2
300
200
3
3
RSIN(up) Pull-up resistor
150
100
600
400
KΩ
KΩ
RSIN(down) Pull-down resistor
R
EXT = 980
IDD(OFF1)
4
5
OUT 0 to 7 = OFF
Supply current (OFF)
IDD(OFF2)
REXT = 250
OUT 0 to 7 = OFF
11.2
4.5
13.5
5
mA
°C
REXT = 980
IDD(ON1)
OUT 0 to 7 = ON
Supply current (ON)
IDD(ON2)
REXT = 250
OUT 0 to 7 = ON
11.7
170
13.5
Thermal Thermal protection (1)
1. Guaranteed by desing (not tested)
The thermal protection switches OFF only the outputs current
7/30
Switching characteristics
STP08DP05
5
Switching characteristics
Table 1.
Symbol
Switching characteristics (V = 5V, T = 25°C, unless otherwise specified.)
DD
Parameter
Test conditions
Min
Typ
35
18
48
30
55
36
Max Unit
Propagation delay time,
VDD = 3.3V
VDD = 5V
70
tPLH1 CLK-OUTn, LE\DM1 = H,
OE\DM2 = L
ns
35
Propagation delay time,
tPLH2 LE\DM1 -OUTn,
OE\DM2 = L
V
DD = 3.3V
VDD = 5V
DD = 3.3V
90
ns
60
Propagation delay time,
tPLH3 OE\DM2-OUTn,
LE\DM1 = H
V
110
ns
VDD = 5V
75
VDD = 3.3V
VDD = 5V
7
4
14
ns
8
Propagation delay time,
CLK-SDO
tPLH
Propagation delay time,
tPHL1 CLK-OUTn, LE\DM1 = H,
OE\DM2 = L
V
DD = 3.3V
VDD = 5V
DD = 3.3V
10
20
V
DD = 3.3 V
VIH = VDD
CL = 10pF
VL = 3.0 V
RL = 60 Ω
ns
7
14
VIL = GND
IO = 20mA
REXT = 1KΩ
Propagation delay time,
tPHL2 LE\DM1 -OUTn,
OE\DM2 = L
V
24
20
20
17
50
ns
VDD = 5V
VDD = 3.3V
VDD = 5V
40
Propagation delay time,
tPHL3 OE\DM2-OUTn,
LE\DM1 = H
40
ns
35
VDD = 3.3V
VDD = 5V
22
18
25
30
ns
25
Propagation delay time,
CLK-SDO
tPHL
Output rise time
VDD = 3.3V
60
tON
10~90% of voltage
waveform
ns
VDD = 5V
VDD = 3.3V
VDD = 5V
10
5
25
Output fall time
90~10% of voltage
waveform
15
tOFF
ns
4
12
tr
tf
CLK rise time (1)
CLK fall time (1)
5000
5000
ns
ns
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
8/30
STP08DP05
Equivalent circuit and outputs
6
Equivalent circuit and outputs
Figure 3. OE/DM2 terminal
Figure 4. LE/DM1 terminal
Figure 5. CLK, SDI terminal
9/30
Equivalent circuit and outputs
Figure 6. SDO terminal
STP08DP05
10/30
STP08DP05
Truth table and timing diagram
7
Truth table and timing diagram
7.1
Truth table
Table 8. Truth table
Clock
LE/DM1 OE/DM2
SDI
OUT0 ........ OUT0 ........ OUT7
SDO
H
L
L
L
L
L
H
Dn
Dn ..... Dn -5 ..... Dn -7
No Change
Dn -7
Dn + 1
Dn + 2
Dn + 3
Dn + 3
Dn -7
Dn -5
Dn -5
Dn -5
H
X
X
Dn +2 ..... Dn -3 ..... Dn -5
Dn +2 ..... Dn -3 ..... Dn -5
OFF
Note:
OUT0 to OUT7 = ON when Dn = H; OUT0 to OUT7 = OFF when Dn = L.
11/30
Truth table and timing diagram
STP08DP05
7.2
Timing diagram
Figure 7. Timing diagram - normal mode
Figure 8. Clock, serial-in, serial-out
12/30
STP08DP05
Truth table and timing diagram
Figure 9. Clock, serial-in, latch, enable, outputs
Figure 10. Outputs
13/30
Typical characteristics
STP08DP05
8
Typical characteristics
Figure 11. Output current-R
resistor
EXT
8000
7000
6000
5000
4000
3000
2000
1000
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
Ouput Current (mA)
Table 9. Output current-R
resistor
EXT
Output Current (mA)
3
5
10
20
50
80
130
124
Rext (Ω)
6740
3930
1913
963
386
241
14/30
STP08DP05
Typical characteristics
Figure 12. Power dissipation vs temperature package
Note:
The Exposed-Pad should be soldered to the PBC to realize the thermal benefits.
15/30
Test circuit
STP08DP05
9
Test circuit
Figure 13. DC characteristics
Figure 14. AC characteristics
16/30
STP08DP05
Test circuit
Figure 15. Timing example for open and/or short detection
17/30
Detection mode functionality
STP08DP05
10
Detection mode functionality
10.1
Phase one: “entering in detection mode“
From the “Normal Mode” condition the device can switch to the “Error Mode“ by a logic
sequence on the OE/DM2 and LE/DM1 pins as showed in the following table and diagram:
Table 10. Entering in detection truth table
CLK
1°
H
L
2°
L
3°
H
L
4°
H
5°
H
L
OE/DM2
LE/DM1
L
H
Figure 16. Entering in detection timing diagram
th
After these five CLK cycles the device goes into the “Error Detection Mode“ and at the 6
rise front of CLK the SDI data are ready for the sampling.
18/30
STP08DP05
Detection mode functionality
10.2
Phase two: “error detection“
The eight data bits must be set “1“ in order to set ON all the outputs during the detection.
The data are latched by LE/DM1 and after that the outputs are ready for the detection
process. When the Micro controller switches the OE/DM2 to LOW, the device drives the
LEDs in order to analyze if an OPEN or SHORT condition has occurred.
Figure 17. Detection diagram
The LEDs status will be detected at least in 1 microsecond and after this time the
microcontroller sets OE\DM2 in HIGH state and the output data detection result will go to
the microprocessor via SDO.
Detection mode and normal mode use both the same format data. As soon as all the
detection data bits are available on the serial line, the device may go back to normal mode
of operation. To re-detect the status the device must go back in normal mode and re-
entering in error detection mode .
19/30
Detection mode functionality
STP08DP05
10.3
Phase three: “resuming to normal mode”
The sequence for re-entering in normal mode is showed in the following Table and diagram:
Table 11. Resuming to normal mode timing diagram
CLK
1°
H
L
2°
L
3°
H
L
4°
H
L
5°
H
L
OE/DM2
LE/DM1
L
Figure 18. Resuming to normal mode timing diagram
Note:
For proper device operation the “Entering in detection” sequence must be follow by a
“Resume Mode” sequence, isn’t possible to insert consecutive equal sequence.
20/30
STP08DP05
Detection mode functionality
10.4
Error detection conditions
Table 12. Detection condition (V = 3.3 to 5 V Temperature range 25°C)
DD
Open Line or Output
SW-1 or SW-3b Short to GND
No error
detected
==> IODEC ≤ 0.5 x IO
==> VO ≥ 2.5V
==> IODEC ≥ 0.5 x IO
==> VO ≤ 2.2 V
detected
Short on LED or Short
to V-LED detected
No error
detected
SW-2 or SW-3a
Note:
Where: I = the output current programmed by the R
,
EXT
O
I
= the detected output current in detection mode.
ODEC
Figure 19. Detection circuit
21/30
Package mechanical data
STP08DP05
11
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
22/30
STP08DP05
Package mechanical data
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
0.51
0.77
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
17.78
0.335
0.100
0.700
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
23/30
Package mechanical data
STP08DP05
TSSOP16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
0.041
0.012
0.0079
0.201
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
5.1
0.002
0.031
0.007
0.004
0.193
0.244
0.169
0.004
0.039
1
0.19
0.09
4.9
c
D
E
5
6.4
0.197
0.252
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0˚
8˚
0˚
8˚
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
24/30
STP08DP05
Package mechanical data
TSSOP16 EXPOSED PAD MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
MIN.
MAX.
A
A1
A2
b
1.2
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.0089
0.201
0.004
0.039
0.8
0.19
0.09
4.9
1
5
0.031
0.007
0.004
0.193
0.067
0.244
0.169
0.059
c
D
0.197
D1
E
1.7
6.2
6.4
4.4
6.6
4.5
0.252
0.173
0.260
0.177
E1
E2
e
4.3
1.5
0.65
0.60
0.0256
0.024
K
0°
8°
0°
8°
L
0.45
0.75
0.018
0.030
7419276A
25/30
Package mechanical data
STP08DP05
Tape & Reel TSSOP16 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
D
12.8
20.2
60
13.2
0.504
0.795
2.362
N
T
22.4
6.9
5.5
1.8
4.1
8.1
0.882
0.272
0.217
0.071
0.161
0.319
Ao
Bo
Ko
Po
P
6.7
5.3
1.6
3.9
7.9
0.264
0.209
0.063
0.153
0.311
26/30
STP08DP05
Package mechanical data
SO-16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
1.75
0.25
1.64
0.46
0.25
MIN.
TYP.
MAX.
0.068
0.010
0.063
0.018
0.010
A
a1
a2
b
0.1
0.004
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45° (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8° (max.)
0016020D
27/30
Package mechanical data
STP08DP05
Tape & Reel SO-16 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
D
12.8
20.2
60
13.2
0.504
0.795
2.362
N
T
22.4
6.65
10.5
2.3
0.882
0.262
0.414
0.090
0.161
0.319
Ao
Bo
Ko
Po
P
6.45
10.3
2.1
0.254
0.406
0.082
0.153
0.311
3.9
4.1
7.9
8.1
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STP08DP05
Revision history
12
Revision history
Table 13. Revision history
Date
Revision
Changes
3-Apr-2007
1
2
First release
Updated Table 7 on page 7
21-May-2007
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STP08DP05
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