STM8L051F3P6_技术文档

STM8L051F3

Value line, 8-bit ultralow power MCU, 8-KB Flash,

256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC

Data brief  preliminary data

Features

■ Operating conditions

– Operating power supply: 1.8 V to 3.6 V

Temperature range: 40 °C to 85 °C

■ Low power features

TSSOP20

– 5 low power modes: Wait, Low power run,

Low power wait, Active-halt with RTC, Halt

– Ultralow leakage per I/0: 50 nA

– Fast wakeup from Halt: 5 µs

■ DMA

– 4 channels supporting ADC, SPI, I2C,

USART, timers

– 1 channel for memory-to-memory

■ Advanced STM8 core

– Harvard architecture and 3-stage pipeline

– Max freq: 16 MHz, 16 CISC MIPS peak

– Up to 40 external interrupt sources

■ 12-bit ADC up to 1 Msps/28 channels

– Internal reference voltage

■ Reset and supply management

■ Timers

– Low power, ultrasafe BOR reset with 5

selectable thresholds

– Ultra low power POR/PDR

– Two 16-bit timers with 2 channels (used as

IC, OC, PWM), quadrature encoder

– One 8-bit timer with 7-bit prescaler

– Programmable voltage detector (PVD)

– 2 watchdogs: 1 Window, 1 Independent

– Beeper timer with 1, 2 or 4 kHz frequencies

■ Clock management

– 32 kHz and 1 to 16 MHz crystal oscillators

– Internal 16 MHz factory-trimmed RC

– Internal 38 kHz low consumption RC

– Clock security system

■ Communication interfaces

– Synchronous serial interface (SPI)

2

– Fast I C 400 kHz SMBus and PMBus

– USART

■ Low power RTC

■ Up to 18 I/Os, all mappable on interrupt vectors

■ Development support

– BCD calendar with alarm interrupt

– Digital calibration with +/- 0.5 ppm accuracy

– LSE security system

– Fast on-chip programming and non-

intrusive debugging with SWIM

– Auto-wakeup from Halt w/ periodic interrupt

– Bootloader using USART

■ Memories

– 8 Kbytes of Flash program memory and

256 bytes of data EEPROM with ECC

– Flexible write and read protection modes

– 1 Kbyte of RAM

Table 1.

Reference

STM8L051xx

Device summary

Part number

STM8L051F3

April 2012

Doc ID 022985 Rev 1

1/46

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice. For further information contact your local STMicroelectronics sales office.

www.st.com

1

Contents

STM8L051F3

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

2.2

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

3.2

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2.1

3.2.2

Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3

Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3.1

3.3.2

3.3.3

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4

3.5

3.6

3.7

3.8

3.9

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

System configuration controller and routing interface . . . . . . . . . . . . . . . 17

3.10 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.10.1 16-bit general purpose timers (TIM2, TIM3) . . . . . . . . . . . . . . . . . . . . . 17

3.10.2 8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.11 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.11.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.11.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.13 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.13.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2

3.13.2 I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.13.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.14 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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Contents

3.15 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4

5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1

System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1

5.2

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6

7

Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1

7.2

ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.1

7.2.2

20-lead thin shrink small package (TSSOP20) . . . . . . . . . . . . . . . . . . . 41

32-pin Low profile quad flat package (LQFP32) . . . . . . . . . . . . . . . . . . 42

8

9

Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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List of tables

STM8L051F3

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Low density value line STM8L05xxx low power device features and peripheral counts. . . . 8

Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Low density value line STM8L05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

TSSOP20 20-lead thin shrink small package, mechanical data . . . . . . . . . . . . . . . . . . . . . 41

LQFP32 32-pin low profile quad flat package, mechanical data. . . . . . . . . . . . . . . . . . . . . 42

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Low density value line STM8L05xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . 10

Low density value line STM8L05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 15

STM8L051Fx 20-pin TSSOP20 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TSSOP20 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

LQFP32 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Low density value line STM8L05xxx ordering information scheme . . . . . . . . . . . . . . . . . . 44

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Introduction

STM8L051F3

1

Introduction

This document describes the features, pinout, mechanical data and ordering information for

the low density value line STM8L151F3 microcontroller with 8-Kbyte Flash memory density.

For more details on the whole STMicroelectronics ultra low power family please refer to

Section 2.2: Ultra low power continuum.

For detailed information on device operation and registers, refer to the reference manual

(RM0031).

For information on to the Flash program memory and data EEPROM, refer to the

programming manual (PM0054).

For information on the debug module and SWIM (single wire interface module), refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).

Low density value line devices provide the following benefits:

●

Integrated system

–

8 Kbytes of low-density embedded Flash program memory

256 bytes of data EEPROM

1 Kbyte of RAM

Internal high-speed and low-power low speed RC

Embedded reset

●

Ultra low power consumption

–

1 µA in Active-halt mode

Clock gated system and optimized power management

Capability to execute from RAM for Low power wait mode and Low power run

mode

●

Advanced features

–

Up to 16 MIPS at 16 MHz CPU clock frequency

Direct memory access (DMA) for memory-to-memory or peripheral-to-memory

access

Short development cycles

–

Application scalability across a common family product architecture with

compatible pinout, memory map and modular peripherals

–

Wide choice of development tools

These features make the value line STM8L05xxx ultra low power microcontroller family

suitable for a wide range of consumer and mass market applications.

Refer to Table 2: Low density value line STM8L05xxx low power device features and

peripheral counts and Section 3: Functional overview for an overview of the complete range

of peripherals proposed in this family.

Figure 1 shows the block diagram of the low density value line STM8L05xxx family.

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STM8L051F3

Description

2

Description

The low density value line STM8L05xxx devices are members of the STM8L ultra low power

8-bit family.

The STM8L ultra low power family features an enhanced STM8 CPU core providing

increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of

a CISC architecture with improved code density, a 24-bit linear addressing space and an

optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which

allows non-intrusive In-Application debugging and ultra-fast Flash programming.

Low density value line STM8L05xxx microcontrollers feature embedded data EEPROM and

low power, low-voltage, single-supply program Flash memory.

The devices incorporate an extensive range of enhanced I/Os and peripherals, a 12-bit

ADC, a real-time clock, two 16-bit timers, one 8-bit timer, as well as standard communication

2

interfaces such as an SPI, an I C interface, and one USART.

The modular design of the peripheral set allows the same peripherals to be found in different

ST microcontroller families including 32-bit families. This makes any transition to a different

family very easy, and simplified even more by the use of a common set of development

tools.

All STM8L ultra low power products are based on the same architecture with the same

memory mapping and a coherent pinout.

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Description

STM8L051F3

2.1

Device overview

Table 2.

Low density value line STM8L05xxx low power device features and

peripheral counts

Features

STM8L051F3

Flash (Kbytes)

8

256

1

Data EEPROM (Bytes)

RAM (Kbytes)

1

Basic

(8-bit)

Timers

General

2

purpose

(16-bit)

SPI

1

Communicati

I2C

on interfaces

USART

GPIOs

1

18 ⁽¹⁾

12-bit synchronized ADC

(number of channels)

1

(10)

RTC, window watchdog, independent watchdog,

16-MHz and 32-kHz internal RC,

Others

1- to 16-MHz and 32-kHz external oscillator

CPU frequency

Operating voltage

Operating temperature

Package

16 MHz

1.8 to 3.6 V

40 to +85 °C

TSSOP20

1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the

NRST/PA1 pin as general purpose output only (PA1).

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Description

2.2

Ultra low power continuum

The ultra low power value line STM8L05xxx are fully pin-to-pin, software and feature

compatible. Besides the full compatibility within the family, the devices are part of

STMicroelectronics microcontrollers ultra low power strategy which also includes

STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of

performance, peripherals, system architecture, and features.

They are all based on STMicroelectronics 0.13 µm Ultralow leakage process.

Note:

The STM8L051xx are pin-to-pin compatible with STM8L101xx devices.

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and

pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core

for STM32L family. In addition specific care for the design architecture has been taken to

optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra low power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals

STM8L051xx and STM32L15xx share identical peripherals which ensure a very easy

migration from one family to another:

●

Analog peripheral: ADC1

●

Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L051xx and STM32L15xx devices

use a common architecture:

●

Same power supply range from 1.65 to 3.6 V

●

Architecture optimized to reach ultra low consumption both in low power modes and

Run mode

●

Fast startup strategy from low power modes

Flexible system clock

Ultra-safe reset: same reset strategy for both STM8L051xx and STM32L15xx including

power-on reset, power-down reset, brownout reset and programmable voltage detector.

Features

ST ultra low power continuum also lies in feature compatibility:

●

More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

Memory density ranging from 4 to 128 Kbytes

●

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Functional overview

STM8L051F3

3

Functional overview

Figure 1.

Low density value line STM8L05xxx device block diagram

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1. Legend:

ADC: Analog-to-digital converter

BOR: Brownout reset

DMA: Direct memory access

I²C: Inter-integrated circuit multimaster interface

IWDG: Independent watchdog

POR/PDR: Power-on reset / power-down reset

RTC: Real-time clock

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous asynchronous receiver transmitter

WWDG: Window watchdog

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STM8L051F3

Functional overview

3.1

Low power modes

The low density value line STM8L05xxx devices support five low power modes to achieve

the best compromise between low power consumption, short startup time and available

wakeup sources:

●

Wait mode: The CPU clock is stopped, but selected peripherals keep running. An

internal or external interrupt or a Reset can be used to exit the microcontroller from

Wait mode (WFE or WFI mode).

Low power run mode: The CPU and the selected peripherals are running. Execution

is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data

EEPROM are stopped and the voltage regulator is configured in ultra low power mode.

The microcontroller enters Low power run mode by software and can exit from this

mode by software or by a reset.

All interrupts must be masked. They cannot be used to exit the microcontroller from this

mode.

●

Low power wait mode: This mode is entered when executing a Wait for event in Low

power run mode. It is similar to Low power run mode except that the CPU clock is

stopped. The wakeup from this mode is triggered by a Reset or by an internal or

external event (peripheral event generated by the timers, serial interfaces, DMA

controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the

system goes back to Low power run mode.

All interrupts must be masked. They cannot be used to exit the microcontroller from this

mode.

●

Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup

can be triggered by RTC interrupts, external interrupts or reset.

Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

The RAM content is preserved. The wakeup is triggered by an external interrupt or

reset. A few peripherals have also a wakeup from Halt capability. Switching off the

internal reference voltage reduces power consumption. Through software configuration

it is also possible to wake up the device without waiting for the internal reference

voltage wakeup time to have a fast wakeup time of 5 µs.

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Functional overview

STM8L051F3

3.2

Central processing unit STM8

3.2.1

Advanced STM8 Core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard

architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20

addressing modes including indexed indirect and relative addressing, and 80 instructions.

Architecture and registers

●

Harvard architecture

3-stage pipeline

32-bit wide program memory bus - single cycle fetching most instructions

X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

●

8-bit accumulator

24-bit program counter - 16-Mbyte linear memory space

16-bit stack pointer - access to a 64-Kbyte level stack

8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

●

20 addressing modes

Indexed indirect addressing mode for lookup tables located anywhere in the address

space

●

Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

●

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2

Interrupt controller

The low density value line STM8L05xxx features a nested vectored interrupt controller:

●

Nested interrupts with 3 software priority levels

32 interrupt vectors with hardware priority

Up to 17 external interrupt sources on 11 vectors

Trap and reset interrupts

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STM8L051F3

Functional overview

3.3

Reset and supply management

3.3.1

Power supply scheme

The device requires a 1.8 V to 3.6 V operating supply voltage (V ). The external power

DD

supply pins must be connected as follows:

●

V

; V

= 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator.

DD1

SS1

Provided externally through V

pins, the corresponding ground pin is V

.

DD1

SS1

V

; V

= 1.8 to 3.6 V: external power supplies for analog peripherals. V

and

DDA

SSA

DDA

must be connected to V

and V

, respectively.

DD1

SS1

V

; V

= 1.8 to 3.6 V: external power supplies for I/Os. V

and V

must be

SS2

DD2

connected to V

and V

, respectively.

DD1

SS1

V

, V

(for ADC1): external reference voltage for ADC1. Must be provided

REF-

REF+

externally through V

and V

pin.

REF+

REF-

3.3.2

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR), coupled with a brownout reset (BOR) circuitry. When the microcontroller operates

between 1.8 and 3.6 V, BOR is always active and ensures proper operation starting from

1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts,

either to confirm or modify default thresholds, or to disable BOR permanently.

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Halt mode, it is possible to automatically switch off the

internal reference voltage (and consequently the BOR) in Halt mode. The device remains in

reset state when V is below a specified threshold, V

or V

, without the need for

DD

POR/PDR

BOR

any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

/V power supply and compares it to the V threshold. This PVD offers 7 different

V

DD DDA

PVD

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt can be generated when V /V drops below the V threshold and/or when

DD DDA

PVD

V

/V

is higher than the V

threshold. The interrupt service routine can then generate

DD DDA

PVD

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3

Voltage regulator

The low density value line STM8L05xxx embeds an internal voltage regulator for generating

the 1.8 V power supply for the core and peripherals.

This regulator has two different modes:

●

Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event

(WFE) modes.

Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low

power wait modes.

When entering Halt or Active-halt modes, the system automatically switches from the MVR

to the LPVR in order to reduce current consumption.

Doc ID 022985 Rev 1

13/46

Functional overview

STM8L051F3

3.4

Clock management

The clock controller distributes the system clock (SYSCLK) coming from different oscillators

to the core and the peripherals. It also manages clock gating for low power modes and

ensures clock robustness.

Features

●

Clock prescaler: to get the best compromise between speed and current consumption

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler.

●

Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register.

Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

System clock sources: four different clock sources can be used to drive the system

clock:

–

1-16 MHz High speed external crystal (HSE)

16 MHz High speed internal RC oscillator (HSI)

32.768 Low speed external crystal (LSE)

38 kHz Low speed internal RC (LSI)

●

RTC clock sources: the above four sources can be chosen to clock the RTC whatever

the system clock.

Startup clock: After reset, the microcontroller restarts by default with an internal

2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the

application program as soon as the code execution starts.

●

Clock security system (CSS): This feature can be enabled by software. If a HSE clock

failure occurs, it is automatically switched to HSI.

Configurable main clock output (CCO): This outputs an external clock for use by the

application.

14/46

Doc ID 022985 Rev 1

STM8L051F3

Figure 2.

Functional overview

Low density value line STM8L05xxx clock tree diagram

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1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE

bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE

bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

Doc ID 022985 Rev 1

15/46

Functional overview

STM8L051F3

3.5

Low power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.

Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,

year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31

day months are made automatically.

It provides a programmable alarm and programmable periodic interrupts with wakeup from

Halt capability.

●

Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is

from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach

36 hours

Periodic alarms based on the calendar can also be generated from every second to

every year

3.6

Memories

The low density value line STM8L05xxx devices have the following main features:

●

Up to 1 Kbyte of RAM

●

The non-volatile memory is divided into three arrays:

–

8 Kbytes of low-density embedded Flash program memory

256 bytes of Data EEPROM

Option bytes

The EEPROM embeds the error correction code (ECC) feature.

The option byte protects part of the Flash program memory from write and readout piracy.

3.7

3.8

DMA

A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and

peripherals-from/to-memory transfer capability. The 4 channels are shared between the

following IPs with DMA capability: ADC1, I2C1, SPI1, USART1, and the three timers.

Analog-to-digital converter

●

12-bit analog-to-digital converter (ADC1) with 10 channels (including 1 fast channel)

and internal reference voltage

●

Conversion time down to 1 µs with f

= 16 MHz

SYSCLK

Programmable resolution

Programmable sampling time

Single and continuous mode of conversion

Scan capability: automatic conversion performed on a selected group of analog inputs

Analog watchdog

Triggered by timer

Note:

ADC1 can be served by DMA1.

16/46

Doc ID 022985 Rev 1

STM8L051F3

Functional overview

3.9

System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate

functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.

The highly flexible routing interface controls the routing of internal analog signals to ADC1

and the internal reference voltage V

.

REFINT

3.10

Timers

Low density value line STM8L05xxx devices contain two 16-bit general purpose timers

(TIM2 and TIM3) and one 8-bit basic timer (TIM4).

All the timers can be served by DMA1.

Table 3 compares the features of the advanced control, general-purpose and basic timers.

Table 3.

Timer

Timer feature comparison

DMA1

Counter Counter

Capture/compare Complementary

Prescaler factor

request

resolution

type

channels

outputs

generation

TIM2

TIM3

Any power of 2

from 1 to 128

16-bit

8-bit

up/down

up

2

0

Yes

None

Any power of 2

from 1 to 32768

TIM4

3.10.1

16-bit general purpose timers (TIM2, TIM3)

●

16-bit autoreload (AR) up/down-counter

7-bit prescaler adjustable to fixed power of 2 ratios (1…128)

2 individually configurable capture/compare channels

PWM mode

Interrupt capability on various events (capture, compare, overflow, break, trigger)

Synchronization with other timers or external signals (external clock, reset, trigger and

enable)

3.10.2

8-bit basic timer (TIM4)

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable

prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.11

Watchdog timers

The watchdog system is based on two independent timers providing maximum security to

the applications.

Doc ID 022985 Rev 1

17/46

Functional overview

STM8L051F3

3.11.1

Window watchdog timer

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually

generated by external interferences or by unexpected logical conditions, which cause the

application program to abandon its normal sequence.

3.11.2

Independent watchdog timer

The independent watchdog peripheral (IWDG) can be used to resolve processor

malfunctions due to hardware or software failures.

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a

CPU clock failure.

3.12

Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in

the range of 1, 2 or 4 kHz.

3.13

Communication interfaces

3.13.1

SPI

The serial peripheral interfaces (SPI1) provide half/ full duplex synchronous serial

communication with external devices.

●

Maximum speed: 8 Mbit/s (f

/2) both for master and slave

SYSCLK

Full duplex synchronous transfers

Simplex synchronous transfers on 2 lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

Hardware CRC calculation

Slave/master selection input pin

Note:

SPI1 can be served by the DMA1 Controller.

2

3.13.2

I C

2

The I C bus interface (I2C1) provides multi-master capability, and controls all I²C bus-

specific sequencing, protocol, arbitration and timing.

●

2

Master, slave and multi-master capability

Standard mode up to 100 kHz and fast speed modes up to 400 kHz

7-bit and 10-bit addressing modes

SMBus 2.0 and PMBus support

Hardware CRC calculation

Note:

I C1 can be served by the DMA1 Controller.

18/46

Doc ID 022985 Rev 1

STM8L051F3

Functional overview

3.13.3

USART

The USART interface (USART1) allows full duplex, asynchronous communications with

external devices requiring an industry standard NRZ asynchronous serial data format. It

offers a very wide range of baud rates.

●

1 Mbit/s full duplex SCI

SPI1 emulation

High precision baud rate generator

Smartcard emulation

IrDA SIR encoder decoder

Single wire half duplex mode

Note:

USART1 can be served by the DMA1 Controller.

3.14

Infrared (IR) interface

The low density STM8L05xxx devices contain an infrared interface which can be used with

an IR LED for remote control functions. Two timer output compare channels are used to

generate the infrared remote control signals.

3.15

Development support

Development tools

Development tools for the STM8 microcontrollers include:

●

The STice emulation system offering tracing and code profiling

●

The STVD high-level language debugger including C compiler, assembler and

integrated development environment

●

The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit

debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time

in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory

programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured

emulator. Beside memory and peripherals, CPU operation can also be monitored in real-

time by means of shadow registers.

Doc ID 022985 Rev 1

19/46

Functional overview

STM8L051F3

Bootloader

The low density value line STM8L05xxx ultra low power devices feature a built-in bootloader

(see UM0560: STM8 bootloader user manual).

The bootloader is used to download application software into the device memories,

including RAM, program and data memory, using standard serial interfaces. It is a

complementary solution to programming via the SWIM debugging interface.

20/46

Doc ID 022985 Rev 1

STM8L051F3

Pin description

4

Pin description

Figure 3.

STM8L051Fx 20-pin TSSOP20 package pinout

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Table 4.

Low density value line STM8L05xxx pin description

n°

Input

Output

Pin name

Default alternate function

4

5

NRST/PA1⁽¹⁾

I/O

X

HS

X Reset PA1

PA2/OSC_IN/[USART_TX]⁽²⁾

/

HSE oscillator input / [USART

I/O X

X

X HS

X

X Port A2

X Port A3

[SPI_MISO] ⁽²⁾

transmit] / [SPI master in- slave out]

PA3/OSC_OUT/[USART_RX]⁽²⁾/[

HSE oscillator output / [USART

receive]/ [SPI master out/slave in]/

6

I/O X

X

SPI_MOSI]⁽²⁾

10 PB0⁽³⁾/TIM2_CH1/ADC1_IN18

11 PB1/TIM3_CH1/ADC1_IN17

12 PB2/ TIM2_CH2/ ADC1_IN16

I/O X

X

X HS

X

X Port B0 Timer 2 - channel 1 / ADC1_IN18

X Port B1 Timer 3 - channel 1 / ADC1_IN17

X Port B2 Timer 2 - channel 2 ADC1_IN16

PB3/TIM2_ETR/

13

Timer 2 - external trigger /

X Port B3

I/O X

X

X HS

X

ADC1_IN15/RTC_ALARM

ADC1_IN15 / RTC_ALARM

SPI master/slave select /

X Port B4

14 PB4⁽³⁾/SPI1_NSS/ADC1_IN14

ADC1_IN14

PB5/SPI_SCK/

15

X Port B5 [SPI clock] / ADC1_IN13

/ADC1_IN13

PB6/SPI1_MOSI/

16

SPI master out/

X Port B6

ADC1_IN12

slave in / ADC1_IN12

Doc ID 022985 Rev 1

21/46

Pin description

STM8L051F3

Table 4.

Low density value line STM8L05xxx pin description (continued)

n°

Input

Output

Pin name

Default alternate function

SPI1 master in- slave out/

ADC1_IN11

17 PB7/SPI1_MISO/ADC1_IN11

I/O X

X

X HS

X

X Port B7

18 PC0/I2C_SDA

19 PC1/I2C_SCL

I/O X

X

T⁽⁴⁾

T⁽³⁾

Port C0 I2C data

Port C1 I2C clock

USART synchronous clock /

PC4/USART_CK]/

20

I/O X

X

X HS

X

X Port C4 I2C1_SMB / Configurable clock

I2C_SMB/CCO/ADC1_IN4

output / ADC1_IN4

LSE oscillator input / [SPI

X Port C5 master/slave select] / [USART

transmit]/Timer 2 -channel 1

PC5/OSC32_IN /[SPI1_NSS]⁽²⁾

/

1

[USART_TX]⁽²⁾/TIM2_CH1

LSE oscillator output / [SPI clock] /

X Port C6 [USART receive]/

Timer 2 -channel 2

PC6/OSC32_OUT/[SPI_SCK]⁽²⁾/[

USART_RX]⁽²⁾/TIM2_CH2

2

X

X HS

X

PD0/TIM3_CH2/[ADC1_TRIG]⁽²⁾

ADC1_IN22

/

Timer 3 - channel 2 / [ADC1_Trigger]

/ ADC1_IN22

9

8

7

I/O X

X Port D0

Digital supply voltage /

ADC1 positive voltage reference

V_DD/ V_DDA/ V_REF+

S

Ground voltage / ADC1 negative voltage

reference / Analog ground voltage

V_SS/ V_REF-/ V_SSA

[USART1 synchronous clock]⁽²⁾

/

PA0⁽⁵⁾/[USART_CK]⁽²⁾

SWIM/BEEP/IR_TIM ⁽⁶⁾

/

HS

3

I/O X

X

X Port A0 SWIM input and output /

(6)

Beep output / Infrared Timer output

1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be

configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1

pin as general purpose output in the STM8L15xxx and STM8L16xxx reference manual (RM0031).

2. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a

duplication of the function).

3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V_DDare not

implemented).

5. The PA0 pin is in input pull-up during the reset phase and after reset release.

6. High Sink LED driver capability available on PA0.

Note:

The slope control of all GPIO pins, except true open drain pins, can be programmed. By

default, the slope control is limited to 2 MHz.

22/46

Doc ID 022985 Rev 1

STM8L051F3

Pin description

4.1

System configuration options

As shown in Table 4: Low density value line STM8L05xxx pin description, some alternate

functions can be remapped on different I/O ports by programming one of the two remapping

registers described in the “ Routing interface (RI) and system configuration controller”

section in the STM8L15xx and STM8L16xx reference manual (RM0031).

Doc ID 022985 Rev 1

23/46

Memory and register map

STM8L051F3

5

Memory and register map

5.1

Memory mapping

The memory map is shown in Figure 4.

Figure 4.

Memory map

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address.

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registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.

24/46

Doc ID 022985 Rev 1

STM8L051F3

Memory and register map

End address

Table 5.

Flash and RAM boundary addresses

Memory area

Size

Start address

RAM

1 Kbyte

0x00 0000

0x00 8000

0x00 03FF

0x00 9FFF

Flash program memory

8 Kbytes

5.2

Register map

Table 6.

I/O port hardware register map

Reset

status

Address

Block

Register label

Register name

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

0x00 500B

0x00 500C

0x00 500D

0x00 500E

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

PA_ODR

PA_IDR

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

0x00

0xXX

0x00

0x01

0x00

0xXX

0x00

0xXX

0x00

0xXX

0x00

Port A

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PB_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B

Port C

Port D

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

0x00 5014

to

Reserved area (0 bytes)

0x00 501D

Doc ID 022985 Rev 1

25/46

Memory and register map

STM8L051F3

Table 7.

Address

General hardware register map

Reset

status

Block

Register label

Register name

0x00 502E

to

Reserved area (44 bytes)

0x00 5049

0x00 5050

0x00 5051

0x00 5052

0x00 5053

0x00 5054

FLASH_CR1

FLASH_CR2

Flash control register 1

Flash control register 2

0x00

Flash

FLASH _PUKR

FLASH _DUKR

FLASH _IAPSR

Flash program memory unprotection key register

Data EEPROM unprotection key register

0x00

Flash in-application programming status register

0x00 5055

to

Reserved area (27 bytes)

0x00 506F

0x00 5070

0x00 5071

DMA1_GCSR

DMA1_GIR1

DMA1 global configuration & status register

DMA1 global interrupt register 1

0xFC

0x00

0x00 5072 to

0x00 5074

Reserved area (3

bytes)

0x00 5075

0x00 5076

DMA1_C0CR

DMA1 channel 0 configuration register

DMA1 channel 0 status & priority register

0x00

DMA1_C0SPR

DMA1 number of data to transfer register

(channel 0)

0x00 5077

0x00 5078

DMA1_C0NDTR

DMA1_C0PARH

DMA1_C0PARL

0x00

0x52

0x00

DMA1

DMA1 peripheral address high register

(channel 0)

DMA1 peripheral address low register

(channel 0)

0x00 5079

0x00 507A

0x00 507B

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 0)

DMA1_C0M0ARH

DMA1_C0M0ARL

0x00

DMA1 memory 0 address low register

(channel 0)

0x00 507C

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Doc ID 022985 Rev 1

STM8L051F3

Table 7. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 507D to

0x00 507E

Reserved area (2 bytes)

0x00 507F

0x00 5080

DMA1_C1CR

DMA1 channel 1 configuration register

DMA1 channel 1 status & priority register

0x00

DMA1_C1SPR

DMA1 number of data to transfer register

(channel 1)

0x00 5081

0x00 5082

DMA1_C1NDTR

DMA1_C1PARH

DMA1_C1PARL

0x00

0x52

0x00

DMA1 peripheral address high register

(channel 1)

DMA1 peripheral address low register

(channel 1)

0x00 5083

0x00 5084

0x00 5085

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 1)

DMA1_C1M0ARH

DMA1_C1M0ARL

0x00

DMA1 memory 0 address low register

(channel 1)

0x00 5086

0x00 5087

0x00 5088

Reserved area (2 bytes)

0x00 5089

0x00 508A

DMA1_C2CR

DMA1 channel 2 configuration register

DMA1 channel 2 status & priority register

0x00

DMA1_C2SPR

DMA1 number of data to transfer register

(channel 2)

DMA1

0x00 508B

0x00 508C

DMA1_C2NDTR

DMA1_C2PARH

DMA1_C2PARL

0x00

0x52

0x00

DMA1 peripheral address high register

(channel 2)

DMA1 peripheral address low register

(channel 2)

0x00 508D

0x00 508E

0x00 508F

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 2)

DMA1_C2M0ARH

DMA1_C2M0ARL

0x00

DMA1 memory 0 address low register

(channel 2)

0x00 5090

0x00 5091

0x00 5092

Reserved area (2 bytes)

0x00 5093

0x00 5094

DMA1_C3CR

DMA1 channel 3 configuration register

DMA1 channel 3 status & priority register

0x00

DMA1_C3SPR

DMA1 number of data to transfer register

(channel 3)

0x00 5095

0x00 5096

0x00 5097

DMA1_C3NDTR

0x00

0x40

0x00

DMA1_C3PARH_

C3M1ARH

DMA1 peripheral address high register

(channel 3)

DMA1_C3PARL_

C3M1ARL

DMA1 peripheral address low register

(channel 3)

Doc ID 022985 Rev 1

27/46

Memory and register map

Table 7. General hardware register map (continued)

Address

STM8L051F3

Reset

status

Block

Register label

Register name

DMA channel 3 memory 0 extended address

register

0x00 5098

0x00 5099

0x00 509A

DMA_C3M0EAR

DMA1_C3M0ARH

DMA1_C3M0ARL

0x00

DMA1 memory 0 address high register

(channel 3)

DMA1

DMA1 memory 0 address low register

(channel 3)

0x00 509B to

0x00 509C

Reserved area (3 bytes)

0x00 509D

0x00 509E

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2

0x00 50A3

0x00 50A4

0x00 50A5

0x00 50A6

0x00 50A7

0x00 50A8

0x00 50A9

0x00 50AA

0x00 50AB

SYSCFG_RMPCR3

SYSCFG_RMPCR1

SYSCFG_RMPCR2

EXTI_CR1

Remapping register 3

Remapping register 1

0x00

SYSCFG

Remapping register 2

External interrupt control register 1

External interrupt control register 2

External interrupt control register 3

External interrupt status register 1

External interrupt status register 2

External interrupt port select register 1

WFE control register 1

EXTI_CR2

EXTI_CR3

ITC - EXTI

EXTI_SR1

EXTI_SR2

EXTI_CONF1

WFE_CR1

WFE_CR2

WFE control register 2

WFE

WFE_CR3

WFE control register 3

WFE_CR4

WFE control register 4

EXTI_CR4

External interrupt control register 4

External interrupt port select register 2

ITC - EXTI

EXTI_CONF2

0x00 50A9

to

Reserved area (7 bytes)

0x00 50AF

0x00 50B0

0x00 50B1

0x00 50B2

0x00 50B3

RST_CR

RST_SR

Reset control register

Reset status register

0x00

0x01

0x00

RST

PWR_CSR1

PWR_CSR2

Power control and status register 1

Power control and status register 2

PWR

0x00 50B4

to

Reserved area (12 bytes)

0x00 50BF

0x00 50C0

0x00 50C1

0x00 50C2

0x00 50C3

CLK_CKDIVR

CLK_CRTCR

CLK_ICKCR

CLK Clock master divider register

CLK Clock RTC register

0x03

0x00⁽¹⁾

0x11

CLK

CLK Internal clock control register

CLK Peripheral clock gating register 1

CLK_PCKENR1

0x00

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Doc ID 022985 Rev 1

STM8L051F3

Table 7. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x00 50CA

0x00 50CB

0x00 50CC

0x00 50CD

0x00 50CE

CLK_PCKENR2

CLK_CCOR

CLK Peripheral clock gating register 2

CLK Configurable clock control register

CLK External clock control register

CLK System clock status register

CLK System clock switch register

CLK Clock switch control register

CLK Clock security system register

CLK Clock BEEP register

0x00

0x01

0xX0

0x00

0xXX

0x00

CLK_ECKCR

CLK_SCSR

CLK_SWR

CLK_SWCR

CLK_CSSR

CLK

CLK_CBEEPR

CLK_HSICALR

CLK_HSITRIMR

CLK_HSIUNLCKR

CLK HSI calibration register

CLK HSI clock calibration trimming register

CLK HSI unlock register

0bxx11 1

00X

0x00 50CF

0x00 50D0

CLK_REGCSR

CLK_PCKENR3

CLK Main regulator control status register

CLK Peripheral clock gating register 3

0x00

0x00 50D1

to

Reserved area (2 bytes)

0x00 50D2

0x00 50D3

0x00 50D4

WWDG_CR

WWDG_WR

WWDG control register

WWDR window register

0x7F

WWDG

IWDG

0x00 50D5

to

00 50DF

Reserved area (11 bytes)

0x00 50E0

0x00 50E1

0x00 50E2

IWDG_KR

IWDG_PR

IWDG_RLR

IWDG key register

IWDG prescaler register

IWDG reload register

0x01

0x00

0xFF

0x00 50E3

to

Reserved area (13 bytes)

0x00 50EF

0x00 50F0

BEEP_CSR1

BEEP_CSR2

BEEP control/status register 1

Reserved area (2 bytes)

0x00

0x1F

0x00 50F1

0x00 50F2

BEEP

0x00 50F3

BEEP control/status register 2

Reserved area (76 bytes)

0x00 50F4

to0x00 513F

0x00 5140

0x00 5141

0x00 5142

RTC_TR1

RTC_TR2

RTC_TR3

RTC Time register 1

RTC Time register 2

RTC Time register 3

0x00

RTC

Doc ID 022985 Rev 1

29/46

Memory and register map

Table 7. General hardware register map (continued)

Address

STM8L051F3

Reset

status

Block

Register label

Register name

0x00 5143

0x00 5144

0x00 5145

0x00 5146

0x00 5147

0x00 5148

0x00 5149

0x00 514A

0x00 514B

0x00 514C

0x00 514D

Reserved area (1 byte)

RTC Date register 1

RTC_DR1

RTC_DR2

RTC_DR3

0x01

0x21

0x00

RTC Date register 2

RTC Date register 3

Reserved area (1 byte)

RTC Control register 1

RTC_CR1

RTC_CR2

RTC_CR3

0x00⁽¹⁾

RTC Control register 2

RTC Control register 3

Reserved area (1 byte)

RTC Initialization and status register 1

RTC Initialization and Status register 2

RTC_ISR1

RTC_ISR2

0x01

0x00

0x00 514E

0x00 514F

Reserved area (2 bytes)

0x00 5150

0x00 5151

0x00 5152

0x00 5153

0x00 5154

0x00 5155

0x00 5156

0x00 5157

0x00 5158

0x00 5159

0x00 5158

0x00 5159

0x00 515A

0x00 515B

0x00 515C

0x00 515D

0x00 515E

0x00 515F

RTC_SPRERH

RTC_SPRERL

RTC_APRER

RTC Synchronous prescaler register high

RTC Synchronous prescaler register low

RTC Asynchronous prescaler register

Reserved area (1 byte)

0x00⁽¹⁾

0xFF⁽¹⁾

0x7F⁽¹⁾

RTC

RTC_WUTRH

RTC_WUTRL

RTC Wakeup timer register high

RTC Wakeup timer register low

Reserved area (1 byte)

0xFF⁽¹⁾

RTC_SSRL

RTC_SSRH

RTC Subsecond register low

RTC Subsecond register high

RTC Write protection register

RTC Subsecond register high

RTC Write protection register

RTC Shift register high

0x00

RTC_WPR

0x00

RTC_SSRH

0x00

RTC_WPR

0x00

RTC_SHIFTRH

RTC_SHIFTRL

RTC_ALRMAR1

RTC_ALRMAR2

RTC_ALRMAR3

RTC_ALRMAR4

0x00

RTC Shift register low

0x00

RTC Alarm A register 1

0x00⁽¹⁾

RTC Alarm A register 2

RTC Alarm A register 3

RTC Alarm A register 4

0x00 5160 to

0x00 5163

Reserved area (4 bytes)

0x00 5164

0x00 5165

RTC_ALRMASSRH

RTC_ALRMASSRL

RTC Alarm A subsecond register high

RTC Alarm A subsecond register low

0x00⁽¹⁾

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Doc ID 022985 Rev 1

STM8L051F3

Table 7. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 5166

RTC_ALRMASSMSKR

RTC Alarm A masking register

Reserved area (3 bytes)

0x00⁽¹⁾

0x00 5167 to

0x00 5169

0x00 516A

0x00 516B

0x00 516C

0x00 516D

RTC_CALRH

RTC_CALRL

RTC_TCR1

RTC_TCR2

RTC Calibration register high

RTC Calibration register low

RTC Tamper control register 1

RTC Tamper control register 2

0x00⁽¹⁾

RTC

0x00 516E to

0x00 518A

Reserved area (36 bytes)

0x00 5190

CSSLSE_CSR

CSS on LSE control and status register

0x00⁽¹⁾

0x00 519A to

0x00 51FF

Reserved area (111 bytes)

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

SPI1_CR1

SPI1_CR2

SPI1 control register 1

SPI1 control register 2

SPI1 interrupt control register

SPI1 status register

0x00

0x02

0x00

0x07

0x00

SPI1_ICR

SPI1_SR

SPI1

SPI1_DR

SPI1 data register

SPI1_CRCPR

SPI1_RXCRCR

SPI1_TXCRCR

SPI1 CRC polynomial register

SPI1 Rx CRC register

SPI1 Tx CRC register

0x00 5208

to

Reserved area (8 bytes)

0x00 520F

0x00 5210

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

I2C1_CR1

I2C1_CR2

I2C1_FREQR

I2C1_OARL

I2C1_OARH

I2C1_OAR2

I2C1_DR

I2C1 control register 1

I2C1 control register 2

0x00

0x0X

0x00

I2C1 frequency register

I2C1 own address register low

I2C1 own address register high

I2C1 own address register for dual mode

I2C1 data register

I2C1

I2C1_SR1

I2C1_SR2

I2C1_SR3

I2C1_ITR

I2C1 status register 1

I2C1 status register 2

I2C1 status register 3

I2C1 interrupt control register

I2C1 clock control register low

I2C1 clock control register high

I2C1_CCRL

I2C1_CCRH

Doc ID 022985 Rev 1

31/46

Memory and register map

Table 7. General hardware register map (continued)

Address

STM8L051F3

Reset

status

Block

Register label

Register name

0x00 521D

0x00 521E

I2C1_TRISER

I2C1_PECR

I2C1 TRISE register

0x02

0x00

I2C1

I2C1 packet error checking register

0x00 521F

to

Reserved area (17 bytes)

0x00 522F

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238

0x00 5239

0x00 523A

USART1_SR

USART1_DR

USART1 status register

USART1 data register

0xC0

0xXX

0x00

USART1_BRR1

USART1_BRR2

USART1_CR1

USART1_CR2

USART1_CR3

USART1_CR4

USART1_CR5

USART1_GTR

USART1_PSCR

USART1 baud rate register 1

USART1 baud rate register 2

USART1 control register 1

USART1 control register 2

USART1 control register 3

USART1 control register 4

USART1 control register 5

USART1 guard time register

USART1 prescaler register

USART1

0x00 523B

to

Reserved area (21 bytes)

0x00 524F

0x00 5250

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

TIM2_CR1

TIM2_CR2

TIM2 control register 1

TIM2 control register 2

0x00

0xFF

TIM2_SMCR

TIM2_ETR

TIM2 Slave mode control register

TIM2 external trigger register

TIM2 DMA1 request enable register

TIM2 interrupt enable register

TIM2 status register 1

TIM2_DER

TIM2_IER

TIM2_SR1

TIM2_SR2

TIM2 status register 2

TIM2

TIM2_EGR

TIM2_CCMR1

TIM2_CCMR2

TIM2_CCER1

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2 event generation register

TIM2 capture/compare mode register 1

TIM2 capture/compare mode register 2

TIM2 capture/compare enable register 1

TIM2 counter high

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

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Doc ID 022985 Rev 1

STM8L051F3

Table 7. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 5260

0x00 5261

0x00 5262

0x00 5263

0x00 5264

0x00 5265

0x00 5266

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_BKR

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare register 2 high

TIM2 capture/compare register 2 low

TIM2 break register

0xFF

0x00

TIM2

TIM2_OISR

TIM2 output idle state register

0x00 5267 to

0x00 527F

Reserved area (25 bytes)

0x00 5280

0x00 5281

0x00 5282

0x00 5283

0x00 5284

0x00 5285

0x00 5286

0x00 5287

0x00 5288

0x00 5289

0x00 528A

0x00 528B

0x00 528C

0x00 528D

0x00 528E

0x00 528F

0x00 5290

0x00 5291

0x00 5292

0x00 5293

0x00 5294

0x00 5295

0x00 5296

TIM3_CR1

TIM3_CR2

TIM3 control register 1

TIM3 control register 2

0x00

0xFF

0x00

TIM3_SMCR

TIM3_ETR

TIM3 Slave mode control register

TIM3 external trigger register

TIM3 DMA1 request enable register

TIM3 interrupt enable register

TIM3 status register 1

TIM3_DER

TIM3_IER

TIM3_SR1

TIM3_SR2

TIM3 status register 2

TIM3_EGR

TIM3 event generation register

TIM3 Capture/Compare mode register 1

TIM3 Capture/Compare mode register 2

TIM3 Capture/Compare enable register 1

TIM3 counter high

TIM3_CCMR1

TIM3_CCMR2

TIM3_CCER1

TIM3_CNTRH

TIM3_CNTRL

TIM3_PSCR

TIM3_ARRH

TIM3_ARRL

TIM3_CCR1H

TIM3_CCR1L

TIM3_CCR2H

TIM3_CCR2L

TIM3_BKR

TIM3

TIM3 counter low

TIM3 prescaler register

TIM3 Auto-reload register high

TIM3 Auto-reload register low

TIM3 Capture/Compare register 1 high

TIM3 Capture/Compare register 1 low

TIM3 Capture/Compare register 2 high

TIM3 Capture/Compare register 2 low

TIM3 break register

TIM3_OISR

TIM3 output idle state register

0x00 5297 to

0x00 52DF

Reserved area (72 bytes)

Doc ID 022985 Rev 1

33/46

Memory and register map

Table 7. General hardware register map (continued)

Address

STM8L051F3

Reset

status

Block

Register label

Register name

0x00 52E0

0x00 52E1

0x00 52E2

0x00 52E3

0x00 52E4

0x00 52E5

0x00 52E6

0x00 52E7

0x00 52E8

0x00 52E9

TIM4_CR1

TIM4_CR2

TIM4_SMCR

TIM4_DER

TIM4_IER

TIM4 control register 1

TIM4 control register 2

0x00

TIM4 Slave mode control register

TIM4 DMA1 request enable register

TIM4 Interrupt enable register

TIM4 status register 1

TIM4

TIM4_SR1

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

TIM4 Event generation register

TIM4 counter

TIM4 prescaler register

TIM4 Auto-reload register

0x00 52EA

to

0x00 52FE

Reserved area (21 bytes)

Infrared control register

Reserved area (41 bytes)

0x00 52FF

IRTIM

IR_CR

0x00

0x00 5317

to

0x00 533F

0x00 5340

0x00 5341

0x00 5342

0x00 5343

0x00 5344

0x00 5345

0x00 5346

0x00 5347

0x00 5348

0x00 5349

0x00 534A

0x00 534B

0x00 534C

0x00 534D

0x00 534E

0x00 534F

0x00 5350

0x00 5351

ADC1_CR1

ADC1_CR2

ADC1 configuration register 1

ADC1 configuration register 2

ADC1 configuration register 3

ADC1 status register

0x00

0x1F

0x00

0x0F

0xFF

0x00

ADC1_CR3

ADC1_SR

ADC1_DRH

ADC1_DRL

ADC1 data register high

ADC1 data register low

ADC1_HTRH

ADC1_HTRL

ADC1_LTRH

ADC1_LTRL

ADC1_SQR1

ADC1_SQR2

ADC1_SQR3

ADC1_SQR4

ADC1_TRIGR1

ADC1_TRIGR2

ADC1_TRIGR3

ADC1_TRIGR4

ADC1 high threshold register high

ADC1 high threshold register low

ADC1 low threshold register high

ADC1 low threshold register low

ADC1 channel sequence 1 register

ADC1 channel sequence 2 register

ADC1 channel sequence 3 register

ADC1 channel sequence 4 register

ADC1 trigger disable 1

ADC1

ADC1 trigger disable 2

ADC1 trigger disable 3

ADC1 trigger disable 4

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Doc ID 022985 Rev 1

STM8L051F3

Table 7. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 53C8 to

0x00 542F

Reserved area(104 bytes)

0x00 5430

0x00 5431

0x00 5432

0x00 5433

0x00 5434

0x00 5435

0x00 5436

0x00 5437

0x00 5438

0x00 5439

0x00 543A

0x00 543B

0x00 543C

0x00 543D

0x00 543E

0x00 543F

Reserved area (1 byte)

0x00

0xXX

0x00

0xFF

0x00

RI_ICR1

RI_ICR2

RI Timer input capture routing register 1

RI Timer input capture routing register 2

RI I/O input register 1

RI_IOIR1

RI_IOIR2

RI I/O input register 2

RI_IOIR3

RI I/O input register 3

RI_IOCMR1

RI_IOCMR2

RI_IOCMR3

RI_IOSR1

RI_IOSR2

RI_IOSR3

RI_IOGCR

RI_ASCR1

RI_ASCR2

RI_RCR

RI I/O control mode register 1

RI I/O control mode register 2

RI I/O control mode register 3

RI I/O switch register 1

RI

RI I/O switch register 2

RI I/O switch register 3

RI I/O group control register

Analog switch register 1

RI Analog switch register 2

RI Resistor control register

0x00 5440

to

Reserved area (16 bytes)

0x00 544F

0x00 5450

0x00 5451

0x00 5452

0x00 5453

0x00 5454

0x00 5455

0x00 5456

0x00 5457

RI_CR

RI I/O control register

RI I/O mask register 1

RI I/O mask register 2

RI I/O mask register 3

RI I/O mask register 4

RI I/O input register 4

RI I/O control mode register 4

RI I/O switch register 4

0x00

0xXX

0x00

RI_MASKR1

RI_MASKR2

RI_MASKR3

RI_MASKR4

RI_IOIR4

RI

RI_IOCMR4

RI_IOSR4

1. These registers are not impacted by a system reset. They are reset at power-on.

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Memory and register map

Table 8. CPU/SWIM/debug module/interrupt controller registers

Address

STM8L051F3

Reset

status

Block

Register label

Register name

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

A

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

0x00

0x03

0xFF

0x28

PCE

PCH

PCL

XH

CPU⁽¹⁾

XL

YH

YL

SPH

SPL

CCR

Stack pointer low

Condition code register

0x00 7F0B to

0x00 7F5F

Reserved area (85 bytes)

CPU

0x00 7F60

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

CFG_GCR

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

Global configuration register

0x00

0xFF

Interrupt Software priority register 1

Interrupt Software priority register 2

Interrupt Software priority register 3

Interrupt Software priority register 4

Interrupt Software priority register 5

Interrupt Software priority register 6

Interrupt Software priority register 7

Interrupt Software priority register 8

ITC-SPR

0x00 7F78

to

0x00 7F79

Reserved area (2 bytes)

SWIM control status register

Reserved area (15 bytes)

0x00 7F80

SWIM

SWIM_CSR

0x00

0x00 7F81

to

0x00 7F8F

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

DM Debug module control register 1

0xFF

0x00

DM

36/46

Doc ID 022985 Rev 1

STM8L051F3

Table 8.

Address

Memory and register map

Reset

CPU/SWIM/debug module/interrupt controller registers (continued)

Block

Register label

Register name

status

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

DM Debug module control register 2

DM Debug module control/status register 1

DM Debug module control/status register 2

DM enable function register

0x00

0x10

0x00

0xFF

DM

0x00 7F9B

to

Reserved area (5 bytes)

0x00 7F9F

1. Accessible by debug module only

Doc ID 022985 Rev 1

37/46

Interrupt vector mapping

STM8L051F3

6

Interrupt vector mapping

Table 9.

Interrupt mapping

Wakeup

from

Active-halt

mode

Wakeup

from Wait from Wait

(WFI

mode)

Wakeup

from Halt

mode

Vector

IRQ

No.

Source

block

Description

(WFE

address

mode)⁽¹⁾

RESET

TRAP

TLI⁽²⁾

Reset

Yes

0x00 8000

0x00 8004

0x00 8008

Software interrupt

-

0

1

External Top level Interrupt

FLASH end of programing/

write attempted to

FLASH

-

Yes

0x00 800C

0x00 8010

protected page interrupt

DMA1 channels 0/1 half

2

DMA1 0/1 transaction/transaction

complete interrupt

DMA1 channels 2/3 half

DMA1 2/3 transaction/transaction

complete interrupt

3

4

-

Yes

0x00 8014

0x00 8018

RTC alarm A/wakeup/

RTC

Yes

tamper 1/tamper 2/tamper 3

5

6

PVD

PVD interrupt

Yes

0x00 801C

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

0x00 8034

0x00 8038

0x00 803C

0x00 8040

0x00 8044

0x00 8048

EXTIB

EXTID

EXTI0

EXTI1

EXTI2

EXTI3

EXTI4

EXTI5

EXTI6

EXTI7

External interrupt port B

External interrupt port D

External interrupt 0

External interrupt 1

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

External interrupt 7

7

Yes

8

Yes

9

Yes

10

11

12

13

14

15

16

Yes

Reserved

CLK system clock

switch/CSS interrupt

17

CLK

-

Yes

0x00 804C

ACD1 end of conversion/

analog watchdog/

18

ADC1

Yes

0x00 8050

overrun interrupt

TIM2 update

19

TIM2

/overflow/trigger/break

interrupt

-

Yes

0x00 8054

38/46

Doc ID 022985 Rev 1

STM8L051F3

Interrupt vector mapping

Table 9.

Interrupt mapping (continued)

Wakeup

from

Active-halt

mode

Wakeup

from Wait from Wait

(WFI

mode)

Wakeup

from Halt

mode

Vector

IRQ

No.

Source

block

Description

(WFE

address

mode)⁽¹⁾

TIM2 Capture/Compare

interrupt

20

21

22

TIM2

TIM3

-

Yes

0x00 8058

0x00 805C

0x00 8060

TIM3 Update

/Overflow/Trigger/Break

interrupt

TIM3 Capture/Compare

interrupt

TIM3

RI

-

Yes

-

23

24

RI trigger interrupt

-

0x00 8064

0x00 8068

Reserved

TIM4 update/overflow/

trigger interrupt

25

26

TIM4

SPI1

-

Yes

0x00 806C

0x00 8070

SPI1 TX buffer empty/

RX buffer not empty/

error/wakeup interrupt

Yes

USART1 transmit data

register empty/

27

USART 1

-

Yes

0x00 8074

transmission complete

interrupt

USART1 received data

ready/overrun error/

28

29

USART 1

I²C1

-

Yes

0x00 8078

0x00 807C

idle line detected/parity

error/global error interrupt

I²C1 interrupt⁽³⁾

Yes

1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the

interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.

When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.

2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.

3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

Doc ID 022985 Rev 1

39/46

Package characteristics

STM8L051F3

7

Package characteristics

7.1

ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

40/46

Doc ID 022985 Rev 1

STM8L051F3

Package characteristics

7.2

Package mechanical data

7.2.1

20-lead thin shrink small package (TSSOP20)

Figure 5.

TSSOP20 20-lead thin shrink small package Figure 6.

outline

TSSOP20 recommended

footprint

D

20

11

c

E1

E

1

10

α

A1

L

A

A2

L1

CP

b

e

TSSOP20-M

BJꢁꢂꢃꢄꢁ

1. Drawing is not to scale

2. Dimensions are in millimeters

Table 10. TSSOP20 20-lead thin shrink small package, mechanical data

Dim.

mm

Typ

inches⁽¹⁾

Min

Max

Min

Typ

Max

A

A1

A2

b

1.2

0.15

1.05

0.3

0.2

6.6

4.5

-

0.0472

0.0059

0.0413

0.0118

0.0079

0.2598

0.1772

-

0.05

0.8

0.19

0.09

6.4

6.2

4.3

-

0.0020

0.0315

0.0075

0.0035

0.2520

0.2441

0.1693

1

0.0394

c

D

6.5

6.4

4.4

0.65

0.6

1

0.2559

0.252

E

E1

e

0.1732

0.0256

0.0236

0.0394

L

0.45

0.75

0.0177

0.0295

L1

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 022985 Rev 1

41/46

Package characteristics

STM8L051F3

7.2.2

32-pin Low profile quad flat package (LQFP32)

Figure 7.

LQFP32 32-pin low profile quad flat package outline

ccc

C

D

D1

D3

A

A2

24

17

16

25

32

L1

b

E3

E1 E

9

L

Pin 1

A1

K

1

8

identification

c

5V_ME

Table 11. LQFP32 32-pin low profile quad flat package, mechanical data

Dim.

millimeters

Typ

inches

Typ

Min

Max

Min

Max

A

A1

A2

b

1.600

0.150

1.450

0.450

0.200

9.200

7.200

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

0.050

1.350

0.300

0.090

8.800

6.800

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

1.400

0.370

0.0551

0.0146

c

D

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

0.3543

0.2756

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

D1

D3

E

8.800

6.800

9.200

7.200

0.3465

0.2677

0.3622

0.2835

E1

E3

e

L

0.450

0.750

0.0177

0.0295

L1

42/46

Doc ID 022985 Rev 1

STM8L051F3

Figure 8.

Package characteristics

LQFP32 recommended footprint

9.40

7.70

0.54

9.40

0.80

5V_FP

1. Dimensions are in millimeters

Doc ID 022985 Rev 1

43/46

Device ordering information

STM8L051F3

8

Device ordering information

Figure 9.

Low density value line STM8L05xxx ordering information scheme

Example:

STM8

L

051

F

3

P

6

Product class

STM8 microcontroller

Family type

L = Low power

Sub-family type

051 = Ultra low power

Pin count

F = 20 pins

Program memory size

3 = 8 Kbytes

Package

P = TSSOP

Temperature range

6 = – 40 to 85 °C

For a list of available options (e.g. memory size, package) and orderable part numbers or for

further information on any aspect of this device, please contact the ST sales office nearest to you.

44/46

Doc ID 022985 Rev 1

STM8L051F3

Revision history

9

Revision history

Table 12. Document revision history

Date

Revision

Changes

23-Apr-2012

1

Initial release.

Doc ID 022985 Rev 1

45/46

STM8L051F3

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46/46

Doc ID 022985 Rev 1


型号：	STM8L051F3P6
厂家：	ST
描述：	Value line, 8-bit ultralow power MCU, 8-KB Flash 时钟微控制器光电二极管外围集成电路
文件：	总46页 (文件大小：346K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM8L051F3P6 [STMICROELECTRONICS]

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