STM8L052C6T6 [STMICROELECTRONICS]
Value Line, 8-bit ultralow power MCU, 32-KB Flash, 256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC; 价值线， 8位超低功耗MCU ， 32 KB的闪存， 256字节的数据EEPROM ， RTC ， LCD，定时器， USART ， I2C ， SPI ， ADC
| 型号： | STM8L052C6T6 |
| 厂家： | 
ST |
| 描述： | Value Line, 8-bit ultralow power MCU, 32-KB Flash, 256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC |
| 文件： | 总102页 (文件大小：1469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM8L052C6
Value Line, 8-bit ultralow power MCU, 32-KB Flash,
256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC
Datasheet − production data
Features
■ Operating conditions
– Operating power supply: 1.8 V to 3.6 V
– Temperature range: -40 °C to 85 °C
LQFP48
■ Low power features
– 5 low power modes: Wait, Low power run
■ DMA
– 4 channels supporting ADC, SPI, I2C,
(5.1 µA), Low power wait (3 µA), Active-halt
with full RTC (1.3 µA), Halt (350 nA)
– Consumption: 195 µA/MHz + 440 µA
– Ultra-low leakage per I/0: 50 nA
– Fast wakeup from Halt: 4.7 µs
USART, timers
– 1 channel for memory-to-memory
■ 12-bit ADC up to 1 Msps/25 channels
– Internal reference voltage
■ Advanced STM8 core
– Harvard architecture and 3-stage pipeline
– Max freq. 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
■ Timers
– Two 16-bit timers with 2 channels (used as
IC, OC, PWM), quadrature encoder
– One 16-bit advanced control timer with 3
channels, supporting motor control
– One 8-bit timer with 7-bit prescaler
– 2 watchdogs: 1 Window, 1 Independent
– Beeper timer with 1, 2 or 4 kHz frequencies
■ Reset and supply management
– Low power, ultra-safe BOR reset with 5
selectable thresholds
– Ultra low power POR/PDR
– Programmable voltage detector (PVD)
■ Communication interfaces
■ Clock management
– Synchronous serial interface (SPI)
– Fast I2C 400 kHz SMBus and PMBus
– USART (ISO 7816 interface and IrDA)
– 32 kHz and 1 to 16 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– Internal 38 kHz low consumption RC
– Clock security system
■ Up to 41 I/Os, all mappable on interrupt vectors
■ Low power RTC
■ Development support
– BCD calendar with alarm interrupt
– Auto-wakeup from Halt w/ periodic interrupt
– Fast on-chip programming and non-
intrusive debugging with SWIM
– Bootloader using USART
■ LCD: up to 4x28 segments w/ step-up
converter
■ Memories
– 32 KB Flash program memory and
256 bytes data EEPROM with ECC, RWW
– Flexible write and read protection modes
– 2 Kbytes of RAM
June 2012
Doc ID 023331 Rev 1
1/102
This is information on a product in full production.
www.st.com
1
Contents
STM8L052C6
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1
3.2.2
Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1
3.3.2
3.3.3
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
3.5
3.6
3.7
3.8
3.9
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 System configuration controller and routing interface . . . . . . . . . . . . . . . 19
3.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Contents
3.14.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4
5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
5.2
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
7
8
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2
8.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Embedded reset and power control block characteristics . . . . . . . . . . . 56
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.3.11 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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9
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.1
9.2
ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.2.1
48-pin low profile quad flat 7x7mm package (LQFP48) . . . . . . . . . . . . . 98
10
11
Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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List of tables
List of tables
Table 1.
Medium density value line STM8L05xxx low power device features and
peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend/abbreviation for Table 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Medium density value line STM8L05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 56
Total current consumption in Run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Total current consumption and timing in Low power run mode at VDD = 1.8 V to
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 63
Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V. . . . . . 64
Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal. . 65
Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 65
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 77
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
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List of tables
STM8L052C6
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
ADC1 accuracy with VDDA = VREF = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
+
R
max for f
= 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
AIN
ADC
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LQFP48 48-pin low profile quad flat package, mechanical data. . . . . . . . . . . . . . . . . . . . . 98
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Medium density value line STM8L05xxx device block diagram . . . . . . . . . . . . . . . . . . . . 12
Medium density value line STM8L05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . 17
STM8L052C6 48-pin LQFP48 package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10. Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 11. Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 12. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 13. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 14. Typical HSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DD
Figure 15. Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 16. Typical VIL and VIH vs VDD (high sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 17. Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 18. Typical pull-up resistance R vs V with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PU
DD
Figure 19. Typical pull-up current I vs V with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
pu
DD
Figure 20. Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 21. Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 22. Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 23. Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 24. Typ. VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 25. Typ. VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 26. Typical NRST pull-up resistance R vs V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PU
DD
Figure 27. Typical NRST pull-up current I vs V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
pu
DD
Figure 28. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 29. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
(1)
Figure 30. SPI1 timing diagram - slave mode and CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
(1)
Figure 31. SPI1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 32. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 33. ADC1 accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 34. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 35. Maximum dynamic current consumption on V
supply pin during ADC
REF+
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 36. Power supply and reference decoupling (V not connected to V ). . . . . . . . . . . . . . 93
REF+
DDA
Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . 93
Figure 38. LQFP48 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 39. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 40. Medium density value line STM8L05xxx ordering information scheme . . . . . . . . . . . . . . 100
Doc ID 023331 Rev 1
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Introduction
STM8L052C6
1
Introduction
This document describes the features, pinout, mechanical data and ordering information of
the medium density value line STM8L052C6 microcontroller with 32-Kbyte Flash memory
density. For further details on the whole STMicroelectronics medium density family please
refer to Section 2.2: Ultra low power continuum.
For detailed information on device operation and registers, refer to the reference manual
(RM0031).
For information on to the Flash program memory and data EEPROM, refer to the
programming manual (PM0054).
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).
Medium density value line devices provide the following benefits:
●
Integrated system
–
–
–
–
–
32 Kbytes of medium density embedded Flash program memory
256 bytes of data EEPROM
2 Kbytes of RAM
Internal high speed and low-power low speed RC
Embedded reset
●
Ultra low power consumption
–
–
–
–
195 µA/MHZ + 440 µA (consumption)
0.9 µA with LSI in Active-halt mode
Clock gated system and optimized power management
Capability to execute from RAM for Low power wait mode and low power run mode
●
●
Advanced features
–
–
Up to 16 MIPS at 16 MHz CPU clock frequency
Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access
Short development cycles
–
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals
–
Wide choice of development tools
Refer to Table 1: Medium density value line STM8L05xxx low power device features and
peripheral counts and Section 3: Functional overview for an overview of the complete range
of peripherals proposed in this family.
Figure 1 shows the block diagram of the medium density value line STM8L05xxx family.
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STM8L052C6
Description
2
Description
The medium density value line STM8L05xxx devices are members of the STM8L ultra low
power 8-bit family.
The value line STM8L05xxx ultra low power family features the enhanced STM8 CPU core
providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive In-application debugging and ultra-fast Flash programming.
Medium density value line STM8L05xxx microcontrollers feature embedded data EEPROM
and low-power, low-voltage, single-supply program Flash memory.
All devices offer 12-bit ADC, real-time clock, 16-bit timers, one 8-bit timer as well as
standard communication interface such as SPI, I2C, USART and 4x28-segment LCD. The
4x 28-segment LCD is available on the medium density value line STM8L05xxx.
The STM8L05xxx family operates from 1.8 V to 3.6 V and is available in the -40 to +85 °C
temperature range.
The modular design of the peripheral set allows the same peripherals to be found in different
ST microcontroller families including 32-bit families. This makes any transition to a different
family very easy, and simplified even more by the use of a common set of development
tools.
All value line STM8L ultra low power products are based on the same architecture with the
same memory mapping and a coherent pinout.
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Description
STM8L052C6
2.1
Device overview
Table 1.
Medium density value line STM8L05xxx low power device features and
peripheral counts
Features
STM8L052C6
Flash (Kbytes)
Data EEPROM (bytes)
RAM (Kbytes)
LCD
32
256
2
4x28
1
Basic
(8-bit)
2
Timers
General purpose
(16-bit)
1
Advanced control
(16-bit)
SPI
1
1
Communication
interfaces
I2C
USART
1
GPIOs
41(1)
12-bit synchronized ADC
(number of channels)
1
(25)
RTC, window watchdog, independent watchdog,
Others
16-MHz and 38-kHz internal RC,
1- to 16-MHz and 32-kHz external oscillator
CPU frequency
Operating voltage
Operating temperature
Package
16 MHz
1.8 V to 3.6 V
-40 to +85 °C
LQFP48
1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the
NRST/PA1 pin as general purpose output only (PA1).
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STM8L052C6
Description
2.2
Ultra low power continuum
The ultra low power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software
and feature compatible. Besides the full compatibility within the STM8L family, the devices
are part of STMicroelectronics microcontrollers ultra low power strategy which also includes
STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of
performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.
Note:
1
2
The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices.
The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15x documentation for more information on these devices.
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra low power performance to range from 5 up to 33.3 DMIPs.
Shared peripherals
STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very
easy migration from one family to another:
●
Analog peripheral: ADC1
●
Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L and STM32L devices use a
common architecture:
●
Same power supply range from 1.8 to 3.6 V
●
Architecture optimized to reach ultra-low consumption both in low power modes and
Run mode
●
●
●
Fast startup strategy from low power modes
Flexible system clock
Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on
reset, power-down reset, brownout reset and programmable voltage detector
Features
ST ultra low power continuum also lies in feature compatibility:
●
More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
Memory density ranging from 4 to 128 Kbytes
●
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Functional overview
STM8L052C6
3
Functional overview
Figure 1.
Medium density value line STM8L05xxx device block diagram
OSC_IN,
OSC_OUT
@VDD
1-16 MHz oscillator
16 MHz internal RC
32 kHz oscillator
VDD18
Clocks
to core and
peripherals
Power
V
V
=1.8 V
to 3.6 V
DD1
SS1
Clock
controller
and
VOLT. REG.
OSC32_IN,
OSC32_OUT
CSS
38 kHz internal RC
Interrupt controller
STM8 Core
NRST
RESET
POR/PDR
BOR
Debug module
(SWIM)
SWIM
PVD
PVD_IN
2 channels
16-bit Timer 2
2 channels
3 channels
16-bit Timer 3
16-bit Timer 1
8-bit Timer 4
32 Kbytes
program memory
256 bytes
data EEPROM
IR_TIM
Infrared interface
2 Kbytes RAM
DMA1
(4 channels)
PA[7:0]
PB[7:0]
Port A
Port B
Port C
Port D
Port E
SCL, SDA,
SMB
I²C1
SPI1
MOSI, MISO,
SCK, NSS
PC[7:0]
PD[7:0]
PE[7:0]
RX, TX, CK
USART1
V
DDA
@VDDA/V
V
SSA
SSA
ADC1_INx
PF0
Port F
12-bit ADC1
V
V
REF+
REF-
BEEP
Beeper
RTC
ALARM, CALIB
Internal reference
voltage
VREFINT out
IWDG
(38 kHz clock)
WWDG
V
= 2.5 V
3.6 V
to
LCD
LCD booster
LCD driver
4x28
SEGx, COMx
1. Legend:
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
I²C: Inter-integrated circuit multimaster interface
LCD: Liquid crystal display
POR/PDR: Power on reset / power down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
IWDG: independent watchdog
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STM8L052C6
Functional overview
3.1
Low power modes
The medium density value line STM8L05xxx devices support five low power modes to
achieve the best compromise between low power consumption, short startup time and
available wakeup sources:
●
●
Wait mode: The CPU clock is stopped, but selected peripherals keep running. An
internal or external interrupt, event or a Reset can be used to exit the microcontroller
from Wait mode (WFE or WFI mode).
Low power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra low power mode.
The microcontroller enters Low power run mode by software and can exit from this
mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
●
Low power wait mode: This mode is entered when executing a Wait for event in Low
power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the
system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
●
●
Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
can be triggered by RTC interrupts, external interrupts or reset.
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.
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Functional overview
STM8L052C6
3.2
Central processing unit STM8
3.2.1
Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
●
●
●
●
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
●
●
●
●
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64-Kbyte level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
●
●
20 addressing modes
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
●
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
●
●
●
●
●
●
●
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
3.2.2
Interrupt controller
The medium density value line STM8L05xxx devices feature a nested vectored interrupt
controller:
●
●
●
●
Nested interrupts with 3 software priority levels
32 interrupt vectors with hardware priority
Up to 40 external interrupt sources on 11 vectors
Trap and reset interrupts
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STM8L052C6
Functional overview
3.3
Reset and supply management
3.3.1
Power supply scheme
The device requires a 1.8 V to 3.6 V operating supply voltage (V ). The external power
DD
supply pins must be connected as follows:
●
●
●
●
V
; V
= 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator.
DD1
SS1
Provided externally through V
pins, the corresponding ground pin is V
.
DD1
SS1
V
V
V
= 1.8 to 3.6 V: external power supplies for analog peripherals. V
and
SSA ; DDA
DDA
must be connected to V
and V
, respectively.
SSA
DD1
SS1
V
; V
= 1.8 to 3.6 V: external power supplies for I/Os. V
and V
must be
SS2
DD2
DD2
SS2
connected to V
and V
, respectively.
DD1
SS1
V
; V
(for ADC1): external reference voltage for ADC1. Must be provided
REF-
REF+
externally through V
and V
pin.
REF+
REF-
3.3.2
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry . At power-on, BOR is always active,
and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached,
the option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains
under reset when V is below a specified threshold, V
or V
, without the need
DD
POR/PDR
BOR
for any external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
/V power supply and compares it to the V threshold. This PVD offers 7 different
V
DD DDA
PVD
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V /V drops below the V threshold and/or when
DD DDA
PVD
V
/V
is higher than the V
threshold. The interrupt service routine can then generate
DD DDA
PVD
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3
Voltage regulator
The medium density value line STM8L05xxx embeds an internal voltage regulator for
generating the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
●
●
Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes
Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low
power wait modes
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
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Functional overview
STM8L052C6
3.4
Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
●
Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
●
●
●
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock sources: 4 different clock sources can be used to drive the system
clock:
–
–
–
–
1-16 MHz High speed external crystal (HSE)
16 MHz High speed internal RC oscillator (HSI)
32.768 kHz Low speed external crystal (LSE)
38 kHz Low speed internal RC (LSI)
●
●
RTC and LCD clock sources: The above four sources can be chosen to clock the
RTC and the LCD, whatever the system clock.
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
●
●
Clock security system (CSS): This feature can be enabled by software. If a HSE clock
failure occurs, the system clock is automatically switched to HSI.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
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STM8L052C6
Figure 2.
Functional overview
Medium density value line STM8L05xxx clock tree diagram
CSS
HSE (1)
HSI
OSC_IN
HSE OSC
1-16 MHz
to core and
memory
SYSCLK
OSC_OUT
SYSCLK
Prescaler
/1;2;4;8;16;32;64;128
HSI RC
16 MHz
LSI
PCLK
LSE (2)
to peripherals
Peripheral
Clock enable (15 bits)
LSE (2)
BEEPCLK
IWDGCLK
to BEEP
to IWDG
CLKBEEPSEL[1:0]
LSI
LSI RC
38 kHz
RTCCLK
to RTC
to LCD
RTCSEL[3:0]
LCD peripheral
clock enable (1 bit)
RTC
RTCCLK/2
RTCCLK
prescaler
/ 2
OSC32_IN
/1;2;4;8;16;32;64
LSE OSC
.
32 768 kH
z
OSC32_OUT
Halt
LCDCLK
to LCD
SYSCLK
HSI
configurable
CCO
LCD peripheral
clock enable (1 bit)
clock output
LSI
CCO
prescaler
HSE (1)
/1;2;4;8;16;32;64
LSE (2)
1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE
bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031).
2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE
bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031).
3.5
Low power real-time clock
The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.
Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,
year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31
day months are made automatically.
It provides a programmable alarm and programmable periodic interrupts with wakeup from
Halt capability.
●
●
Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is
from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach
36 hours.
Periodic alarms based on the calendar can also be generated from every second to
every year.
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Functional overview
STM8L052C6
3.6
LCD (Liquid crystal display)
The LCD is only available on STM8L052xx devices.
●
The liquid crystal display drives up to 4 common terminals and up to 28 segment
terminals to drive up to 112 pixels. Internal step-up converter to guarantee contrast
control whatever V
.
DD
●
●
●
●
●
Static 1/2, 1/3, 1/4 duty supported.
Static 1/2, 1/3, bias supported.
Phase inversion to reduce power consumption and EMI.
Up to 4 pixels which can be programmed to blink.
The LCD controller can operate in Halt mode.
Note:
Unnecessary segments and common pins can be used as general I/O pins.
3.7
Memories
The medium density value line STM8L05xxx devices have the following main features:
●
2 Kbytes of RAM
●
The non-volatile memory is divided into three arrays:
–
–
–
32 Kbytes of medium density embedded Flash program memory
256 bytes of data EEPROM
Option bytes
The EEPROM embeds the error correction code (ECC) feature. It supports the read-while-
write (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.
The option byte protects part of the Flash program memory from write and readout piracy.
3.8
DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, I2C1, SPI1, USART1and the four timers.
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STM8L052C6
Functional overview
3.9
Analog-to-digital converter
●
12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel)
and internal reference voltage
●
●
●
●
●
●
●
Conversion time down to 1 µs with f
= 16 MHz
SYSCLK
Programmable resolution
Programmable sampling time
Single and continuous mode of conversion
Scan capability: automatic conversion performed on a selected group of analog inputs
Analog watchdog
Triggered by timer
Note:
ADC1 can be served by DMA1.
3.10
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.
The highly flexible routing interface allows application software to control the routing of
different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog
signals to ADC1 and the internal reference voltage V
.
REFINT
3.11
Timers
The medium density value line STM8L05xxx devices contain one advanced control timer
(TIM1), two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer
(TIM4).
All the timers can be served by DMA1.
Table 2 compares the features of the advanced control, general-purpose and basic timers.
Table 2.
Timer
Timer feature comparison
DMA1
Counter Counter
Capture/compare Complementary
Prescaler factor
request
resolution
type
channels
outputs
generation
Any integer
from 1 to 65536
TIM1
3 + 1
3
16-bit
8-bit
up/down
up
TIM2
TIM3
Any power of 2
from 1 to 128
Yes
2
0
None
Any power of 2
from 1 to 32768
TIM4
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Functional overview
STM8L052C6
3.11.1
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
●
16-bit up, down and up/down autoreload counter with 16-bit prescaler
●
3 independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse
mode output
●
●
●
●
●
●
1 additional capture/compare channel which is not connected to an external I/O
Synchronization module to control the timer with external signals
Break input to force timer outputs into a defined state
3 complementary outputs with adjustable dead time
Encoder mode
Interrupt capability on various events (capture, compare, overflow, break, trigger)
3.11.2
16-bit general purpose timers
●
●
●
●
●
●
16-bit autoreload (AR) up/down-counter
7-bit prescaler adjustable to fixed power of 2 ratios (1…128)
2 individually configurable capture/compare channels
PWM mode
Interrupt capability on various events (capture, compare, overflow, break, trigger)
Synchronization with other timers or external signals (external clock, reset, trigger and
enable)
3.11.3
8-bit basic timer
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer overflow.
3.12
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
3.12.1
Window watchdog timer
The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
3.12.2
Independent watchdog timer
The independent watchdog peripheral (IWDG) can be used to resolve processor
malfunctions due to hardware or software failures.
It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.
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STM8L052C6
Functional overview
3.13
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
3.14
Communication interfaces
3.14.1
SPI
The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial
communication with external devices.
●
●
●
●
●
●
Maximum speed: 8 Mbit/s (f
/2) both for master and slave
SYSCLK
Full duplex synchronous transfers
Simplex synchronous transfers on 2 lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
Hardware CRC calculation
Slave/master selection input pin
Note:
SPI1 can be served by the DMA1 Controller.
3.14.2
I²C
2
2
The I C bus interface (I C1) provides multi-master capability, and controls all I²C bus-
specific sequencing, protocol, arbitration and timing.
●
●
●
●
●
2
Master, slave and multi-master capability
Standard mode up to 100 kHz and fast speed modes up to 400 kHz
7-bit and 10-bit addressing modes
SMBus 2.0 and PMBus support
Hardware CRC calculation
Note:
I C1 can be served by the DMA1 Controller.
3.14.3
USART
The USART interface (USART1) allows full duplex, asynchronous communications with
external devices requiring an industry standard NRZ asynchronous serial data format. It
offers a very wide range of baud rates.
●
●
●
●
●
●
1 Mbit/s full duplex SCI
SPI1 emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
Single wire half duplex mode
Note:
USART1 can be served by the DMA1 Controller.
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Functional overview
STM8L052C6
3.15
Infrared (IR) interface
The medium density value line STM8L05xxx devices contain an infrared interface which can
be used with an IR LED for remote control functions. Two timer output compare channels
are used to generate the infrared remote control signals.
3.16
Development support
Development tools
Development tools for the STM8 microcontrollers include:
●
The STice emulation system offering tracing and code profiling
●
The STVD high-level language debugger including C compiler, assembler and
integrated development environment
●
The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
Single wire data interface (SWIM) and debug module
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, CPU operation can also be monitored in real-
time by means of shadow registers.
Bootloader
A bootloader is available to reprogram the Flash memory using the USART1 interface. The
reference document for the bootloader is UM0560: STM8 bootloader user manual.
The bootloader is used to download application software into the device memories,
including RAM, program and data memory, using standard serial interfaces. It is a
complementary solution to programming via the SWIM debugging interface.
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STM8L052C6
Pin description
4
Pin description
Figure 3.
STM8L052C6 48-pin LQFP48 package pinout (with LCD)
48 47 46 45 44 43 42 41 40 39 38 37
36
1
PD7
PD6
PA0
NRST/PA1
PA2
2
35
3
34 PD5
33
4
PA3
PD4
32
5
PA4
PF0
31
6
PB7
PA5
30
7
PB6
PA6
29
8
PB5
PA7
28
V
SS1/VSSA/VREF-
9
PB4
27
10
VDD1
PB3
26
VDDA
11
12
PB2
25
VREF+
PB1
24
13 14 15 16 17 18 19 20 21 22 23
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Pin description
Table 3.
STM8L052C6
Legend/abbreviation for Table 4
Type
I= input, O = output, S = power supply
FT
Five-volt tolerant
Level
TT
3.6 V tolerant
Output
Input
Output
HS = high sink/source (20 mA)
float = floating, wpu = weak pull-up
T = true open drain, OD = open drain, PP = push pull
Port and control
configuration
Bold X (pin state after reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).
Table 4.
Medium density value line STM8L05xxx pin description
Pin
number
Input
Output
Pin name
Default alternate function
2
3
NRST/PA1(1)
I/O
I/O
X
X
HS
X Reset PA1
PA2/OSC_IN/
HSE oscillator input /
X Port A2 [USART1 transmit] / [SPI1
master in- slave out]
[USART1_TX](8)
[SPI1_MISO] (8)
/
X
X
X
X
X
X
X
X
X
HS
HS
HS
HS
HS
X
X
X
X
X
HSE oscillator output /
X Port A3 [USART1 receive]/ [SPI1
master out/slave in]/
PA3/OSC_OUT/[USART1_
4
5
6
7
I/O
X
X
X
RX](8)/[SPI1_MOSI](8)
PA4/TIM2_BKIN/
Timer 2 - break input /
X Port A4
I/O TT(2)
I/O TT(2)
LCD COM 0 / ADC1 input 2
LCD_COM0/ADC1_IN2
Timer 3 - break input /
X Port A5 LCD_COM 1 / ADC1 input
PA5/TIM3_BKIN/
LCD_COM1/ADC1_IN1
1
[ADC1 - trigger] /
X Port A6 LCD_COM2 /
ADC1 input 0
PA6/[ADC1_TRIG]/
LCD_COM2/ADC1_IN0
I/O TT(2)
I/O FT
X
X
X
X
8
PA7/LCD_SEG0(3)
X
X
HS
HS
X
X
X Port A7 LCD segment 0
PB0(4)/TIM2_CH1/
LCD_SEG10/ADC1_IN18
Timer 2 - channel 1 / LCD
X Port B0
24
I/O TT(2) X(4) X(4)
segment 10 / ADC1_IN18
PB1/TIM3_CH1/
LCD_SEG11/
ADC1_IN17
Timer 3 - channel 1 / LCD
X Port B1
25
26
I/O TT(2)
I/O TT(2)
X
X
X
X
X
X
HS
HS
X
X
segment 11 / ADC1_IN17
PB2/ TIM2_CH2/
LCD_SEG12/
ADC1_IN16
Timer 2 - channel 2 / LCD
X Port B2
segment 12 / ADC1_IN16
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Doc ID 023331 Rev 1
STM8L052C6
Pin description
Table 4.
Medium density value line STM8L05xxx pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
PB3/TIM2_ETR/
LCD_SEG13/
ADC1_IN15
Timer 2 - external trigger /
X Port B3 LCD segment 13
27
28
29
30
31
I/O TT(2)
X
X
X
X
X
X
X
HS
X
X
X
X
X
/ADC1_IN15
PB4(4)/[SPI1_NSS](8)
LCD_SEG14/
ADC1_IN14
/
[SPI1 master/slave select] /
X Port B4 LCD segment 14 /
I/O TT(2) X(4) X(4)
HS
HS
HS
HS
ADC1_IN14
PB5/[SPI1_SCK](8)
LCD_SEG15/
ADC1_IN13
/
[SPI1 clock] / LCD segment
15 / ADC1_IN13
I/O TT(2)
I/O TT(2)
I/O TT(2)
X
X
X
X
X
X
X Port B5
PB6/[SPI1_MOSI](8)
LCD_SEG16/
ADC1_IN12
/
/
[SPI1 master out/slave in]/
X Port B6 LCD segment 16 /
ADC1_IN12
PB7/[SPI1_MISO](8)
LCD_SEG17/
[SPI1 master in- slave out]
X Port B7 /LCD segment 17 /
ADC1_IN11
ADC1_IN11
37
38
PC0(3)/I2C1_SDA
PC1(3)/I2C1_SCL
I/O FT
I/O FT
X
X
X
X
T(5)
T(5)
Port C0 I2C1 data
Port C1 I2C1 clock
USART1 receive /
PC2/USART1_RX/
LCD_SEG22/ADC1_IN6/
VREFINT
LCD segment 22 /
ADC1_IN6 /Internal voltage
41
42
I/O TT(2)
I/O TT(2)
X
X
X
X
X
X
HS
HS
X
X
X Port C2
reference output
PC3/USART1_TX/
LCD_SEG23/
ADC1_IN5
USART1 transmit /
X Port C3 LCD segment 23 /
ADC1_IN5
USART1 synchronous
clock / I2C1_SMB /
X Port C4 Configurable clock output /
LCD segment 24/
PC4/USART1_CK/
I2C1_SMB/CCO/
LCD_SEG24/
43
44
I/O TT(2)
X
X
X
X
X
X
HS
HS
X
X
ADC1_IN4
ADC1_IN4
PC5/OSC32_IN
LSE oscillator input / [SPI1
X Port C5 master/slave select] /
[USART1 transmit]
/[SPI1_NSS](8)
/
I/O
[USART1_TX](8)
PC6/OSC32_OUT/
LSE oscillator output /
X Port C6 [SPI1 clock] / [USART1
receive]
45
46
[SPI1_SCK](8)
/
I/O
X
X
X
X
X
X
HS
HS
X
X
[USART1_RX](8)
PC7/LCD_SEG25/
ADC1_IN3
LCD segment 25
X Port C7
I/O TT(2)
/ADC1_IN3
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Pin description
STM8L052C6
Table 4.
Medium density value line STM8L05xxx pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
PD0/TIM3_CH2/
[ADC1_TRIG](8)
LCD_SEG7/ADC1_IN22/
Timer 3 - channel 2 /
X Port D0 [ADC1_Trigger] / LCD
segment 7 / ADC1_IN22
20
21
22
23
33
34
/
I/O TT(2)
I/O TT(2)
I/O TT(2)
I/O TT(2)
I/O TT(2)
I/O TT(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS
X
X
X
X
X
X
PD1/TIM3_ETR/
LCD_COM3/
ADC1_IN21
Timer 3 - external trigger /
X Port D1
HS
HS
HS
HS
HS
LCD_COM3 / ADC1_IN21
PD2/TIM1_CH1
/LCD_SEG8/
ADC1_IN20
Timer 1 - channel 1 / LCD
X Port D2
segment 8 / ADC1_IN20
Timer 1 - externaltrigger /
X Port D3 LCD segment 9 /
ADC1_IN19
PD3/ TIM1_ETR/
LCD_SEG9/ADC1_IN19
PD4/TIM1_CH2
/LCD_SEG18/
ADC1_IN10
Timer 1 - channel 2 / LCD
X Port D4
segment 18 / ADC1_IN10
PD5/TIM1_CH3
/LCD_SEG19/
ADC1_IN9
Timer 1 - channel 3 / LCD
X Port D5
segment 19 / ADC1_IN9
PD6/TIM1_BKIN
/LCD_SEG20/
ADC1_IN8/RTC_CALIB/
/VREFINT
Timer 1 - break input / LCD
segment 20 / ADC1_IN8 /
RTC calibration / Internal
voltage reference output
35
36
I/O TT(2)
X
X
X
X
X
X
HS
HS
X
X
X Port D6
Timer 1 - inverted channel
1/ LCD segment 21 /
X Port D7 ADC1_IN7 / RTC alarm /
Internal voltage reference
output
PD7/TIM1_CH1N
/LCD_SEG21/
ADC1_IN7/RTC_ALARM/V
REFINT
I/O TT(2)
14
15
PE0(3)/LCD_SEG1
I/O FT
X
X
X
X
X
X
HS
HS
X
X
X Port E0 LCD segment 1
PE1/TIM1_CH2N/
LCD_SEG2
Timer 1 - inverted channel
X Port E1
I/O TT(2)
2 / LCD segment 2
PE2/TIM1_CH3N/
LCD_SEG3
Timer 1 - inverted channel
X Port E2
16
I/O TT(2)
X
X
X
HS
X
3 / LCD segment 3
17
18
PE3/LCD_SEG4
PE4/LCD_SEG5
I/O TT(2)
I/O TT(2)
X
X
X
X
X
X
HS
HS
X
X
X Port E3 LCD segment 4
X Port E4 LCD segment 5
PE5/LCD_SEG6/
ADC1_IN23
LCD segment 6 /
X Port E5
19
47
I/O TT(2)
I/O TT(2)
X
X
X
X
X
X
HS
HS
X
X
ADC1_IN23
PE6/LCD_SEG26/
PVD_IN
X Port E6 LCD segment 26/PVD_IN
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Doc ID 023331 Rev 1
STM8L052C6
Pin description
Table 4.
Medium density value line STM8L05xxx pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
PE7/LCD_SEG27
PF0/ADC1_IN24
48
32
I/O TT(2)
X
X
X
X
X
X
HS
X
X
X Port E7 LCD segment 27
ADC1_IN24
I/O
S
HS
X Port F0
13
13
10
11
12
VLCD
Reserved
VDD
LCD booster external capacitor
Reserved. Must be tied to VDD
Digital power supply
S
S
S
VDDA
Analog supply voltage
VREF+
ADC1 positive voltage reference
I/O ground / Analog ground voltage /
ADC1 negative voltage reference
9
VSS1/VSSA/VREF-
S
39
40
VDD2
VSS2
S
S
IOs supply voltage
IOs ground voltage
[USART1 synchronous
PA0(6)/[USART1_CK](8)
/
HS
clock](8) / SWIM input and
1
I/O
X
X(6)
X
X
X Port A0
(7)
SWIM/BEEP/IR_TIM (7)
output /Beep output
/ Infrared Timer output
1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1
pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031).
2. In the 3.6 V tolerant I/Os, protection diode to VDD is not implemented.
3. In the 5 V tolerant I/Os, protection diode to VDD is not implemented.
4. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
5. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are
not implemented).
6. The PA0 pin is in input pull-up during the reset phase and after reset release.
7. High Sink LED driver capability available on PA0.
8. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not
aduplication of the function).
Note:
The slope control of all GPIO pins, except true open drain pins, can be programmed. By
default, the slope control is limited to 2 MHz.
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Pin description
STM8L052C6
4.1
System configuration options
As shown in Table 4: Medium density value line STM8L05xxx pin description, some
alternate functions can be remapped on different I/O ports by programming one of the two
remapping registers described in the “ Routing interface (RI) and system configuration
controller” section in the STM8L15x and STM8L16x reference manual (RM0031).
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STM8L052C6
Memory and register map
5
Memory and register map
5.1
Memory mapping
The memory map is shown in Figure 4.
Figure 4.
Memory map
0x00 0000
(2 Kbytes) (1)
RAM
including
(513 bytes) (1)
Stack
0x00 07FF
0x00 0800
Reserved
0x00 0FFF
0x00 1000
Data EEPROM
(256 bytes)
0x00 10FF
0x00 1100
0x00 5000
GPIO Ports
Flash
0x00 5050
0x00 5070
0x00 509E
0x00 50A0
0x00 50A6
0x00 50B0
Reserved
0x00 47FF
0x00 4800
DMA1
SYSCFG
ITC-EXTI
WFE
Option bytes
0x00 48FF
0x00 4900
RST
0x00 50B2
0x00 50C0
0x00 50D3
0x00 50E0
0x00 50F3
0x00 5140
0x00 5200
0x00 5210
0x00 5230
0x00 5250
0x00 5280
0x00 52B0
PWR
CLK
Reserved
WWDG
IWDG
BEEP
RTC
0x00 4FFF
0x00 5000
SPI1
I2C1
GPIO and peripheral registers
Reserved
USART1
TIM2
0x00 57FF
0x00 5800
TIM3
0x00 5FFF
0x00 6000
TIM1
0x00 52E0
0x00 52FF
0x00 5340
0x00 5380
0x00 5400
0x00 5430
0x00 5440
TIM4
Boot ROM
(2 Kbytes)
IRTIM
ADC1
0x00 67FF
0x00 6800
Reserved
LCD
Reserved
0x00 7EFF
0x00 7F00
RI
CPU/SWIM/Debug/ITC
Registers
Reserved
0x00 7FFF
0x00 8000
0x00 807F
0x00 8080
Reset and interrupt vectors
Medium density
Flash program memory
(32 Kbytes)
0x00 FFFF
1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.
2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.
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Memory and register map
STM8L052C6
Table 5.
Flash and RAM boundary addresses
Memory area
Size
Start address
End address
RAM
2 Kbytes
0x00 0000
0x00 8000
0x00 07FF
0x00 FFFF
Flash program memory
32 Kbytes
5.2
Register map
Table 6.
I/O port hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0xXX
0x00
0x01
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PC_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
Port A control register 2
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
Port B
Port C
Port D
Port E
Port B control register 2
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
Port C control register 2
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
Port D control register 2
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
Port E control register 2
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STM8L052C6
Table 6. I/O port hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
0x00
0xXX
0x00
0x00
0x00
Port F
Port F control register 2
Table 7.
General hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 501E to
0x00 5049
Reserved area (44 bytes)
0x00 5050
0x00 5051
FLASH_CR1
FLASH_CR2
Flash control register 1
Flash control register 2
0x00
0x00
Flash program memory unprotection key
register
0x00 5052
0x00 5053
0x00 5054
FLASH _PUKR
FLASH _DUKR
FLASH _IAPSR
0x00
0x00
0x00
Flash
Data EEPROM unprotection key register
Flash in-application programming status
register
0x00 5055 to
0x00 506F
Reserved area (27 bytes)
Doc ID 023331 Rev 1
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Memory and register map
Table 7. General hardware register map (continued)
Address
STM8L052C6
Reset
status
Block
Register label
Register name
DMA1 global configuration & status
register
0x00 5070
0x00 5071
DMA1_GCSR
DMA1_GIR1
0xFC
0x00
DMA1 global interrupt register 1
Reserved area (3 bytes)
0x00 5072 to
0x00 5074
0x00 5075
0x00 5076
DMA1_C0CR
DMA1 channel 0 configuration register
DMA1 channel 0 status & priority register
0x00
0x00
DMA1_C0SPR
DMA1 number of data to transfer register
(channel 0)
0x00 5077
0x00 5078
DMA1_C0NDTR
DMA1_C0PARH
DMA1_C0PARL
0x00
0x52
0x00
DMA1 peripheral address high register
(channel 0)
DMA1 peripheral address low register
(channel 0)
0x00 5079
0x00 507A
0x00 507B
Reserved area (1 byte)
DMA1
DMA1 memory 0 address high register
(channel 0)
DMA1_C0M0ARH
DMA1_C0M0ARL
0x00
0x00
DMA1 memory 0 address low register
(channel 0)
0x00 507C
0x00 507D
0x00 507E
Reserved area (2 bytes)
0x00 507F
0x00 5080
DMA1_C1CR
DMA1 channel 1 configuration register
DMA1 channel 1 status & priority register
0x00
0x00
DMA1_C1SPR
DMA1 number of data to transfer register
(channel 1)
0x00 5081
0x00 5082
0x00 5083
DMA1_C1NDTR
DMA1_C1PARH
DMA1_C1PARL
0x00
0x52
0x00
DMA1 peripheral address high register
(channel 1)
DMA1 peripheral address low register
(channel 1)
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Doc ID 023331 Rev 1
STM8L052C6
Table 7. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5084
0x00 5085
Reserved area (1 byte)
DMA1 memory 0 address high register
(channel 1)
DMA1_C1M0ARH
DMA1_C1M0ARL
0x00
0x00
DMA1 memory 0 address low register
(channel 1)
0x00 5086
0x00 5087
0x00 5088
Reserved area (2 bytes)
0x00 5089
0x00 508A
DMA1_C2CR
DMA1 channel 2 configuration register
DMA1 channel 2 status & priority register
0x00
0x00
DMA1_C2SPR
DMA1 number of data to transfer register
(channel 2)
0x00 508B
0x00 508C
DMA1_C2NDTR
DMA1_C2PARH
DMA1_C2PARL
0x00
0x52
0x00
DMA1 peripheral address high register
(channel 2)
DMA1 peripheral address low register
(channel 2)
0x00 508D
0x00 508E
0x00 508F
Reserved area (1 byte)
DMA1 memory 0 address high register
(channel 2)
DMA1_C2M0ARH
DMA1_C2M0ARL
0x00
0x00
DMA1
DMA1 memory 0 address low register
(channel 2)
0x00 5090
0x00 5091
0x00 5092
Reserved area (2 bytes)
0x00 5093
0x00 5094
DMA1_C3CR
DMA1 channel 3 configuration register
DMA1 channel 3 status & priority register
0x00
0x00
DMA1_C3SPR
DMA1 number of data to transfer register
(channel 3)
0x00 5095
0x00 5096
DMA1_C3NDTR
0x00
0x40
0x00
DMA1_C3PARH_
C3M1ARH
DMA1 peripheral address high register
(channel 3)
DMA1_C3PARL_
C3M1ARL
DMA1 peripheral address low register
(channel 3)
0x00 5097
0x00 5098
0x00 5099
Reserved area (1 byte)
DMA1 memory 0 address high register
(channel 3)
DMA1_C3M0ARH
DMA1_C3M0ARL
0x00
0x00
DMA1 memory 0 address low register
(channel 3)
0x00 509A
0x00 509B to
0x00 509D
Reserved area (3 bytes)
0x00 509E
0x00 509F
SYSCFG_RMPCR1
SYSCFG_RMPCR2
Remapping register 1
Remapping register 2
0x00
0x00
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Memory and register map
Table 7. General hardware register map (continued)
Address
STM8L052C6
Reset
status
Block
Register label
Register name
0x00 50A0
0x00 50A1
0x00 50A2
0x00 50A3
0x00 50A4
0x00 50A5
0x00 50A6
0x00 50A7
0x00 50A8
EXTI_CR1
EXTI_CR2
EXTI_CR3
EXTI_SR1
EXTI_SR2
EXTI_CONF1
WFE_CR1
WFE_CR2
WFE_CR3
External interrupt control register 1
External interrupt control register 2
External interrupt control register 3
External interrupt status register 1
External interrupt status register 2
External interrupt port select register 1
WFE control register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ITC - EXTI
WFE control register 2
WFE
WFE control register 3
0x00 50AC to
0x00 50AF
Reserved area (4 bytes)
0x00 50B0
0x00 50B1
0x00 50B2
0x00 50B3
RST_CR
RST_SR
Reset control register
Reset status register
0x00
0x01
0x00
0x00
RST
PWR_CSR1
PWR_CSR2
Power control and status register 1
Power control and status register 2
PWR
0x00 50B4 to
0x00 50BF
Reserved area (12 bytes)
0x00 50C0
0x00 50C1
0x00 50C2
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 50CC
0x00 50CD
0x00 50CE
0x00 50CF
CLK_DIVR
CLK_CRTCR
CLK_ICKR
Clock master divider register
Clock RTC register
0x03
0x00
Internal clock control register
Peripheral clock gating register 1
Peripheral clock gating register 2
Configurable clock control register
External clock control register
System clock status register
System clock switch register
Clock switch control register
Clock security system register
Clock BEEP register
0x11
CLK_PCKENR1
CLK_PCKENR2
CLK_CCOR
0x00
0x80
0x00
CLK_ECKR
0x00
CLK_SCSR
0x01
CLK
CLK_SWR
0x01
CLK_SWCR
0bxxxx0000
0x00
CLK_CSSR
CLK_CBEEPR
CLK_HSICALR
CLK_HSITRIMR
CLK_HSIUNLCKR
CLK_REGCSR
0x00
HSI calibration register
0xxx
HSI clock calibration trimming register
HSI unlock register
0x00
0x00
Main regulator control status register
0bxx11100x
0x00 50D0 to
0x00 50D2
Reserved area (3 bytes)
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Doc ID 023331 Rev 1
STM8L052C6
Table 7. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 50D3
0x00 50D4
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
0x00 50D5 to
00 50DF
Reserved area (11 bytes)
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
IWDG prescaler register
IWDG reload register
0xXX
0x00
0xFF
IWDG
BEEP
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
BEEP_CSR1
BEEP_CSR2
BEEP control/status register 1
Reserved area (2 bytes)
0x00
0x1F
0x00 50F1
0x00 50F2
0x00 50F3
BEEP control/status register 2
0x00 50F4 to
0x00 513F
Reserved area (76 bytes)
Doc ID 023331 Rev 1
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Memory and register map
Table 7. General hardware register map (continued)
Address
STM8L052C6
Reset
status
Block
Register label
Register name
0x00 5140
0x00 5141
0x00 5142
0x00 5143
0x00 5144
0x00 5145
0x00 5146
0x00 5147
0x00 5148
0x00 5149
0x00 514A
0x00 514B
0x00 514C
0x00 514D
RTC_TR1
RTC_TR2
RTC_TR3
Time register 1
Time register 2
0x00
0x00
0x00
Time register 3
Reserved area (1 byte)
Date register 1
RTC_DR1
RTC_DR2
RTC_DR3
0x01
0x21
0x00
Date register 2
Date register 3
Reserved area (1 byte)
Control register 1
RTC_CR1
RTC_CR2
RTC_CR3
0x00
0x00
0x00
Control register 2
Control register 3
Reserved area (1 byte)
Initialization and status register 1
Initialization and Status register 2
RTC_ISR1
RTC_ISR2
0x00
0x00
0x00 514E
0x00 514F
Reserved area (2 bytes)
0x00 5150
0x00 5151
0x00 5152
0x00 5153
0x00 5154
0x00 5155
RTC_SPRERH(1)
RTC_SPRERL(1)
RTC_APRER(1)
Synchronous prescaler register high
Synchronous prescaler register low
Asynchronous prescaler register
Reserved area (1 byte)
0x00(1)
0xFF(1)
0x7F(1)
RTC
RTC_WUTRH(1)
RTC_WUTRL(1)
Wakeup timer register high
0xFF(1)
0xFF(1)
Wakeup timer register low
0x00 5156 to
0x00 5158
Reserved area (3 bytes)
Write protection register
Reserved area (2 bytes)
0x00 5159
RTC_WPR
0x00
0x00 515A
0x00 515B
0x00 515C
0x00 515D
0x00 515E
0x00 515F
RTC_ALRMAR1
RTC_ALRMAR2
RTC_ALRMAR3
RTC_ALRMAR4
Alarm A register 1
Alarm A register 2
Alarm A register 3
Alarm A register 4
0x00
0x00
0x00
0x00
0x00 5160 to
0x00 51FF
Reserved area (160 bytes)
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Doc ID 023331 Rev 1
STM8L052C6
Table 7. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
SPI1_CR1
SPI1_CR2
SPI1 control register 1
SPI1 control register 2
SPI1 interrupt control register
SPI1 status register
0x00
0x00
0x00
0x02
0x00
0x07
0x00
0x00
SPI1_ICR
SPI1_SR
SPI1
SPI1_DR
SPI1 data register
SPI1_CRCPR
SPI1_RXCRCR
SPI1_TXCRCR
SPI1 CRC polynomial register
SPI1 Rx CRC register
SPI1 Tx CRC register
0x00 5208 to
0x00 520F
Reserved area (8 bytes)
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
0x00 521E
I2C1_CR1
I2C1_CR2
I2C1 control register 1
I2C1 control register 2
0x00
0x00
0x00
0x00
0x00
I2C1_FREQR
I2C1_OARL
I2C1_OARH
I2C1 frequency register
I2C1 own address register low
I2C1 own address register high
Reserved (1 byte)
I2C1_DR
I2C1_SR1
I2C1 data register
0x00
0x00
0x00
0x0x
0x00
0x00
0x00
0x02
0x00
I2C1 status register 1
I2C1
I2C1_SR2
I2C1 status register 2
I2C1_SR3
I2C1 status register 3
I2C1_ITR
I2C1 interrupt control register
I2C1 clock control register low
I2C1 clock control register high
I2C1 TRISE register
I2C1_CCRL
I2C1_CCRH
I2C1_TRISER
I2C1_PECR
I2C1 packet error checking register
0x00 521F to
0x00 522F
Reserved area (17 bytes)
Doc ID 023331 Rev 1
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Memory and register map
Table 7. General hardware register map (continued)
Address
STM8L052C6
Reset
status
Block
Register label
Register name
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
USART1_SR
USART1_DR
USART1 status register
USART1 data register
0xC0
undefined
0x00
USART1_BRR1
USART1_BRR2
USART1_CR1
USART1_CR2
USART1_CR3
USART1_CR4
USART1_CR5
USART1_GTR
USART1_PSCR
USART1 baud rate register 1
USART1 baud rate register 2
USART1 control register 1
USART1 control register 2
USART1 control register 3
USART1 control register 4
USART1 control register 5
USART1 guard time register
USART1 prescaler register
0x00
0x00
USART1
0x00
0x00
0x00
0x00
0x00
0x00
0x00 523B to
0x00 524F
Reserved area (21 bytes)
38/102
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STM8L052C6
Table 7. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
TIM2_CR1
TIM2_CR2
TIM2 control register 1
TIM2 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM2_SMCR
TIM2_ETR
TIM2 Slave mode control register
TIM2 external trigger register
TIM2 DMA1 request enable register
TIM2 interrupt enable register
TIM2 status register 1
TIM2_DER
TIM2_IER
TIM2_SR1
TIM2_SR2
TIM2 status register 2
TIM2_EGR
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare enable register 1
TIM2 counter high
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCER1
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_BKR
TIM2
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare register 2 high
TIM2 capture/compare register 2 low
TIM2 break register
TIM2_OISR
TIM2 output idle state register
0x00 5267 to
0x00 527F
Reserved area (25 bytes)
Doc ID 023331 Rev 1
39/102
Memory and register map
Table 7. General hardware register map (continued)
Address
STM8L052C6
Reset
status
Block
Register label
Register name
0x00 5280
0x00 5281
0x00 5282
0x00 5283
0x00 5284
0x00 5285
0x00 5286
0x00 5287
0x00 5288
0x00 5289
0x00 528A
0x00 528B
0x00 528C
0x00 528D
0x00 528E
0x00 528F
0x00 5290
0x00 5291
0x00 5292
0x00 5293
0x00 5294
0x00 5295
0x00 5296
TIM3_CR1
TIM3_CR2
TIM3 control register 1
TIM3 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM3_SMCR
TIM3_ETR
TIM3 Slave mode control register
TIM3 external trigger register
TIM3 DMA1 request enable register
TIM3 interrupt enable register
TIM3 status register 1
TIM3_DER
TIM3_IER
TIM3_SR1
TIM3_SR2
TIM3 status register 2
TIM3_EGR
TIM3 event generation register
TIM3 Capture/Compare mode register 1
TIM3 Capture/Compare mode register 2
TIM3 Capture/Compare enable register 1
TIM3 counter high
TIM3_CCMR1
TIM3_CCMR2
TIM3_CCER1
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM3_BKR
TIM3
TIM3 counter low
TIM3 prescaler register
TIM3 Auto-reload register high
TIM3 Auto-reload register low
TIM3 Capture/Compare register 1 high
TIM3 Capture/Compare register 1 low
TIM3 Capture/Compare register 2 high
TIM3 Capture/Compare register 2 low
TIM3 break register
TIM3_OISR
TIM3 output idle state register
0x00 5297 to
0x00 52AF
Reserved area (25 bytes)
40/102
Doc ID 023331 Rev 1
STM8L052C6
Table 7. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 52B0
0x00 52B1
0x00 52B2
0x00 52B3
0x00 52B4
0x00 52B5
0x00 52B6
0x00 52B7
0x00 52B8
0x00 52B9
0x00 52BA
0x00 52BB
0x00 52BC
0x00 52BD
0x00 52BE
0x00 52BF
0x00 52C0
0x00 52C1
0x00 52C2
0x00 52C3
0x00 52C4
0x00 52C5
0x00 52C6
0x00 52C7
0x00 52C8
0x00 52C9
0x00 52CA
0x00 52CB
0x00 52CC
0x00 52CD
0x00 52CE
0x00 52CF
0x00 52D0
0x00 52D1
TIM1_CR1
TIM1_CR2
TIM1 control register 1
TIM1 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1_SMCR
TIM1_ETR
TIM1 Slave mode control register
TIM1 external trigger register
TIM1 DMA1 request enable register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1_DER
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1 status register 2
TIM1_EGR
TIM1 event generation register
TIM1 Capture/Compare mode register 1
TIM1 Capture/Compare mode register 2
TIM1 Capture/Compare mode register 3
TIM1 Capture/Compare mode register 4
TIM1 Capture/Compare enable register 1
TIM1 Capture/Compare enable register 2
TIM1 counter high
TIM1_CCMR1
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1 counter low
TIM1
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 Auto-reload register high
TIM1 Auto-reload register low
TIM1 Repetition counter register
TIM1 Capture/Compare register 1 high
TIM1 Capture/Compare register 1 low
TIM1 Capture/Compare register 2 high
TIM1 Capture/Compare register 2 low
TIM1 Capture/Compare register 3 high
TIM1 Capture/Compare register 3 low
TIM1 Capture/Compare register 4 high
TIM1 Capture/Compare register 4 low
TIM1 break register
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1_DTR
TIM1 dead-time register
TIM1_OISR
TIM1_DCR1
TIM1 output idle state register
DMA1 control register 1
Doc ID 023331 Rev 1
41/102
Memory and register map
Table 7. General hardware register map (continued)
Address
STM8L052C6
Reset
status
Block
Register label
Register name
0x00 52D2
0x00 52D3
TIM1_DCR2
TIM1 DMA1 control register 2
0x00
0x00
TIM1
TIM1_DMA1R
TIM1 DMA1 address for burst mode
0x00 52D4 to
0x00 52DF
Reserved area (12 bytes)
0x00 52E0
0x00 52E1
0x00 52E2
0x00 52E3
0x00 52E4
0x00 52E5
0x00 52E6
0x00 52E7
0x00 52E8
0x00 52E9
TIM4_CR1
TIM4_CR2
TIM4_SMCR
TIM4_DER
TIM4_IER
TIM4 control register 1
TIM4 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM4 Slave mode control register
TIM4 DMA1 request enable register
TIM4 Interrupt enable register
TIM4 status register 1
TIM4
TIM4_SR1
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 Event generation register
TIM4 counter
TIM4 prescaler register
TIM4 Auto-reload register
0x00 52EA to
0x00 52FE
Reserved area (21 bytes)
Infrared control register
Reserved area (64 bytes)
0x00 52FF
IRTIM
IR_CR
0x00
0x00 5300 to
0x00 533F
42/102
Doc ID 023331 Rev 1
STM8L052C6
Table 7. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347
0x00 5348
0x00 5349
0x00 534A
0x00 534B
0x00 534C
0x00 534D
0x00 534E
0x00 534F
0x00 5350
0x00 5351
ADC1_CR1
ADC1_CR2
ADC1 configuration register 1
ADC1 configuration register 2
ADC1 configuration register 3
ADC1 status register
0x00
0x00
0x1F
0x00
0x00
0x00
0x0F
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADC1_CR3
ADC1_SR
ADC1_DRH
ADC1_DRL
ADC1 data register high
ADC1 data register low
ADC1_HTRH
ADC1_HTRL
ADC1_LTRH
ADC1_LTRL
ADC1_SQR1
ADC1_SQR2
ADC1_SQR3
ADC1_SQR4
ADC1_TRIGR1
ADC1_TRIGR2
ADC1_TRIGR3
ADC1_TRIGR4
ADC1 high threshold register high
ADC1 high threshold register low
ADC1 low threshold register high
ADC1 low threshold register low
ADC1 channel sequence 1 register
ADC1 channel sequence 2 register
ADC1 channel sequence 3 register
ADC1 channel sequence 4 register
ADC1 trigger disable 1
ADC1
ADC1 trigger disable 2
ADC1 trigger disable 3
ADC1 trigger disable 4
0x00 5352 to
0x00 53FF
Reserved area (174 bytes)
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
LCD_CR1
LCD_CR2
LCD_CR3
LCD_FRQ
LCD_PM0
LCD_PM1
LCD_PM2
LCD control register 1
LCD control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
LCD control register 3
LCD frequency selection register
LCD Port mask register 0
LCD Port mask register 1
LCD Port mask register 2
Reserved area
LCD
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Memory and register map
Table 7. General hardware register map (continued)
Address
STM8L052C6
Reset
status
Block
Register label
Register name
0x00 5408 to
0x00 540B
Reserved area (4 bytes)
0x00 540C
0x00 540D
0x00 540E
0x00 540F
0x00 5410
0x00 5411
0x00 5412
0x00 5413
0x00 5414
0x00 5415
0x00 5416
0x00 5417
0x00 5418
0x00 5419
LCD_RAM0
LCD_RAM1
LCD_RAM2
LCD_RAM3
LCD_RAM4
LCD_RAM5
LCD_RAM6
LCD_RAM7
LCD_RAM8
LCD_RAM9
LCD_RAM10
LCD_RAM11
LCD_RAM12
LCD_RAM13
LCD display memory 0
LCD display memory 1
LCD display memory 2
LCD display memory 3
LCD display memory 4
LCD display memory 5
LCD display memory 6
LCD display memory 7
LCD display memory 8
LCD display memory 9
LCD display memory 10
LCD display memory 11
LCD display memory 12
LCD display memory 13
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
LCD
0x00 541A to
0x00 542F
Reserved area (22 bytes)
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STM8L052C6
Table 7. General hardware register map (continued)
Address
Memory and register map
Reset
Block
Register label
Register name
status
0x00 5430
0x00 5431
0x00 5432
0x00 5433
0x00 5434
0x00 5435
0x00 5436
0x00 5437
0x00 5438
0x00 5439
0x00 543A
0x00 543B
0x00 543C
0x00 543D
0x00 543E
0x00 543F
Reserved area (1 byte)
Timer input capture routing register 1
Timer input capture routing register 2
I/O input register 1
0x00
0x00
RI_ICR1
RI_ICR2
0x00
RI_IOIR1
undefined
undefined
undefined
0x00
RI_IOIR2
I/O input register 2
RI_IOIR3
I/O input register 3
RI_IOCMR1
RI_IOCMR2
RI_IOCMR3
RI_IOSR1
RI_IOSR2
RI_IOSR3
RI_IOGCR
RI_ASCR1
RI_ASCR2
RI_RCR
I/O control mode register 1
I/O control mode register 2
I/O control mode register 3
I/O switch register 1
0x00
RI
0x00
0x00
I/O switch register 2
0x00
I/O switch register 3
0x00
I/O group control register
Analog switch register 1
Analog switch register 2
Resistor control register 1
0x3F
0x00
0x00
0x00
0x00 5440 to
0x00 5444
Reserved area (5 bytes)
1. These registers are not impacted by a system reset. They are reset at power-on.
Table 8.
Address
CPU/SWIM/debug module/interrupt controller registers
Reset
Status
Block
Register Label
Register Name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
A
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x28
PCE
PCH
PCL
XH
CPU(1)
XL
YH
YL
SPH
SPL
CCR
Stack pointer low
Condition code register
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Memory and register map
Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)
Address
STM8L052C6
Reset
Status
Block
Register Label
Register Name
0x00 7F0B to
0x00 7F5F
Reserved area (85 bytes)
CPU
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Global configuration register
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Interrupt Software priority register 1
Interrupt Software priority register 2
Interrupt Software priority register 3
Interrupt Software priority register 4
Interrupt Software priority register 5
Interrupt Software priority register 6
Interrupt Software priority register 7
Interrupt Software priority register 8
ITC-SPR
0x00 7F78 to
0x00 7F79
Reserved area (2 bytes)
SWIM control status register
Reserved area (15 bytes)
0x00 7F80
SWIM
SWIM_CSR
0x00
0x00 7F81 to
0x00 7F8F
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM Debug module control register 1
DM Debug module control register 2
DM Debug module control/status register 1
DM Debug module control/status register 2
DM enable function register
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DM
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
0x00 7F9B to
0x00 7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
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STM8L052C6
Interrupt vector mapping
6
Interrupt vector mapping
Table 9.
Interrupt mapping
Wakeup
from
Active-
halt mode
Wakeup
from Wait fromWait
(WFI
mode)
Wakeup
Wakeup
from Halt
mode
IRQ
No.
Source
block
Vector
address
Description
(WFE
mode)(1)
RESET
TRAP
Reset
Software interrupt
Yes
-
Yes
-
Yes
-
Yes
-
0x00 8000
0x00 8004
0x00 8008
0
1
Reserved
FLASH end of programing/
write attempted to
protected page interrupt
FLASH
-
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
0x00 800C
0x00 8010
0x00 8014
DMA1 channels 0/1 half
transaction/transaction
complete interrupt
2
3
DMA1 0/1
DMA1 channels 2/3 half
transaction/transaction
complete interrupt
DMA1 2/3
RTC
RTC alarm A/
wakeup
4
5
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0x00 8018
0x00 801C
EXTI E/F/
PVD(2)
External interrupt port E/F
PVD interrupt
6
EXTIB/G
EXTID/H
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
EXTI5
EXTI6
EXTI7
LCD
External interrupt port B/G
External interrupt port D/H
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
LCD interrupt
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8034
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
7
8
9
10
11
12
13
14
15
16
CLK system clock switch/
CSS interrupt/
TIM 1 break
17
18
CLK/TIM1
ADC1
-
-
Yes
Yes
Yes
Yes
0x00 804C
0x00 8050
ACD1 end of conversion/
analog watchdog/
Yes
Yes
overrun interrupt
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Interrupt vector mapping
STM8L052C6
Table 9.
Interrupt mapping (continued)
Wakeup
from
Active-
halt mode
Wakeup
from Wait fromWait
(WFI
mode)
Wakeup
Wakeup
from Halt
mode
IRQ
No.
Source
block
Vector
address
Description
(WFE
mode)(1)
TIM2 update/overflow/
trigger/break
19
TIM2
-
-
Yes
Yes
0x00 8054
interrupt
TIM2capture/
compare interrupt
20
21
22
TIM2
TIM3
TIM3
-
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
0x00 8058
0x00 805C
0x00 8060
TIM3 update/overflow/
trigger/break interrupt
TIM3 capture/compare
interrupt
Update /overflow/trigger/
COM
23
24
25
TIM1
TIM1
TIM4
-
-
-
-
-
-
-
-
Yes
Yes
Yes
0x00 8064
0x00 8068
0x00 806C
Capture/compare
TIM4 update/overflow/
trigger interrupt
Yes
SPI1 TX buffer empty/
RX buffer not empty/
error/wakeup interrupt
26
27
SPI1
Yes
-
Yes
-
Yes
Yes
Yes
Yes
0x00 8070
0x00 8074
USART1transmit data
register empty/
transmission complete
interrupt
USART1
USART1 received data
ready/overrun error/
idle line detected/parity
error/global error interrupt
28
29
USART1
I2C1
-
-
Yes
Yes
Yes
Yes
0x00 8078
0x00 807C
I2C1 interrupt(3)
Yes
Yes
1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the
interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.
When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
2. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).
3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
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STM8L052C6
Option bytes
7
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.
All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See Table 10 for details on option byte addresses.
The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP and UBC values which can only be taken into account when they are modified in
ICP mode (with the SWIM).
Refer to the STM8Lxx Flash programming manual (PM0054) and STM8 SWIM and Debug
Manual (UM0470) for information on SWIM programming procedures.
Table 10. Option byte addresses
Option
Option bits
3
Factory
default
setting
Addr.
Option name
byte
No.
7
6
5
4
2
1
0
Read-out
protection
(ROP)
0x00 4800
OPT0
OPT1
ROP[7:0]
UBC[7:0]
0xAA
UBC (User
Boot code size)
0x00 4802
0x00 4807
0x00
0x00
Reserved
Independent
watchdog
option
OPT3
[3:0]
WWDG WWDG IWDG IWDG
_HALT _HW _HALT _HW
0x00 4808
Reserved
0x00
Number of
stabilization
0x00 4809 clock cycles for OPT4
HSE and LSE
Reserved
Reserved
LSECNT[1:0]
HSECNT[1:0]
0x00
0x01
oscillators
Brownout reset OPT5
0x00 480A
BOR_
ON
BOR_TH
(BOR)
[3:0]
0x00 480B
0x00 480C
Bootloader
option bytes
(OPTBL)
0x00
0x00
OPTBL
[15:0]
OPTBL[15:0]
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Option bytes
STM8L052C6
Table 11. Option byte description
Option
byte
Option description
No.
ROP[7:0] Memory readout protection (ROP)
0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L05x/15x and STM8L16x reference manual
(RM0031).
OPT0
UBC[7:0] Size of the user boot code area
0x00: no UBC
0x01: the UBC contains only the interrupt vectors.
0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt
vectors.
0x03 - Page 0 to 2 reserved for UBC, memory write-protected
0xFF - Page 0 to 254 reserved for UBC, memory write-protected
Refer to User boot code section in the STM8L05x/15x and STM8L16x reference manual (RM0031).
OPT1
OPT2
Reserved
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent window watchdog off on Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
OPT3
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
HSECNT: Number of HSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
OPT4
LSECNT: Number of LSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
Refer to Table 29: LSE oscillator characteristics on page 69.
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STM8L052C6
Option bytes
Table 11. Option byte description (continued)
Option
Option description
byte
No.
BOR_ON:
0: Brownout reset off
1: Brownout reset on
OPT5
BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 20 for details on the thresholds according to
the value of BOR_TH bits.
OPTBL[15:0]:
This option is checked by the boot ROM code after reset. Depending on
OPTBL content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the
CPU jumps to the bootloader or to the reset vector.
Refer to the UM0560 bootloader user manual for more details.
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Electrical parameters
STM8L052C6
8
Electrical parameters
8.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
8.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
is indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
8.1.2
Typical values
Unless otherwise specified, typical data is based on T = 25 °C, V = 3 V. It is given only as
A
DD
design guidelines and is not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2Σ).
8.1.3
8.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 5.
Figure 5.
Pin loading conditions
STM8L PIN
50 pF
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STM8L052C6
Electrical parameters
8.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 6.
Figure 6. Pin input voltage
STM8L PIN
V
IN
8.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 12. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External supply voltage (including VDDA
VDD- VSS
- 0.3
4.0
V
(1)
and VDD2
)
Input voltage on true open-drain pins
(PC0 and PC1)
VSS - 0.3
VSS - 0.3
VDD + 4.0
VDD + 4.0
Input voltage on five-volt tolerant (FT)
pins (PA7 and PE0)
(2)
VIN
V
Input voltage on 3.6 V tolerant (TT) pins
Input voltage on any other pin
VSS - 0.3
VSS - 0.3
4.0
4.0
see Absolute maximum
ratings (electrical sensitivity)
on page 95
VESD
Electrostatic discharge voltage
1. All power (VDD1, VDD2, VDDA) and ground (VSS1, VSS2, VSSA) pins must always be connected to the
external power supply.
2. VIN maximum must always be respected. Refer to Table 13. for maximum allowed injected current values.
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Electrical parameters
STM8L052C6
Table 13. Current characteristics
Symbol
Ratings
Max.
Unit
IVDD
IVSS
Total current into VDD power line (source)
Total current out of VSS ground line (sink)
80
80
Output current sunk by IR_TIM pin (with high sink LED driver
capability)
80
IIO
Output current sunk by any other I/O and control pin
Output current sourced by any I/Os and control pin
25
- 25
Injected current on true open-drain pins (PC0 and PC1)(1)
Injected current on five-volt tolerant (FT) pins (PA7 and PE0) (1)
Injected current on 3.6 V tolerant (TT) pins (1)
- 5 / +0
- 5 / +0
- 5 / +0
- 5 / +5
25
mA
IINJ(PIN)
Injected current on any other pin (2)
Total injected current (sum of all I/O and control pins) (3)
ΣIINJ(PIN)
1. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 12. for maximum allowed input voltage values.
2. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 12. for maximum allowed input voltage values.
3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 14. Thermal characteristics
Symbol
Ratings
Storage temperature range
Maximum junction temperature
Value
Unit
TSTG
TJ
-65 to +150
150
° C
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STM8L052C6
Electrical parameters
8.3
Operating conditions
Subject to general operating conditions for V and T .
DD
A
8.3.1
General operating conditions
Table 15. General operating conditions
Symbol Parameter
System clock
Conditions
Min.
Max.
Unit
(1)
f
1.8 V ≤ VDD < 3.6 V
0
16
MHz
SYSCLK
frequency
Standard operating
voltage
VDD
1.8
1.8
3.6
3.6
V
V
Analog operating
voltage
Must be at the same
potential as VDD
VDDA
Power dissipation at
TA= 85 °C
(2)
PD
LQFP48
288
85
mW
°C
TA
TJ
Temperature range
1.8 V ≤ VDD < 3.6 V
-40 °C ≤ TA < 85 °C
-40
-40
Junction temperature
range
105(3)
°C
1. fSYSCLK = fCPU
2. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/ΘJA with TJmax in this table and ΘJA in “Thermal
characteristics” table.
3. TJmax is given by the test limit. Above this value, the product behavior is not guaranteed.
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Electrical parameters
STM8L052C6
8.3.2
Embedded reset and power control block characteristics
Table 16. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
0(1)
Max
Unit
Typ
BOR detector
enabled
(1)
VDD rise time rate
∞
tVDD
µs/V
BOR detector
enabled
20(1)
∞
(1)
VDD fall time rate
VDD rising
tTEMP
VPDR
Reset release delay
3
ms
V
Power-down reset threshold Falling edge
1.30(2)
1.67
1.69
1.87
1.96
2.22
2.31
2.45
2.54
2.68
2.78
1.80
1.88
1.98
2.08
2.2
1.50
1.70
1.75
1.93
2.04
2.3
1.65
1.74
1.80
1.97
2.07
2.35
2.44
2.60
2.7
Falling edge
Brown-out reset threshold 0
(BOR_TH[2:0]=000)
VBOR0
VBOR1
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
Rising edge
Falling edge
Brown-out reset threshold 1
(BOR_TH[2:0]=001)
Rising edge
Falling edge
Brown-out reset threshold 2
(BOR_TH[2:0]=010)
V
Rising edge
2.41
2.55
2.66
2.80
2.90
1.84
1.94
2.04
2.14
2.24
2.34
2.44
2.54
2.64
2.74
2.83
2.94
3.05
3.15
Falling edge
Brown-out reset threshold 3
(BOR_TH[2:0]=011)
Rising edge
Falling edge
2.85
2.95
1.88
1.99
2.09
2.18
2.28
2.38
2.48
2.58
2.69
2.79
2.88
2.99
3.09
3.20
Brown-out reset threshold 4
(BOR_TH[2:0]=100)
Rising edge
Falling edge
PVD threshold 0
Rising edge
Falling edge
PVD threshold 1
Rising edge
Falling edge
PVD threshold 2
Rising edge
2.28
2.39
2.47
2.57
2.68
2.77
2.87
2.97
3.08
Falling edge
PVD threshold 3
V
Rising edge
Falling edge
PVD threshold 4
Rising edge
Falling edge
PVD threshold 5
Rising edge
Falling edge
PVD threshold 6
Rising edge
1. Data guaranteed by design, not tested in production.
2. Data based on characterization results, not tested in production.
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STM8L052C6
Figure 7.
Electrical parameters
POR/BOR thresholds
Vdd
Vdd
3.6 V
Operating power supply
Vdd
BOR threshold
1.8 V
BOR Threshold_0
VBOR0
VPDR
without BOR = Battery life extension
PDR Threshold
Internal NRST
with
BOR
with without
BOR BOR
Time
BOR always active
at power up
BOR activated by user for
power down detection
8.3.3
Supply current characteristics
Total current consumption
The MCU is placed under the following conditions:
●
All I/O pins in input mode with a static value at V or V (no load)
DD SS
●
All peripherals are disabled except if explicitly mentioned.
In the following table, data is based on characterization results, unless otherwise specified.
Subject to general operating conditions for V and T .
DD
A
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Electrical parameters
STM8L052C6
Table 17. Total current consumption in Run mode
Max
55 °C
Para
meter
Conditions(1)
Symbol
Typ
Unit
85 °C
0.49
0.58
0.86
1.25
fCPU = 125 kHz
0.39 0.47
0.48 0.56
0.75 0.84
1.10 1.20
f
CPU = 1 MHz
HSI RC osc.
(16 MHz)(3)
fCPU = 4 MHz
f
f
CPU = 8 MHz
CPU = 16 MHz
1.85 1.93 2.12(5)
All
peripherals
OFF,
code
executed
from RAM,
VDD from 1.8
fCPU = 125 kHz
0.05 0.06
0.18 0.19
0.55 0.62
0.99 1.20
0.09
0.20
0.64
1.21
Supply
current
in run
mode(2)
f
f
CPU = 1 MHz
CPU = 4 MHz
IDD(RUN)
HSE external
mA
clock
(4)
(fCPU=fHSE
)
fCPU = 8 MHz
CPU = 16 MHz
V to
3.6 V
1.90 2.22 2.23(5)
f
LSI RC osc.
(typ. 38 kHz)
fCPU = fLSI
0.040 0.045 0.046
LSE external
clock
0.035 0.040 0.048(5)
fCPU = fLSE
(32.768 kHz)
fCPU = 125 kHz
0.43 0.55
0.60 0.77
1.11 1.34
1.90 2.20
0.56
0.80
1.37
2.23
4.75
0.39
0.52
1.40
2.44
4.52
f
CPU = 1 MHz
HSI RC
osc.(6)
fCPU = 4 MHz
fCPU = 8 MHz
f
CPU = 16 MHz
3.8
4.60
All
peripherals
OFF, code
executed
from Flash,
VDD from
fCPU = 125 kHz
0.30 0.36
0.40 0.50
1.15 1.31
2.17 2.33
Supply
current
in Run
mode
f
f
f
CPU = 1 MHz
CPU = 4 MHz
CPU = 8 MHz
IDD(RUN)
mA
HSE external
clock
(4)
(fCPU=fHSE
)
1.8 V to 3.6 V
fCPU = 16 MHz
fCPU = fLSI
4.0
4.46
LSI RC osc.
0.110 0.123 0.130
LSE ext. clock
(32.768
kHz)(7)
fCPU = fLSE
0.100 0.101 0.104
1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc. , fCPU=fSYSCLK
2. CPU executing typical data processing
3. The run from RAM consumption can be approximated with the linear formula:
IDD(run_from_RAM) = Freq * 90 µA/MHz + 380 µA
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Electrical parameters
4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE
consumption
(IDD HSE) must be added. Refer to Table 28.
5. Tested in production.
6. The run from Flash consumption can be approximated with the linear formula:
IDD(run_from_Flash) = Freq * 195 µA/MHz + 440 µA
7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE
consumption
(IDD LSE) must be added. Refer to Table 29.
Figure 8.
Typ. I
vs. V , f
= 16 MHz
DD(RUN)
DD CPU
3.00
2.75
2.50
2.25
2.00
1.75
1.50
-40°C
25°C
85°C
1.8
2.1
2.6
VDD [V]
3.1
3.6
ai18213V2
1. Typical current consumption measured with code executed from RAM
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Electrical parameters
STM8L052C6
In the following table, data is based on characterization results, unless otherwise specified.
Table 18. Total current consumption in Wait mode
Max
Conditions(1)
Symbol Parameter
Typ
Unit
85
°C(2)
55°C
fCPU = 125 kHz
0.33 0.39 0.41
0.35 0.41 0.44
0.42 0.51 0.52
0.52 0.57 0.58
0.68 0.76 0.79
0.032 0.056 0.068
0.078 0.121 0.144
0.218 0.26 0.30
0.40 0.52 0.57
0.760 1.01 1.05
0.035 0.044 0.046
fCPU = 1 MHz
fCPU = 4 MHz
HSI
f
CPU = 8 MHz
CPU = 16 MHz
CPU not
clocked,
f
all peripherals
OFF,
code executed
from RAM
with Flash in
fCPU = 125 kHz
Supply
IDD(Wait) current in
Wait mode
f
CPU = 1 MHz
CPU = 4 MHz
HSE external
mA
clock
f
(4)
(fCPU=fHSE
)
IDDQ mode(3)
,
fCPU = 8 MHz
fCPU = 16 MHz
VDD from
1.8 V to 3.6 V
fCPU = fLSI
LSI
LSE(5)
external clock
(32.768
fCPU = fLSE
0.032 0.036 0.038
kHz)
f
f
f
f
f
f
CPU = 125 kHz
CPU = 1 MHz
CPU = 4 MHz
CPU = 8 MHz
CPU = 16 MHz
CPU = 125 kHz
0.38 0.48 0.49
0.41 0.49 0.51
0.50 0.57 0.58
0.60 0.66 0.68
0.79 0.84 0.86
0.06 0.08 0.09
0.10 0.17 0.18
0.24 0.36 0.39
0.50 0.58 0.61
1.00 1.08 1.14
0.055 0.058 0.065
HSI
CPU not
clocked,
all peripherals
OFF,
code executed
from Flash,
VDD from
Supply
current in
HSE(4)
external clock
(fCPU=HSE)
fCPU = 1 MHz
IDD(Wait)
Wait
mA
fCPU = 4 MHz
fCPU = 8 MHz
fCPU = 16 MHz
fCPU = fLSI
mode
1.8 V to 3.6 V
LSI
LSE(5)
external clock
(32.768 kHz)
fCPU = fLSE
0.051 0.056 0.060
1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc. , fCPU = fSYSCLK
2. For temperature range 6.
3. Flash is configured in IDDQ mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.
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STM8L052C6
Electrical parameters
4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE
consumption
(IDD HSE) must be added. Refer to Table 28.
5. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE
consumption
(IDD HSE) must be added. Refer to Table 29.
Figure 9.
Typ. I
vs. V , f
= 16 MHz 1)
DD CPU
DD(Wait)
1000
950
900
850
800
750
700
-40°C
25°C
85°C
650
600
550
500
1.8
2.1
2.6
DD [V]
3.1
3.6
V
ai18214V2
1. Typical current consumption measured with code executed from Flash memory.
Doc ID 023331 Rev 1
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Electrical parameters
STM8L052C6
In the following table, data is based on characterization results, unless otherwise specified.
Table 19. Total current consumption and timing in Low power run mode at V = 1.8 V to
DD
3.6 V
Conditions(1)
Symbol
Parameter
Typ
Max
Unit
TA = -40 °C
to 25 °C
5.1
5.4
all peripherals OFF
TA = 55 °C
TA = 85 °C
5.7
6.8
6
7.5
LSI RC osc.
(at 38 kHz)
TA = -40 °C
to 25 °C
5.4
5.7
with TIM2 active(2)
all peripherals OFF
TA = 55 °C
TA = 85 °C
6.0
7.2
6.3
7.8
Supply current in Low
power run mode
IDD(LPR)
μA
TA = -40 °C
to 25 °C
5.25
5.6
TA = 55 °C
TA = 85 °C
5.67
5.85
6.1
6.3
LSE (3) external
clock
(32.768 kHz)
TA = -40 °C
to 25 °C
5.59
6
with TIM2 active (2)
TA = 55 °C
TA = 85 °C
6.10
6.30
6.4
7
1. No floating I/Os
2. Timer 2 clock enabled and counter running
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 29
Figure 10. Typ. I
vs. V (LSI clock source)
DD
DD(LPR)
18
16
14
12
10
8
–40° C
25° C
85° C
6
4
2
0
.
1 8
2.1
2.6
3.1
3.6
V
DD [V]
ai18216V2
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Doc ID 023331 Rev 1
STM8L052C6
In the following table, data is based on characterization results, unless otherwise specified.
Table 20. Total current consumption in Low power wait mode at V = 1.8 V to 3.6 V
Electrical parameters
DD
Conditions(1)
Symbol
Parameter
Typ Max Unit
3.3
3.3 3.6
4.4
3.4 3.7
3.7
TA = -40 °C to 25 °C
3
all peripherals OFF
TA = 55 °C
TA = 85 °C
5
LSI RC osc.
(at 38 kHz)
TA = -40 °C to 25 °C
with TIM2 active(2)
all peripherals OFF
TA = 55 °C
4
TA = 85 °C
4.8 5.4
2.35 2.7
2.42 2.82
3.10 3.71
2.46 2.75
2.50 2.81
3.16 3.82
Supply current in
Low power wait mode
IDD(LPW)
μA
TA = -40 °C to 25 °C
TA = 55 °C
LSE external
clock(3)
(32.768 kHz)
TA = 85 °C
TA = -40 °C to 25 °C
with TIM2 active (2)
TA = 55 °C
TA = 85 °C
1. No floating I/Os.
2. Timer 2 clock enabled and counter is running.
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 29.
Figure 11. Typ. I
vs. V (LSI clock source)
DD
DD(LPW)
16.00
14.00
12.00
10.00
8.00
-40°C
25°C
85°C
6.00
4.00
2.00
0.00
1.8
2.1
2.6
DD [V]
3.1
3.6
ai18217V2
V
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Electrical parameters
In the following table, data is based on characterization results, unless otherwise specified.
Table 21. Total current consumption and timing in Active-halt mode at V = 1.8 V to 3.6 V
STM8L052C6
DD
Conditions (1)
Symbol
Parameter
Typ Max Unit
TA = -40 °C to 25 °C
0.9
1.2
1.5
1.4
1.5
2.1
3
LCD OFF(2)
TA = 55 °C
TA = 85 °C
3.4
3.1
3.3
LCD ON
(static duty/
external
(3)
TA = -40 °C to 25 °C
TA = 55 °C
TA = 85 °C
1.9
1.9
4.3
4.3
VLCD
)
LSI RC
Supply current in
Active-halt mode
IDD(AH)
μA
LCD ON
(1/4 duty/
external
TA = -40 °C to 25 °C
TA = 55 °C
(at 38 kHz)
1.95 4.4
2.4 5.4
(4)
TA = 85 °C
VLCD
)
LCD ON
(1/4 duty/
internal
(5)
TA = -40 °C to 25 °C
TA = 55 °C
3.9 8.75
4.15 9.3
TA = 85 °C
4.5 10.2
VLCD
)
TA = -40 °C to 25 °C
0.5
1.2
LCD OFF(7)
TA = 55 °C
0.62 1.4
0.88 2.1
0.85 1.9
0.95 2.2
TA = 85 °C
LCD ON
(static duty/
external
(3)
TA = -40 °C to 25 °C
TA = 55 °C
LSE external
clock
(32.768 kHz)
TA = 85 °C
1.3
3.2
VLCD
)
Supply current in
Active-halt mode
IDD(AH)
μA
LCD ON
(1/4 duty/
external
TA = -40 °C to 25 °C
TA = 55 °C
1.5
1.6
2.5
3.8
(6)
(4)
TA = 85 °C
1.8
4.2
VLCD
)
LCD ON
(1/4 duty/
internal
(5)
TA = -40 °C to 25 °C
TA = 55 °C
3.4
3.7
7.6
8.3
TA = 85 °C
3.9
9.2
VLCD
)
Supply current during
wakeup time from
Active-halt mode
(using HSI)
IDD(WUFAH)
2.4
mA
Wakeup time from
Active-halt mode to
Run mode (using HSI)
(8)(9)
4.7
7
μs
μs
tWU_HSI(AH)
Wakeup time from
Active-halt mode to
Run mode (using LSI)
(8)
tWU_LSI(AH)
150
(9)
1. No floating I/O, unless otherwise specified.
2. RTC enabled. Clock source = LSI
3. RTC enabled, LCD enabled with external VLCD = 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.
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Electrical parameters
4. RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
5. LCD enabled with internal LCD booster VLCD = 3 V , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD
connected.
6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 29.
7. RTC enabled. Clock source = LSE.
8. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU
.
9. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal
Symbol
Parameter
Condition(1)
Typ
Unit
LSE
LSE/32(3)
LSE
1.15
1.05
1.30
1.20
1.45
1.35
V
DD = 1.8 V
Supply current in Active-halt
mode
(2)
V
DD = 3 V
µA
IDD(AH)
LSE/32(3)
LSE
VDD = 3.6 V
LSE/32(3)
1. No floating I/O, unless otherwise specified.
2. Based on measurements on bench with 32.768 kHz external crystal oscillator.
3. RTC clock is LSE divided by 32.
In the following table, data is based on characterization results, unless otherwise specified.
Table 23. Total current consumption and timing in Halt mode at V = 1.8 to 3.6 V
DD
Symbol
Parameter
Condition(1)
Typ
Max
Unit
1400(2)
2000
TA = -40 °C to 25 °C
TA = 55 °C
350
580
Supply current in Halt mode
IDD(Halt)
nA
(Ultra-low-power ULP bit =1 in
the PWR_CSR2 register)
2800(2)
TA = 85 °C
1160
Supply current during wakeup
time from Halt mode (using
HSI)
IDD(WUHalt)
2.4
mA
Wakeup time from Halt to Run
mode (using HSI)
(3)(4)
4.7
7
µs
µs
tWU_HSI(Halt)
Wakeup time from Halt mode
to Run mode (using LSI)
(3)(4)
150
tWU_LSI(Halt)
1. TA = -40 to 85 °C, no floating I/O, unless otherwise specified.
2. Tested in production.
3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
4. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU
.
Doc ID 023331 Rev 1
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Electrical parameters
STM8L052C6
Current consumption of on-chip peripherals
Table 24. Peripheral current consumption
Typ.
Symbol
Parameter
Unit
VDD = 3.0 V
TIM1 supply current(1)
TIM2 supply current (1)
TIM3 supply current (1)
TIM4 timer supply current (1)
USART1 supply current (2)
SPI1 supply current (2)
I2C1 supply current (2)
DMA1 supply current(2)
WWDG supply current(2)
Peripherals ON(3)
IDD(TIM1)
IDD(TIM2)
IDD(TIM3)
IDD(TIM4)
IDD(USART1)
IDD(SPI1)
IDD(I2C1)
13
8
8
3
6
µA/MHz
3
5
IDD(DMA1)
IDD(WWDG)
IDD(ALL)
3
2
44
1500
µA/MHz
ADC1 supply current(4)
IDD(ADC1)
Power voltage detector and brownout Reset unit supply current
IDD(PVD/BOR)
IDD(BOR)
2.6
2.4
(5)
Brownout Reset unit supply current (5)
including LSI supply
current
Independent watchdog supply current
excluding LSI
µA
0.45
IDD(IDWDG)
0.05
supply current
1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins
toggling. Not tested in production.
3. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.
5. Including supply current of internal reference voltage.
Table 25. Current consumption under external reset
Symbol
Parameter
Conditions
Typ
Unit
VDD = 1.8 V
DD = 3 V
VDD = 3.6 V
48
76
91
Supply current under
external reset (1)
All pins are externally
tied to VDD
IDD(RST)
V
µA
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
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Electrical parameters
8.3.4
Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for V and T .
DD
A
Table 26. HSE external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External clock source
frequency(1)
fHSE_ext
1
16
MHz
OSC_IN input pin high level
voltage
VHSEH
VHSEL
0.7 x VDD
VSS
VDD
V
OSC_IN input pin low level
voltage
0.3 x VDD
OSC_IN input
capacitance(1)
Cin(HSE)
2.6
pF
µA
OSC_IN input leakage
current
ILEAK_HSE
VSS < VIN < VDD
1
1. Data guaranteed by Design, not tested in production.
LSE external clock (LSEBYP=1 in CLK_ECKCR)
Subject to general operating conditions for V and T .
DD
A
Table 27. LSE external clock characteristics
Symbol
Parameter
Min
Typ
Max
Unit
External clock source frequency(1)
fLSE_ext
32.768
kHz
(2)
OSC32_IN input pin high level voltage
0.7 x VDD
VSS
VDD
VLSEH
V
(2)
OSC32_IN input pin low level voltage
0.3 x VDD
VLSEL
OSC32_IN input capacitance(1)
OSC32_IN input leakage current
Cin(LSE)
0.6
pF
µA
ILEAK_LSE
1
1. Data guaranteed by Design, not tested in production.
2. Data based on characterization results, not tested in production.
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Electrical parameters
STM8L052C6
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 28. HSE oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
High speed external oscillator
frequency
fHSE
1
16
MHz
RF
Feedback resistor
200
20
kΩ
C(1)
pF
Recommended load capacitance (2)
C = 20 pF,
OSC = 16 MHz
2.5 (startup)
f
0.7 (stabilized)(3)
IDD(HSE) HSE oscillator power consumption
mA
C = 10 pF,
2.5 (startup)
fOSC =16 MHz
0.46 (stabilized)(3)
gm
Oscillator transconductance
Startup time
3.5(3)
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
1
1. C=
C =CL2 is approximately equivalent to 2 x crystal CLOAD.
L1
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Data guaranteed by Design. Not tested in production.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This
value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 12. HSE oscillator circuit diagram
f
to core
HSE
R
m
R
F
C
O
L
m
C
L1
OSC_IN
C
m
g
m
Resonator
Consumption
control
Resonator
STM8
OSC_OUT
C
L2
HSE oscillator critical g formula
m
gmcrit = (2 × Π × fHSE)2 × Rm(2Co + C)2
R : Motional resistance (see crystal specification), L : Motional inductance (see crystal specification),
m
m
C : Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),
m
C
=C =C: Grounded external capacitance
L1
L2
g
>> g
m
mcrit
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Doc ID 023331 Rev 1
STM8L052C6
Electrical parameters
LSE crystal/ceramic resonator oscillator
The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 29. LSE oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Low speed external oscillator
frequency
fLSE
32.768
kHz
RF
Feedback resistor
ΔV = 200 mV
1.2
8
MΩ
pF
C(1)
Recommended load capacitance (2)
1.4(3)
µA
V
DD = 1.8 V
450
600
750
IDD(LSE) LSE oscillator power consumption
VDD = 3 V
nA
VDD = 3.6 V
gm
Oscillator transconductance
Startup time
3(3)
µA/V
s
(4)
tSU(LSE)
VDD is stabilized
1
1. C=
C =CL2 is approximately equivalent to 2 x crystal CLOAD.
L1
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value.
Refer to crystal manufacturer for more details.
3. Data guaranteed by Design. Not tested in production.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 13. LSE oscillator circuit diagram
f
LSE
R
m
R
F
C
O
L
m
C
L1
OSC_IN
C
m
g
m
Resonator
Consumption
control
Resonator
STM8
OSC_OUT
C
L2
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Electrical parameters
STM8L052C6
Internal clock sources
Subject to general operating conditions for V , and T .
DD
A
High speed internal RC oscillator (HSI)
In the following table, data is based on characterization results, not tested in production,
unless otherwise specified.
Table 30. HSI oscillator characteristics
Conditions(1)
Symbol
Parameter
Frequency
Min
Typ
Max
Unit
fHSI
VDD = 3.0 V
DD = 3.0 V, TA = 25 °C
16
MHz
%
V
-1 (2)
-5
1(2)
5
Accuracy of HSI
oscillator (factory
calibrated)
ACCHSI
TRIM
1.8 V ≤ VDD ≤ 3.6 V,
-40 °C ≤ TA ≤ 85 °C
%
Trimming code ≠ multiple of 16
0.4
0.7
1.5
%
%
HSI user trimming
step(3)
Trimming code = multiple of 16
HSI oscillator setup
time (wakeup time)
tsu(HSI)
3.7
6(4)
µs
HSI oscillator power
consumption
IDD(HSI)
100
140(4)
µA
1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.
2. Tested in production.
3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16
(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for
more details.
4. Guaranteed by design, not tested in production.
Figure 14. Typical HSI frequency vs V
DD
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
-40°C
25°C
85°C
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85
3
3.15 3.3 3.45 3.6
ai18218V2
VDD [V]
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STM8L052C6
Low speed internal RC oscillator (LSI)
Electrical parameters
In the following table, data is based on characterization results, not tested in production.
Table 31. LSI oscillator characteristics
Parameter (1)
Conditions(1)
Symbol
Min
Typ
Max
Unit
fLSI
Frequency
26
38
56
kHz
µs
tsu(LSI) LSI oscillator wakeup time
200(2)
LSI oscillator frequency
IDD(LSI)
0 °C ≤ TA ≤ 85 °C
-12
11
%
drift(3)
1. VDD = 1.8 V to 3.6 V, TA = -40 to 85 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. This is a deviation for an individual part, once the initial frequency has been measured.
Figure 15. Typical LSI frequency vs. V
DD
45
43
41
39
37
35
33
31
29
27
25
-40°C
25°C
85°C
1.8
2.1
2.6
3.1
3.6
VDD [V]
ai18219V2
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Electrical parameters
STM8L052C6
8.3.5
Memory characteristics
T = -40 to 85 °C unless otherwise specified.
A
Table 32. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM
Data retention mode (1)
Halt mode (or Reset)
1.8
V
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.
Flash memory
Table 33. Flash program and data EEPROM memory
Max
Symbol
Parameter
Conditions
Min
Typ
Unit
(1)
Operating voltage
(all modes, read/write/erase)
VDD
fSYSCLK = 16 MHz
1.8
3.6
V
Programming time for 1 or 64 bytes (block)
erase/write cycles (on programmed byte)
6
3
ms
ms
tprog
Programming time for 1 to 64 bytes (block)
write cycles (on erased byte)
TA=+25 °C, VDD = 3.0 V
TA=+25 °C, VDD = 1.8 V
Iprog
Programming/ erasing consumption
0.7
mA
Data retention (program memory) after 100
erase/write cycles at TA= –40 to +85 °C
TRET = +85 °C
TRET = +85 °C
30(1)
30(1)
(2)
tRET
years
cycles
kcycles
Data retention (data memory) after 100000
erase/write cycles at TA= –40 to +85 °C
Erase/write cycles (program memory)
Erase/write cycles (data memory)
100(1)
TA = –40 to +85 °C
(3)
NRW
100(1)
(4)
1. Data based on characterization results, not tested in production.
2. Conforming to JEDEC JESD22a117
3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation
addresses a single byte.
4. Data based on characterization performed on the whole data memory.
8.3.6
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard pins) should be avoided during normal product operation. However,
DD
in order to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.
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STM8L052C6
Electrical parameters
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.
Table 34. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on true open-drain pins (PC0 and
PC1)
-5
+0
Injected current on all five-volt tolerant (FT) pins
Injected current on all 3.6 V tolerant (TT) pins
Injected current on any other pin
-5
-5
-5
+0
+0
+5
IINJ
mA
8.3.7
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V and T unless otherwise specified. All
DD
A
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
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Electrical parameters
STM8L052C6
Table 35. I/O static characteristics
Conditions(1)
Symbol
Parameter
Min
Max
Unit
Typ
Input voltage on true open-drain
pins (PC0 and PC1)
VSS-0.3
0.3 x VDD
Input voltage on five-volt
tolerant (FT) pins (PA7 and
PE0)
VSS-0.3
VSS-0.3
0.3 x VDD
Input low level voltage(2)
VIL
V
Input voltage on 3.6 V tolerant
(TT) pins
0.3 x VDD
0.3 x VDD
VSS-0.3
Input voltage on any other pin
Input voltage on true open-drain
pins (PC0 and PC1)
with VDD < 2 V
5.2
5.5
0.70 x VDD
Input voltage on true open-drain
pins (PC0 and PC1)
with VDD ≥ 2 V
Input voltage on five-volt
tolerant (FT) pins (PA7 and
PE0)
5.2
5.5
Input high level voltage (2)
VIH
V
with VDD < 2 V
Input voltage on five-volt
tolerant (FT) pins (PA7 and
PE0)
0.70 x VDD
with VDD ≥ 2 V
Input voltage on 3.6 V tolerant
(TT) pins
3.6
0.70 x VDD
VDD+0.3
Input voltage on any other pin
I/Os
200
200
Schmitt trigger voltage
hysteresis (3)
Vhys
mV
nA
True open drain I/Os
VSS≤ VIN≤ VDD
High sink I/Os
-
-
-
-
50 (5)
VSS≤ VIN≤ VDD
True open drain I/Os
200(5)
Ilkg
Input leakage current (4)
VSS≤ VIN≤ VDD
PA0 with high sink LED driver
capability
-
-
200(5)
60
Weak pull-up equivalent
resistor(2)(6)
RPU
CIO
VIN=VSS
30
45
5
kΩ
I/O pin capacitance
pF
1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
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STM8L052C6
Electrical parameters
6. RPU pull-up equivalent resistor based on a resistive transistor(corresponding IPU current characteristics described in
Figure 19).
Figure 16. Typical V and V vs V (high sink I/Os)
IL
IH
DD
3
2.5
2
-40°C
25°C
85°C
1.5
1
0.5
0
1.8
2.1
2.6
VDD [V]
3.1
3.6
ai18220V2
Figure 17. Typical V and V vs V (true open drain I/Os)
IL
IH
DD
3
2.5
2
-40°C
25°C
85°C
1.5
1
0.5
0
1.8
2.1
2.6
3.1
3.6
VDD [V]
ai18221V2
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Electrical parameters
STM8L052C6
Figure 18. Typical pull-up resistance R vs V with V =V
PU
DD
IN
SS
60
55
50
45
40
35
30
-40°C
25°C
85°C
1.8
2
2.2
2.4
2.6
VDD [V]
2.8
3
3.2
3.4
3.6
ai18222V2
Figure 19. Typical pull-up current I vs V with V =V
pu
DD
IN
SS
120
100
80
60
40
20
0
-40°C
25°C
85°C
1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85
DD [V]
3
3.15 3.3 3.45 3.6
ai18223V2
V
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STM8L052C6
Electrical parameters
Output driving current
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 36. Output driving current (high sink ports)
I/O
Symbol
Parameter
Conditions
Min
Max Unit
Type
IIO = +2 mA,
VDD = 3.0 V
0.45
0.45
0.7
V
V
V
V
V
V
IIO = +2 mA,
VDD = 1.8 V
(1)
Output low level voltage for an I/O pin
VOL
IIO = +10 mA,
VDD = 3.0 V
IIO = -2 mA,
VDD = 3.0 V
VDD-0.45
IIO = -1 mA,
VDD = 1.8 V
(2)
VDD-0.45
Output high level voltage for an I/O pin
VOH
IIO = -10 mA,
VDD = 3.0 V
VDD-0.7
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 13 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD
.
Table 37. Output driving current (true open drain ports)
I/O
Symbol
Parameter
Conditions
Min
Max Unit
Type
IIO = +3 mA,
VDD = 3.0 V
0.45
V
(1)
Output low level voltage for an I/O pin
VOL
I
IO = +1 mA,
0.45
VDD = 1.8 V
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS
.
Table 38. Output driving current (PA0 with high sink LED driver capability)
I/O
Symbol
Parameter
Conditions
Min
Max Unit
Type
IIO = +20 mA,
VDD = 2.0 V
(1)
Output low level voltage for an I/O pin
0.45
V
VOL
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS
.
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Electrical parameters
STM8L052C6
Figure 20. Typ. V @ V = 3.0 V (high sink
Figure 21. Typ. V @ V = 1.8 V (high sink
OL DD
OL
DD
ports)
ports)
1
0.75
0.5
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40°C
25°C
85°C
-40°C
25°C
85°C
0.25
0
0
1
2
3
4
5
6
7
8
0
2
4
6
8
10
IOL [mA]
12
14
16
18
20
I
OL [mA]
ai18227V2
ai18226V2
Figure 22. Typ. V @ V = 3.0 V (true open Figure 23. Typ. V @ V = 1.8 V (true open
OL
DD
OL
DD
drain ports)
drain ports)
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-40°C
25°C
85°C
-40°C
25°C
85°C
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
OL [mA]
I
OL [mA]
BJꢀꢁꢂꢂꢃ7ꢂ
ai18228V2
Figure 24. Typ. V
V
@ V = 3.0 V (high Figure 25. Typ. V
V
@ V = 1.8 V (high
DD - OH
DD
DD - OH DD
sink ports)
sink ports)
2
1.75
1.5
1.25
1
0.5
0.4
0.3
0.2
0.1
0
-40°C
25°C
85°C
-40°C
25°C
85°C
0.75
0.5
0.25
0
0
2
4
6
8
10
IOH [mA]
12
14
16
18
20
0
1
2
3
4
5
6
7
IOH [mA]
BJꢀꢁꢂꢄꢀ7ꢂ
ai12830V2
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STM8L052C6
Electrical parameters
NRST pin
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 39. NRST pin characteristics
Symbol
VIL(NRST)
VIH(NRST)
Parameter
Conditions
Min
VSS
1.4
Max
Unit
Typ
NRST input low level voltage (1)
NRST input high level voltage (1)
0.8
VDD
IOL = 2 mA
for 2.7 V ≤ VDD ≤ 3.6
V
V
NRST output low level voltage (1)
NRST input hysteresis(3)
VOL(NRST)
0.4
I
OL = 1.5 mA
for VDD < 2.7 V
10%VDD
VHYST
mV
(2)
NRST pull-up equivalent resistor
RPU(NRST)
30
45
60
50
kΩ
(1)
NRST input filtered pulse (3)
VF(NRST)
ns
NRST input not filtered pulse (3)
VNF(NRST)
300
1. Data based on characterization results, not tested in production.
2. 200 mV min.
3. Data guaranteed by design, not tested in production.
Figure 26. Typical NRST pull-up resistance R vs V
PU
DD
60
-40°C
25°C
85°C
55
50
45
40
35
30
1.8
2
2.2
2.4
2.6
VDD [V]
2.8
3
3.2
3.4
3.6
ai18224V2
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Electrical parameters
Figure 27. Typical NRST pull-up current I vs V
STM8L052C6
pu
DD
120
100
80
60
40
20
0
-40°C
25°C
°C
85
1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85
VDD [V]
3
3.15 3.3 3.45 3.6
ai18225V2
The reset network shown in Figure 28 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V max. level specified
IL(NRST)
in Table 39. Otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If the NRST signal is used to reset the
external circuitry, attention must be paid to the charge/discharge time of the external
capacitor to fulfill the external devices reset timing conditions. The minimum recommended
capacity is 10 nF.
Figure 28. Recommended NRST pin configuration
V
DD
RPU
EXTERNAL
RESET
NRST
INTERNAL RESET
Filter
CIRCUIT
0.1 µF
STM8
(Optional)
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STM8L052C6
Electrical parameters
8.3.8
Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under ambient temperature, f frequency and V supply voltage
SYSCLK
DD
conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 40. SPI1 characteristics
Symbol
Parameter
Conditions(1)
Master mode
Min
Max
Unit
MHz
ns
0
0
8
8
fSCK
1/tc(SCK)
SPI1 clock frequency
Slave mode
tr(SCK)
tf(SCK)
SPI1 clock rise and fall
time
Capacitive load: C = 30 pF
-
30
(2)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 x 1/fSYSCLK
80
-
-
(2)
th(NSS)
(2)
tw(SCKH)
tw(SCKL)
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
SCK high and low time
Data input setup time
105
145
(2)
(2)
Master mode
30
3
-
tsu(MI)
tsu(SI)
(2)
Slave mode
-
(2)
Master mode
15
0
-
th(MI)
th(SI)
Data input hold time
(2)
Slave mode
-
(2)(3)
ta(SO)
Data output access time
Data output disable time
Data output valid time
Slave mode
-
3x 1/fSYSCLK
(2)(4)
tdis(SO)
Slave mode
30
-
-
(2)
(2)
(2)
(2)
tv(SO)
tv(MO)
th(SO)
th(MO)
Slave mode (after enable edge)
60
Master mode (after enable
edge)
Data output valid time
-
20
-
Slave mode (after enable edge)
15
1
Data output hold time
Master mode (after enable
edge)
-
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.
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Electrical parameters
STM8L052C6
Figure 29. SPI1 timing diagram - slave mode and CPHA=0
NSS input
t
t
t
h(NSS)
SU(NSS)
c(SCK)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
dis(SO)
v(SO)
r(SCK)
f(SCK)
h(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134
(1)
Figure 30. SPI1 timing diagram - slave mode and CPHA=1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
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STM8L052C6
Electrical parameters
(1)
Figure 31. SPI1 timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
BIT6 IN
LSB IN
t
h(MI)
MOSI
OUTUT
M SB OUT
BIT1 OUT
LSB OUT
t
t
h(MO)
v(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
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Electrical parameters
STM8L052C6
I2C - Inter IC control interface
Subject to general operating conditions for V
, and T unless otherwise specified.
, f
DD
A
SYSCLK
2
2
The STM8L I C interface (I2C1) meets the requirements of the Standard I C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 41. I2C characteristics
Standard mode
Fast mode I2C(1)
I2C
Symbol
Parameter
Unit
Min(2)
4.7
Max (2)
Min (2)
1.3
Max (2)
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
μs
SCL clock high time
SDA setup time
4.0
0.6
250
0
100
0
SDA data hold time
900
300
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
1000
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
th(STA)
tsu(STA)
tsu(STO)
tw(STO:STA)
Cb
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
μs
Repeated START condition setup
time
STOP condition setup time
μs
μs
pF
STOP to START condition time (bus
free)
Capacitive load for each bus line
400
400
1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).
Data based on standard I2C protocol requirement, not tested in production.
2.
Note:
For speeds around 200 kHz, the achieved speed can have a 5% tolerance
For other speed ranges, the achieved speed can have a 2% tolerance
The above variations depend on the accuracy of the external components used.
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STM8L052C6
Figure 32.
Electrical parameters
2
Typical application with I C bus and timing diagram1)
V
V
DD
DD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDA
SCL
2
I C BUS
STM8L
REPEATED START
START
t
t
su(STA)
w(STO:STA)
START
SDA
t
t
r(SDA)
f(SDA)
STOP
t
t
h(SDA)
su(SDA)
SCL
t
t
t
t
t
su(STO)
t
h(STA)
w(SCLH)
w(SCLL)
r(SCL)
f(SCL)
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
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Electrical parameters
STM8L052C6
8.3.9
LCD controller
In the following table, data is guaranteed by design. Not tested in production.
Table 42. LCD characteristics
Symbol
Parameter
Min
Typ
Max.
Unit
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
VLCD6
VLCD7
CEXT
LCD external voltage
3.6
V
V
LCD internal reference voltage 0
LCD internal reference voltage 1
LCD internal reference voltage 2
LCD internal reference voltage 3
LCD internal reference voltage 4
LCD internal reference voltage 5
LCD internal reference voltage 6
LCD internal reference voltage 7
VLCD external capacitance
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
V
V
V
V
V
V
V
0.1
2
µF
µA
µA
MΩ
kΩ
V
Supply current(1) at VDD = 1.8 V
Supply current(1) at VDD = 3 V
3
3
IDD
(2)
RHN
High value resistive network (low drive)
Low value resistive network (high drive)
Segment/Common higher level voltage
Segment/Common 2/3 level voltage
Segment/Common 1/2 level voltage
Segment/Common 1/3 level voltage
Segment/Common lowest level voltage
6.6
360
(3)
RLN
V33
V23
V12
V13
V0
VLCDx
2/3VLCDx
1/2VLCDx
1/3VLCDx
V
V
V
0
V
1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.
2. RHN is the total high value resistive network.
3. RLN is the total low value resistive network.
VLCD external capacitor
The application can achieve a stabilized LCD reference voltage by connecting an external
capacitor C
to the V
pin. C
is specified in Table 42.
EXT
LCD
EXT
86/102
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STM8L052C6
Electrical parameters
8.3.10
Embedded reference voltage
In the following table, data is based on characterization results, not tested in production,
unless otherwise specified.
Table 43. Reference voltage characteristics
Symbol
Parameter
Conditions
Min
Typ
Max.
Unit
Internal reference voltage
consumption
IREFINT
1.4
µA
ADC sampling time when reading
the internal reference voltage
(1)(2)
TS_VREFINT
5
10
25
µs
Internal reference voltage buffer
consumption (used for ADC)
(2)
IBUF
13.5
µA
V
VREFINT out
Reference voltage output
1.202(3) 1.224 1.242(3)
Internal reference voltage low
power buffer consumption
(2)
ILPBUF
730
1200
nA
(2)
IREFOUT
Buffer output current(4)
1
µA
pF
CREFOUT
tVREFINT
Reference voltage output load
50
Internal reference voltage startup
time
2
3
10
5
ms
µs
Internal reference voltage buffer
startup time once enabled (1)
(2)
tBUFEN
Accuracy of VREFINT stored in the
VREFINT_Factory_CONV byte(5)
ACCVREFINT
STABVREFINT
STABVREFINT
mV
Stability of VREFINT over
temperature
-40 °C ≤ TA ≤
20
50
20
TBD
ppm/°C
ppm/°C
ppm
85 °C
Stability of VREFINT over
temperature
0 °C ≤ TA ≤ 50
°C
Stability of VREFINT after 1000
hours
1. Defined when ADC output reaches its final value 1/2LSB
2. Data guaranteed by Design. Not tested in production.
3. Tested in production at VDD = 3 V 10 mV.
4. To guaranty less than 1% VREFOUT deviation.
5. Measured at VDD = 3 V 10 mV. This value takes into account VDD accuracy and ADC conversion accuracy.
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Electrical parameters
STM8L052C6
8.3.11
12-bit ADC1 characteristics
In the following table, data is guaranteed by design, not tested in production.
Table 44. ADC1 characteristics
Symbol
Parameter
Conditions
Min
1.8
2.4
Typ
Max
Unit
V
VDDA
Analog supply voltage
3.6
2.4 V ≤ VDDA≤ 3.6 V
1.8 V ≤ VDDA≤ 2.4 V
VDDA
V
Reference supply
voltage
VREF+
VDDA
VSSA
V
VREF-
IVDDA
Lower reference voltage
V
Current on the VDDA
input pin
1000
1450
µA
µA
µA
700
(peak)(1)
Current on the VREF+
input pin
IVREF+
400
450
(average)(1)
Conversion voltage
range
0(2)
-40
VAIN
TA
VREF+
Temperature range
85
°C
on PF0 fast channel
on all other channels
on PF0 fast channel
on all other channels
External resistance on
VAIN
50(3)
kΩ
RAIN
Internal sample and
hold capacitor
CADC
16
pF
2.4 V≤ VDDA≤ 3.6 V
without zooming
0.320
0.320
16
8
MHz
ADC sampling clock
frequency
fADC
1.8 V≤ VDDA≤ 2.4 V
MHz
MHz
kHz
with zooming
VAIN on PF0 fast
1(4)(5)
channel
fCONV
12-bit conversion rate
VAIN on all other
channels
760(4)(5)
External trigger
frequency
fTRIG
tLAT
tconv
3.5
1/fADC
External trigger latency
1/fSYSCLK
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STM8L052C6
Electrical parameters
Table 44. ADC1 characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VAIN on PF0 fast
channel
0.43(4)(5)
µs
VDDA < 2.4 V
VAIN on PF0 fast
channel
2.4 V ≤ VDDA≤ 3.6 V
0.22(4)(5)
µs
tS
Sampling time
VAIN on slow channels
VDDA < 2.4 V
0.86(4)(5)
0.41(4)(5)
µs
µs
VAIN on slow channels
2.4 V ≤ VDDA≤ 3.6 V
12 + tS
1(4)
1/fADC
µs
tconv
12-bit conversion time
16 MHz
Wakeup time from OFF
state
tWKUP
3
µs
TA = +25 °C
TA = +70 °C
1(7)
s
Time before a new
conversion
(6)
tIDLE
20(7)
ms
Internal reference
voltage startup time
refer to
Table 43
tVREFINT
ms
1. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
2. VREF- or VDDA must be tied to ground.
3. Guaranteed by design, not tested in production.
4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 kΩ.
5. Value obtained for continuous conversion on fast channel.
6. The time between 2 conversions, or between ADC ON and the first conversion must be lower than tIDLE.
7. The tIDLE maximum value is ∞ on the “Z” revision code of the device.
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Electrical parameters
STM8L052C6
In the following three tables, data is guaranteed by characterization result, not tested in
production.
Table 45. ADC1 accuracy with V
= 3.3 V to 2.5 V
Conditions
DDA
Symbol
Parameter
Typ
Max
Unit
fADC = 16 MHz
1
1.6
1.6
1.5
2
DNL
Differential non linearity fADC = 8 MHz
fADC = 4 MHz
1
1
fADC = 16 MHz
1.2
1.2
1.2
2.2
1.8
1.8
1.5
1
INL
TUE
Integral non linearity
Total unadjusted error
Offset error
f
ADC = 8 MHz
1.8
1.7
3.0
2.5
2.3
2
LSB
fADC = 4 MHz
fADC = 16 MHz
f
ADC = 8 MHz
fADC = 4 MHz
ADC = 16 MHz
f
Offset
Gain
fADC = 8 MHz
fADC = 4 MHz
1.5
1.2
0.7
LSB
f
ADC = 16 MHz
Gain error
fADC = 8 MHz
fADC = 4 MHz
1
1.5
Table 46. ADC1 accuracy with V
Symbol
= 2.4 V to 3.6 V
DDA
Parameter
Typ
1
Max
Unit
LSB
LSB
DNL
INL
Differential non linearity
Integral non linearity
2
3
1.7
TUE
Offset
Gain
2
1
4
2
3
LSB
LSB
LSB
Total unadjusted error
Offset error
Gain error
1.5
Table 47. ADC1 accuracy with V
Symbol
= V
= 1.8 V to 2.4 V
REF+
DDA
Parameter
Typ
1
Max
2
Unit
LSB
LSB
DNL
INL
Differential non linearity
Integral non linearity
2
3
TUE
Offset
Gain
3
2
2
5
3
3
LSB
LSB
LSB
Total unadjusted error
Offset error
Gain error
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STM8L052C6
Figure 33. ADC1 accuracy characteristics
Electrical parameters
VREF+
VDDA
4096
[1LSBIDEAL
=
(or
depending on package)]
4096
EG
(1) Example of an actual transfer curve
4095
4094
4093
(2) The ideal transfer curve
(3) End point correlation line
(2)
ET=Total Unadjusted Error: maximum deviation
ET
between the actual and the ideal transfer curves.
(3)
7
6
5
4
3
2
1
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
(1)
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
ED
1 LSBIDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
VSSA
ai14395b
Figure 34. Typical connection diagram using the ADC
STM8L05xxx
V
DD
Sample and hold ADC
V
0.6 V
T
converter
(1)
C
R
R
AIN
ADC
AINx
12-bit
converter
V
T
V
AIN
0.6 V
C
(1)
ADC
parasitic
I
50 nA
L
ai17090e
1. Refer to Table 44 for the values of RAIN and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
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Electrical parameters
Figure 35. Maximum dynamic current consumption on V
STM8L052C6
supply pin during ADC
REF+
conversion
Sampling (n cycles)
Conversion (12 cycles)
ADC clock
I
ref+
700µA
300µA
(1)
Table 48.
R
max for f
= 16 MHz
ADC
AIN
RAIN max (kohm)
Ts
(cycles)
Ts
(µs)
Slow channels
Fast channels
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V
4
9
0.25
Not allowed
0.8
Not allowed
Not allowed
0.8
0.7
2.0
Not allowed
1.0
0.5625
16
24
48
96
192
384
1
1.5
3
2.0
4.0
3.0
3.0
1.8
6.0
4.5
6.8
4.0
15.0
30.0
50.0
50.0
10.0
6
15.0
32.0
50.0
10.0
20.0
12
24
25.0
40.0
50.0
50.0
1. Guaranteed by design, not tested in production.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 36 or Figure 37,
depending on whether V is connected to V or not. Good quality ceramic 10 nF
REF+
DDA
capacitors should be used. They should be placed as close as possible to the chip.
92/102
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Electrical parameters
Figure 36. Power supply and reference decoupling (V
not connected to V
)
DDA
REF+
STM8L
V
REF+
DDA
External
reference
1 μF // 10 nF
V
V
Supply
1 μF // 10 nF
/V
SSA REF-
ai17031b
Figure 37. Power supply and reference decoupling (V
connected to V
)
REF+
DDA
STM8L
VREF+/VDDA
Supply
1 μF // 10 nF
VREF–/VSSA
ai17032b
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Electrical parameters
STM8L052C6
8.3.12
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000 standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
DD
SS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 49. EMS data
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, TA = +25 °C,
Voltage limits to be applied on
VFESD
any I/O pin to induce a functional fCPU= 16 MHz,
3B
disturbance
conforms to IEC 61000
Fast transient voltage burst limits
to be applied through 100 pF on
VDD and VSS pins to induce a
VDD = 3.3 V, TA = +25 °C,
fCPU = 16 MHz,
conforms to IEC 61000
4A
2B
Using HSI
Using HSE
VEFTB
functional disturbance
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC61967-2 which specifies the board and the loading of each pin.
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Electrical parameters
(1)
Table 50. EMI data
Max vs.
Unit
16 MHz
Monitored
frequency band
Symbol
Parameter
Conditions
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
-3
VDD = 3.6 V,
TA = +25 °C,
LQFP32
conforming to
IEC61967-2
9
4
2
dBμV
SEMI
Peak level
-
1. Not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.
Table 51. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Unit
value (1)
Electrostatic discharge voltage
(human body model)
VESD(HBM)
2000
TA = +25 °C
V
Electrostatic discharge voltage
(charge device model)
VESD(CDM)
500
1. Data based on characterization results, not tested in production.
Static latch-up
●
LU: 3 complementary static tests are required on 6 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
Table 52. Electrical sensitivities
Symbol
Parameter
Class
LU
Static latch-up class
II
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Electrical parameters
STM8L052C6
8.4
Thermal characteristics
The maximum chip junction temperature (T
) must never exceed the values given in
Jmax
Table 15: General operating conditions on page 55.
The maximum chip-junction temperature, T
the following equation:
, in degree Celsius, may be calculated using
Jmax
T
= T
+ (P
x Θ )
Jmax
Amax
Dmax JA
Where:
●
●
●
●
T
is the maximum ambient temperature in °C
is the package junction-to-ambient thermal resistance in °C/W
Amax
Θ
P
JA
is the sum of P
and P
(P
= P
+ P
)
I/Omax
Dmax
INTmax
I/Omax
Dmax
INTmax
P
is the product of I and V , expressed in Watts. This is the maximum chip
INTmax
DD
DD
internal power.
●
P
represents the maximum power dissipation on output pins
I/Omax
Where:
P
= Σ (V *I ) + Σ((V -V )*I ),
I/Omax
OL OL
DD OH
OH
taking into account the actual V /I and V /I of the I/Os at low and high level in
OL OL
OH OH
the application.
(1)
Table 53. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP 48- 7 x 7 mm
ΘJA
65
°C/W
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
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STM8L052C6
Package characteristics
9
Package characteristics
9.1
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 023331 Rev 1
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Package characteristics
STM8L052C6
9.2
Package mechanical data
9.2.1
48-pin low profile quad flat 7x7mm package (LQFP48)
Figure 38. LQFP48 48-pin low profile quad flat package outline
D
ccc
$
D1
D3
"
"ꢂ
25
36
24
37
48
L1
b
E3
E1 E
L
13
A1
K
Pin 1
identification
1
12
D
5B_ME
1. Drawing is not to scale.
Table 54. LQFP48 48-pin low profile quad flat package, mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
1.6
0.15
1.45
0.27
0.2
0.063
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
0.05
1.35
0.17
0.09
8.8
0.002
0.0531
0.0067
0.0035
0.3465
0.2677
1.4
0.0551
0.0087
0.22
c
D
9
7
9.2
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
6.8
7.2
5.5
9
8.8
6.8
9.2
7.2
0.3465
0.2677
0.3622
0.2835
E1
E3
e
7
5.5
0.5
0.6
1
L
0.45
0.0°
0.75
0.0177
0.0°
0.0295
L1
k
3.5°
7.0°
0.08
7.0°
ccc
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
98/102
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STM8L052C6
Figure 39. LQFP48 recommended footprint
Package characteristics
0.50
1.20
0.30
36
25
37
24
0.20
7.30
9.70 5.80
7.30
48
13
12
1
1.20
5.80
9.70
5B_FP
1. Dimensions are in millimeters.
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Device ordering information
STM8L052C6
10
Device ordering information
Figure 40. Medium density value line STM8L05xxx ordering information scheme
Example:
STM8
L
052
C
6
T
6
Product class
STM8 microcontroller
Family type
L = Low power
Sub-family type
052 = Ultra-low-power with LCD
Pin count
C = 48 pins
Program memory size
6 = 32 Kbytes
Package
T = LQFP
Temperature range
6 = - 40 °C to 85 °C
1. For a list of available options (e.g. memory size, package) and orderable part numbers
or for further information on any aspect of this device, please contact the ST sales
office nearest to you
100/102
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Revision history
11
Revision history
Table 55. Document revision history
Date
Revision
Changes
22-Jun-2012
1
Initial release.
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STM8L052C6
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相关型号：
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STMICROELECTR
STM8L101F1P3
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1P3A
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1P3ATR
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1P3TR
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1P6
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1P6A
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1P6ATR
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1P6TR
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
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