STM8L101F1P6 [STMICROELECTRONICS]
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C; 8位超低功耗微控制器,高达8 KB闪存多功能定时器,比较器, USART , SPI , I2C型号: | STM8L101F1P6 |
厂家: | ST |
描述: | 8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C |
文件: | 总81页 (文件大小:1992K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STM8L101xx
8-bit ultralow power microcontroller with up to 8 Kbytes Flash,
multifunction timers, comparators, USART, SPI, I2C
Features
■ Main microcontroller features
– Supply voltage range 1.65 V to 3.6 V
– Low power consumption (Halt: 0.3 µA,
Active-halt: 0.8 µA, Dynamic Run:
150 µA/MHz)
UFQFPN32
LQFP32
– STM8 Core with up to 16 CISC MIPS
throughput
– Temp. range: -40 to 85 °C and 125 °C
UFQFPN28
■ Peripherals
UFQFPN20
TSSOP20
■
Memories
– Up to 8 Kbytes of Flash program including
up to 2 Kbytes of data EEPROM
– Two 16-bit general purpose timers (TIM2
and TIM3) with up and down counter and 2
channels (used as IC, OC, PWM)
– Error correction code (ECC)
– One 8-bit timer (TIM4) with 7-bit prescaler
– Infrared remote control (IR)
– Flexible write and read protection modes
– In-application and in-circuit programming
– Data EEPROM capability
– Independent watchdog
– Auto-wakeup unit
– 1.5 Kbytes of static RAM
– Beeper timer with 1, 2 or 4 kHz frequencies
– SPI synchronous serial interface
– Fast I2C Multimaster/slave 400 kHz
– USART with fractional baud rate generator
– 2 comparators with 4 inputs each
■
Clock management
– Internal 16 MHz RC with fast wakeup time
(typ. 4 µs)
– Internal low consumption 38 kHz RC
driving both the IWDG and the AWU
■ Reset and supply management
■ Development support
– Ultralow power, ultrasafe power-on-reset
/power down reset
– Hardware single wire interface module
(SWIM) for fast on-chip programming and
non intrusive debugging
– Three low power modes: Wait, Active-halt,
Halt
– In-circuit emulation (ICE)
■ Interrupt management
■ 96-bit unique ID
– Nested interrupt controller with software
priority control
– Up to 29 external interrupt sources
Table 1.
Device summary
Part number
Reference
■ I/Os
STM8L101F1, STM8L101F2,
STM8L101F3,
STM8L101G2, STM8L101G3
STM8L101K3
– Up to 30 I/Os, all mappable on external
interrupt vectors
– I/Os with prog. input pull-ups, high
sink/source capability and one LED driver
infrared output
STM8L101xx
October 2010
Doc ID 15275 Rev 11
1/81
www.st.com
1
Contents
STM8L101xx
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . 10
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.10 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.11 General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.13 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.14 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.15 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.16 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.17 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
5
6
7
8
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Contents
9
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2
9.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 41
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11
12
Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Doc ID 15275 Rev 11
3/81
List of tables
STM8L101xx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STM8L101xx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Total current consumption and timing in Halt and Active-halt mode at
VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 53
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . 69
UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4),
Table 40.
Table 41.
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
UFQFPN20 3 x 3 mm 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
20-lead thin shrink small package, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 42.
Table 43.
Table 44.
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STM8L101xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
STM8L101xx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standard 20-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
20-pin UFQFPN package pinout for STM8L101F1U6ATR,
STM8L101F2U6ATR and STM8L101F3U6ATR part numbers. . . . . . . . . . . . . . . . . . . . . . 15
20-pin TSSOP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standard 28-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
28-pin UFQFPN package pinout for STM8L101G3U6ATR and
Figure 4.
Figure 5.
Figure 6.
STM8L101G2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 7.
Figure 8.
Figure 9.
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. IDD(RUN) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. IDD(WAIT) vs. VDD, fCPU = 2 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 14. IDD(WAIT) vs. VDD, fCPU = 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Typical HSI frequency vs. V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DD
Figure 17. Typical HSI accuracy vs. temperature, V = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DD
Figure 18. Typical HSI accuracy vs. temperature, VDD = 1.65 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . 47
Figure 19. Typical LSI RC frequency vs. VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 20. Typical VIL and VIH vs. VDD (standard I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 21. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 22. Typical pull-up resistance R vs. V with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PU
DD
Figure 23. Typical pull-up current IPU vs. V with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DD
Figure 24. Typ. VOL at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 25. Typ. VOL at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 26. Typ. VOL at VDD = 3.0 V (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 27. Typ. VOL at VDD = 1.8 V (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 28. Typ. VDD - VOH at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 29. Typ. VDD - VOH at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 30. Typical NRST pull-up resistance R vs. V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
PU
DD
Figure 31. Typical NRST pull-up current I vs. V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
pu
DD
Figure 32. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 33. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
(1)
Figure 34. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
(1)
Figure 35. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 36. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 37. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . . 67
(1)
Figure 38. UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 39. LQFP32 - 32-pin low profile quad flat package outline (7 x 7) . . . . . . . . . . . . . . . . . . . . . . 69
(1)
Figure 40. LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
(1)
Figure 41. UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4 x 4) . . . . 70
Figure 42. UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 43. UFQFPN20 3 x 3 mm 0.6 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
(1)
Figure 44. UFQFPN20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 45. TSSOP20 - 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
(1)
Figure 46. TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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List of figures
STM8L101xx
Figure 47. STM8L101xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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STM8L101xx
Introduction
1
Introduction
This datasheet provides the STM8L101xx pinout, ordering information, mechanical and
electrical device characteristics.
For complete information on the STM8L101xx microcontroller memory, registers and
peripherals, please refer to the STM8L reference manual.
The STM8L101xx devices are members of the STM8L low power 8-bit family. They are
referred to as low-density devices in the STM8L101xx microcontroller family reference
manual (RM0013) and in the STM8L Flash programming manual (PM0054).
All devices of the SM8L product line provide the following benefits:
●
Reduced system cost
–
Up to 8 Kbytes of low-density embedded Flash program memory including up to
2 Kbytes of data EEPROM
–
–
High system integration level with internal clock oscillators and watchdogs.
Smaller battery and cheaper power supplies.
●
Low power consumption and advanced features
–
–
–
Up to 16 MIPS at 16 MHz CPU clock frequency
Less than 150 µA/MH, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode
Clock gated system and optimized power management
●
●
Short development cycles
–
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals.
–
Full documentation and a wide choice of development tools
Product longevity
–
Advanced core and peripherals made in a state-of-the art technology
Product family operating from 1.65 V to 3.6 V supply
–
2
Description
The STM8L101xx low power family features the enhanced STM8 CPU core providing
increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of
a CISC architecture with improved code density, a 24-bit linear addressing space and an
optimized architecture for low power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive in-application debugging and ultrafast Flash programming.
All STM8L101xx microcontrollers feature low power low-voltage single-supply program
Flash memory. The 8-Kbyte devices embed data EEPROM.
The STM8L101xx low power family is based on a generic set of state-of-the-art peripherals.
The modular design of the peripheral set allows the same peripherals to be found in different
ST microcontroller families including 32-bit families. This makes any transition to a different
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Description
STM8L101xx
family very easy, and simplified even more by the use of a common set of development
tools.
All STM8L low power products are based on the same architecture with the same memory
mapping and a coherent pinout.
Table 2.
Device features
Features
STM8L101xx
8 Kbytes of Flash program
memory including up to
2 Kbytes of Data EEPROM
2 Kbytes of Flash program
memory
4 Kbytes of Flash program
memory
Flash
RAM
1.5 Kbytes
Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep,
Serial peripheral interface (SPI), Inter-integrated circuit (I²C),
Universal synchronous / asynchronous receiver / transmitter (USART),
2 comparators, Infrared (IR) interface
Peripheral functions
Timers
Two 16-bit timers, one 8-bit timer
1.65 to 3.6 V
Operating voltage
-40 to +85 °C or
Operating temperature
-40 to +85 °C
-40 to +125 °C
UFQFPN28 4x4
UFQFPN28 4x 4
UFQFPN20 3x3
UFQFPN32
LQFP32
Packages
UFQFPN20 3x3
UFQFPN20 3x3
TSSOP20 4.4 x 6.4
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Product overview
3
Product overview
Figure 1.
STM8L101xx device block diagram
@VDD
VDD18
Power
V
V
=1.65 V
to 3.6 V
DD
SS
16 MHz int RC
38 kHz int RC
Clock
controller
Volt. reg.
Clocks
to core and
peripherals
NRST
Reset
POR/PDR
STM8
Core
up to 16 MHz
Up to 8 Kbytes
Flash memory
(including
up to 2 Kbytes
data EEPROM)
Nested interrupt
controller
up to 29 external
interrupts
1.5 Kbytes
SRAM
RX, TX, CK
SDA, SCL
Debug module
(SWIM)
USART
SWIM
I²C1
multimaster
Infrared interface
IR_TIM
MOSI, MISO,
SCK, NSS
SPI
PA[6:0]
PB[7:0]
Port A
Port B
Port C
Port D
TIM2_CH[2:1]
TIM2_TRIG
16-bit Timer 2
16-bit Timer 3
8-bit Timer 4
TIM3_CH[2:1]
TIM3_TRIG
PC[6:0]
PD[7:0]
IWDG
COMP1_CH[4:1]
COMP1
COMP2
COMP_REF
AWU
BEEP
Beeper
COMP2_CH[4:1]
Legend:
AWU: Auto-wakeup unit
Int. RC: internal RC oscillator
I²C: Inter-integrated circuit multimaster interface
POR/PDR: Power on reset / power down reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous / asynchronous receiver / transmitter
IWDG: Independent watchdog
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Product overview
STM8L101xx
3.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It features 21 internal registers, 20 addressing modes including indexed, indirect and relative
addressing, and 80 instructions.
3.2
Development tools
Development tools for the STM8 microcontrollers include:
●
The STice emulation system offering tracing and code profiling
●
The STVD high-level language debugger including C compiler, assembler and
integrated development environment
●
The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
3.3
3.4
Single wire data interface (SWIM) and debug module
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in real-
time by means of shadow registers.
Interrupt controller
The STM8L101xx features a nested vectored interrupt controller:
●
●
●
●
Nested interrupts with 3 software priority levels
26 interrupt vectors with hardware priority
Up to 29 external interrupt sources on 10 vectors
Trap and reset interrupts
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STM8L101xx
Product overview
3.5
Memory
The STM8L101xx devices have the following main features:
●
1.5 Kbytes of RAM
●
The EEPROM is divided into two memory arrays (see the STM8L reference manual for
details on the memory mapping):
–
Up to 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes
of data EEPROM. Data EEPROM and Flash program areas can be write protected
independently by using the memory access security mechanism (MASS).
–
64 option bytes (one block) of which 5 bytes are already used for the device.
Error correction code is implemented on the EEPROM.
3.6
Low power modes
To minimize power consumption, the product features three low power modes:
●
Wait mode: CPU clock stopped, selected peripherals at full clock speed.
●
Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup
time is controlled by the AWU unit.
●
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
Wakeup is triggered by an external interrupt.
3.7
3.8
Voltage regulators
The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power
supply for the core and peripherals.
This regulator has two different modes: main voltage regulator mode (MVR) and low power
voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system
automatically switches from the MVR to the LPVR in order to reduce current consumption.
Clock control
The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock
to the core and the peripherals and to manage clock gating for low power modes. This
system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a
programmable prescaler.
In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog
(IWDG) and Auto-wakeup unit (AWU).
3.9
Independent watchdog
The independent watchdog (IWDG) peripheral can be used to resolve processor
malfunctions due to hardware or software failures.
It is clocked by the 38 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure.
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Product overview
STM8L101xx
3.10
3.11
Auto-wakeup counter
The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode.
General purpose and basic timers
STM8L101xx devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one
8-bit basic timer (TIM4).
16-bit general purpose timers
The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable
prescaler. They perform a wide range of functions, including:
●
●
●
●
●
Time base generation
Measuring the pulse lengths of input signals (input capture)
Generating output waveforms (output compare, PWM and One pulse mode)
Interrupt capability on various events (capture, compare, overflow, break, trigger)
Synchronization with other timers or external signals (external clock, reset, trigger and
enable)
8-bit basic timer
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer overflow.
3.12
3.13
Beeper
The STM8L101xx devices include a beeper function used to generate a beep signal in the
range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz.
Infrared (IR) interface
The STM8L101xx devices contain an infrared interface which can be used with an IR LED
for remote control functions. Two timer output compare channels are used to generate the
infrared remote control signals.
3.14
Comparators
The STM8L101xx features two zero-crossing comparators (COMP1 and COMP2) sharing
the same current bias and voltage reference. The voltage reference can be internal
(comparison with ground) or external (comparison to a reference pin voltage).
Each comparator is connected to 4 channels, which can be used to generate interrupt, timer
input capture or timer break. Their polarity can be inverted.
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STM8L101xx
Product overview
3.15
USART
The USART interface (USART) allows full duplex, asynchronous communications with
external devices requiring an industry standard NRZ asynchronous serial data format. It
offers a very wide range of baud rates.
3.16
SPI
The serial peripheral interface (SPI) provides half/ full duplex synchronous serial
communication with external devices. It can be configured as the master and in this case it
provides the communication clock (SCK) to the external slave device. The interface can also
operate in multi-master configuration.
3.17
I²C
The inter-integrated circuit (I2C) bus interface is designed to serve as an interface between
2
the microcontroller and the serial I C bus. It provides multi-master capability, and controls all
I²C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast
speed modes.
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Pin description
STM8L101xx
4
Pin description
Figure 2.
Standard 20-pin UFQFPN package pinout
20 19 18 17 16
NRST / PA1 (HS)
PA2 (HS)
15
14
13
1
2
3
4
5
PC0 / I²C_SDA
PB7 (HS) / SPI_MISO
PB6 (HS) / SPI_MOSI
PB5 (HS) / SPI_SCK
PB4 (HS) / SPI_NSS
PA3 (HS)
V
SS
12
11
V
DD
6
7
8
9
10
1. HS corresponds to 20 mA high sink/source capability.
2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the
STM8L reference manual (RM0013).
Note:
The COMP_REF pin is not available in this standard 20-pin UFQFPN package. It is available
on Port A6 in the 20-pin UFQFPN package pinout for STM8L101F1U6ATR,
STM8L101F2U6ATR and STM8L101F3U6ATR part numbers (Figure 3 on page 15).
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STM8L101xx
Figure 3.
Pin description
20-pin UFQFPN package pinout for STM8L101F1U6ATR,
STM8L101F2U6ATR and STM8L101F3U6ATR part numbers
20 19 18 17 16
NRST / PA1 (HS)
PA2 (HS)
15
14
13
1
2
3
4
5
PC0 / I²C_SDA
PB7 (HS) / SPI_MISO
PB6 (HS) / SPI_MOSI
PB5 (HS) / SPI_SCK
PB4 (HS) / SPI_NSS
PA6 (HS) / COMP_REF
V
SS
12
11
V
DD
6
7
8
9
10
1. Please refer to the warning below.
2. HS corresponds to 20 mA high sink/source capability.
3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the
STM8L reference manual (RM0013).
Warning: For the STM8L101F1U6ATR, STM8L101F2U6ATR and
STM8L101F3U6ATR part numbers (devices with COMP_REF
pin), all ports available on 32-pin packages must be
considered as active ports. To avoid spurious effects, you
have to configure them as input pull-up. A small increase in
consumption (typ. < 300 µA) may occur during the power up
and reset phase until these ports are properly configured.
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Pin description
Figure 4.
STM8L101xx
20-pin TSSOP package pinout
PC3 (HS) / USART_TX
1
2
20
19
PC2 (HS) / USART_RX
PC1 / I²C_SCL
PC4 (HS) / USART_CK/ CCO
PA0 (HS) / SWIM / BEEP / IR_TIM
18
17
16
15
3
4
5
6
PC0 / I²C_SDA
NRST / PA1 (HS)
PA2 (HS)
PB7 (HS) / SPI_MISO
PB6 (HS) / SPI_MOSI
PB5 (HS) / SPI_SCK
PA3 (HS)
V
SS
7
14 PB4 (HS) / SPI_NSS
V
DD
8
13
12
11
PB3 (HS) /TIM2_TRIG /COMP2_CH2
PD0 (HS) / TIM3_CH2 / COMP1_CH3
PB0 (HS) / TIM2_CH1 / COMP1_CH1
9
PB2 (HS) / TIM2_CH2 / COMP2_CH1
PB1 (HS) / TIM3_CH1 / COMP1_CH2
10
1. HS corresponds to 20 mA high sink/source capability.
2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the
STM8L reference manual (RM0013).
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STM8L101xx
Figure 5.
Pin description
Standard 28-pin UFQFPN package pinout
28 27 26 25 24
23
22
PC0 / I²C_SDA
PD4 (HS)
21
20
19
18
17
1
2
3
4
NRST / PA1 (HS)
PA2 (HS)
PB7 (HS) / SPI_MISO
PB6 (HS) / SPI_MOSI
PB5 (HS) / SPI_SCK
PB4 (HS) / SPI_NSS
PA3 (HS)
PA4 (HS) / TIM2_BKIN
5
PA5 (HS) / TIM3_BKIN
V
16
15
6
7
SS
PB3 (HS) / TIM2_TRIG / COMP2_CH2
V
DD
8
9
10 11 12
13
14
1. HS corresponds to 20 mA high sink/source capability.
2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the
STM8L reference manual (RM0013).
Note:
The COMP_REF pin is not available in this standard 28-pin UFQFPN package. It is available
on Port A6 in the 28-pin UFQFPN package pinout for STM8L101G3U6ATR and
STM8L101G2U6ATR part numbers (Figure 6 on page 18).
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Pin description
Figure 6.
STM8L101xx
28-pin UFQFPN package pinout for STM8L101G3U6ATR and
STM8L101G2U6ATR part numbers
28 27 26 25 24
23
22
PC0 / I²C_SDA
PD4 (HS)
21
20
19
18
17
1
2
3
4
NRST / PA1 (HS)
PA2 (HS)
PB7 (HS) / SPI_MISO
PB6 (HS) / SPI_MOSI
PB5 (HS) / SPI_SCK
PB4 (HS) / SPI_NSS
PA3 (HS)
PA4 (HS) / TIM2_BKIN
5
PA6 (HS) / COMP_REF
V
16
15
6
7
SS
PB3 (HS) / TIM2_TRIG / COMP2_CH2
V
DD
8
9
10 11 12
13
14
1. HS corresponds to 20 mA high sink/source capability.
2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the
STM8L reference manual (RM0013).
Warning: For the STM8L101G3U6ATR and STM8L101G2U6ATR part
numbers (devices with COMP_REF pin), all ports available on
32-pin packages must be considered as active ports. To avoid
spurious effects, you have to configure them as input pull-up.
A small increase in consumption (typ. < 300 µA) may occur
during the power up and reset phase until these ports are
properly configured.
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STM8L101xx
Figure 7.
Pin description
32-pin package pinout
32 31 30 29 28 27 26 25
24
23
22
PD7 (HS)
1
NRST / PA1 (HS)
PD6 (HS)
PD5 (HS)
PD4 (HS)
2
3
PA2 (HS)
PA3 (HS)
PA4 (HS) / TIM2_BKIN
PA5 (HS) / TIM3_BKIN
21
20
4
5
PB7 (HS) / SPI_MISO
PA6 (HS) / COMP_REF
VSS
19
18
17
PB6 (HS) / SPI_MOSI
PB5 (HS) / SPI_SCK
PB4 (HS) / SPI_NSS
6
7
8
VDD
9
10 11 12 13 14 15 16
1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package.
2. HS corresponds to 20 mA high sink/source capability.
3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the
STM8L reference manual (RM0013).
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Pin description
STM8L101xx
Table 3.
Legend/abbreviation for table 4
Type
I= input, O = output, S = power supply
Input
CM = CMOS
Level
Output
Input
HS = high sink/source (20 mA)
float = floating, wpu = weak pull-up
T = true open drain, OD = open drain, PP = push pull
Port and control
configuration
Output
Bold X (pin state after reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).
Table 4.
STM8L101xx pin description
Pin number
Input
Output
Pin name
Alternate function
1
2
3
-
1
2
-
4
5
6
-
1
2
3
4
5
1
2
3
4
-
1
2
3
4
5
NRST/PA1(2)
PA2
I/O
X
X
X
X
X
HS
HS
HS
HS
HS
X
X
X
X
X
X
X
X
X
X
Reset
PA1
I/O X
I/O X
I/O X
I/O X
X
X
X
X
Port A2
Port A3
PA3
-
PA4/TIM2_BKIN
PA5/TIM3_BKIN
Port A4 Timer 2 - break input
Port A5 Timer 3 - break input
-
-
-
Comparator external
reference
-
3
-
-
5
6
PA6/COMP_REF I/O X
X
X
HS
X
X
Port A6
4
5
4
5
7
8
6
7
6
7
7
8
VSS
VDD
S
S
Ground
Power supply
Timer 3 - channel 2 /
Port D0 Comparator 1 -
channel 3
PD0/TIM3_CH2/
COMP1_CH3
6
-
6
-
9
-
8
9
8
9
9
I/O X
I/O X
X
X
X
X
HS
HS
X
X
X
X
Timer 3 - trigger /
Port D1 Comparator 1 -
channel 4
PD1/TIM3_TRIG/
COMP1_CH4
10
PD2/
COMP2_CH3
Comparator 2 -
Port D2
-
-
-
-
-
-
10 10 11
11 11 12
I/O X
I/O X
X
X
X
X
HS
HS
X
X
X
X
channel 3
PD3/
COMP2_CH4
Comparator 2 -
Port D3
channel 4
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Pin description
Table 4.
STM8L101xx pin description (continued)
Pin number
Input
Output
Pin name
Alternate function
Timer 2 - channel 1 /
Port B0 Comparator 1 -
PB0/TIM2_CH1/
COMP1_CH1 (3)
7
8
9
7
10 12 12 13
11 13 13 14
12 14 14 15
I/O X(3) X(3)
X
X
X
X
HS
HS
HS
HS
X
X
X
X
X
X
X
X
channel 1
Timer 3 - channel 1 /
Port B1 Comparator 1 -
PB1/TIM3_CH1/
COMP1_CH2
8
9
I/O X
I/O X
I/O X
X
X
X
channel 2
Timer 2 - channel 2 /
Port B2 Comparator 2 -
PB2/ TIM2_CH2/
COMP2_CH1/
channel 1
Timer 2 - trigger /
Port B3 Comparator 2 -
channel 2
PB3/TIM2_TRIG/
COMP2_CH2
10 10 13 15 15 16
SPI master/slave
select
11 11 14 16 16 17 PB4/SPI_NSS(3) I/O X(3) X(3)
X
X
X
HS
HS
HS
X
X
X
X
X
X
Port B4
12 12 15 17 17 18 PB5/SPI_SCK
13 13 16 18 18 19 PB6/SPI_MOSI
I/O X
I/O X
X
X
Port B5 SPI clock
SPI master out/ slave
in
Port B6
SPI master in/ slave
out
14 14 17 19 19 20 PB7/SPI_MISO
I/O X
X
X
HS
X
X
Port B7
-
-
-
-
-
-
-
-
-
-
-
-
20 20 21 PD4
I/O X
I/O X
I/O X
I/O X
I/O X
I/O X
X
X
X
X
X
X
X
X
X
X
X
X
HS
HS
HS
HS
X
X
X
X
X
Port D4
-
-
-
-
-
-
22 PD5
23 PD6
24 PD7
X
Port D5
X
Port D6
X
Port D7
15 15 18 21 21 25 PC0/I2C_SDA
16 16 19 22 22 26 PC1/I2C_SCL
T(4)
T(4)
X
Port C0 I2C data
Port C1 I2C clock
Port C2 USART receive
Port C3 USART transmit
17 17 20 23 23 27 PC2/USART_RX I/O X
18 18 1 24 24 28 PC3/USART_TX I/O X
X
X
HS
HS
X
X
X
USART synchronous
Port C4 clock / Configurable
clock output
PC4/USART_CK/
CCO
19 19 2 25 25 29
I/O X
I/O X
X
X
X
X
HS
HS
X
X
X
X
-
-
-
26 26 30 PC5
Port C5
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Pin description
STM8L101xx
Table 4.
STM8L101xx pin description (continued)
Pin number
Input
Output
Pin name
Alternate function
-
-
-
27 27 31 PC6
I/O X
X
X
X
HS
X
X
X
Port C6
Port A0
SWIM input and out-
put /Beep out-
put/Timer Infrared
output
PA0(5)/SWIM/
20 20 3 28 28 32
I/O X
X(5)
HS(6)
X
BEEP/IR_TIM (6)
1. Please refer to the warning below.
2. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1
pin as general purpose output in the STM8L101xx reference manual (RM0013).
3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented).
5. The PA0 pin is in input pull-up during the reset phase and after reset release.
6. High sink LED driver capability available on PA0.
Warning: For the STM8L101F1U6ATR, STM8L101F2U6ATR,
STM8L101F3U6ATR, STM8L101G2U6ATR and
STM8L101G3U6ATR part numbers (devices with COMP_REF
pin), all ports available on 32-pin packages must be
considered as active ports. To avoid spurious effects, you
have to configure them as input pull-up. A small increase in
consumption (typ. < 300 µA) may occur during the power up
and reset phase until these ports are properly configured.
22/81
Doc ID 15275 Rev 11
STM8L101xx
Memory and register map
5
Memory and register map
Figure 8.
Memory map
0x00 0000
RAM
(1.5 Kbytes) (1)
including
Stack
(up to 513 bytes) (1)
0x00 05FF
0x00 0600
Reserved
0x00 47FF
0x00 4800
Option bytes
0x00 48FF
0x 004900
Reserved
Unique ID
0x 004924
0x 004925
0x 004930
0x 004931
Reserved
0x00 49FF
0x00 5000
GPIO and peripheral registers(2)
0x00 57FF
0x00 5800
Reserved
0x00 7EFF
0x00 7F00
CPU/SWIM/Debug/ITC
Registers
0x00 7FFF
0x00 8000
0x00 807F
0x00 8080
Interrupt vectors
Low-density
Flash program memory
(up to 8 Kbytes) (1)
including
Data EEPROM
(up to 2 Kbytes)
0x00 9FFF
1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.
2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.
Doc ID 15275 Rev 11
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Memory and register map
STM8L101xx
Table 5.
Flash and RAM boundary addresses
Memory area
Size
Start address
End address
RAM
1.5 Kbytes
0x00 0000
0x00 05FF
2 Kbytes
4 Kbytes
8 Kbytes
0x00 8000
0x00 8000
0x00 8000
0x00 87FF
0x00 8FFF
0x00 9FFF
Flash program memory
Table 6.
Address
I/O Port hardware register map
Reset
status
Block
Register label
Register name
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0xxx
0x00
0x00
0x00
0x00
0xxx
0x00
0x00
0x00
0x00
0xxx
0x00
0x00
0x00
0x00
0xxx
0x00
0x00
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PC_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
Port A control register 2
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
Port B
Port C
Port D
Port B control register 2
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
Port C control register 2
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
Port D control register 2
24/81
Doc ID 15275 Rev 11
STM8L101xx
Memory and register map
Reset
Table 7.
Address
General hardware register map
Block
Register label
Register name
status
0x00 5050
0x00 5051
FLASH_CR1
FLASH_CR2
Flash control register 1
Flash control register 2
0x00
0x00
Flash Program memory unprotection
register
0x00 5052
0x00 5053
0x00 5054
FLASH _PUKR
FLASH _DUKR
FLASH _IAPSR
0x00
0x00
0xX0
Flash
Data EEPROM unprotection register
Flash in-application programming status
register
0x00 5055
to
Reserved area (75 bytes)
0x00 509F
0x00 50A0
0x00 50A1
0x00 50A2
0x00 50A3
0x00 50A4
0x00 50A5
0x00 50A6
0x00 50A7
EXTI_CR1
EXTI_CR2
EXTI_CR3
EXTI_SR1
EXTI_SR2
EXTI_CONF
WFE_CR1
WFE_CR2
External interrupt control register 1
External interrupt control register 2
External interrupt control register 3
External interrupt status register 1
External interrupt status register 2
External interrupt port select register
WFE control register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ITC-EXTI
WFE
WFE control register 2
0x00 50A8
to
Reserved area (8 bytes)
0x00 50AF
0x00 50B0
0x00 50B1
RST_CR
RST_SR
Reset control register
Reset status register
0x00
0x01
RST
0x00 50B2
to
0x00 50BF
Reserved area (14 bytes)
Clock divider register
0x00 50C0
CLK_CKDIVR
0x03
0x00 50C1
to
Reserved area (2 bytes)
0x00 50C2
CLK
0x00 50C3
0x00 50C4
0x00 50C5
CLK_PCKENR
CLK_CCOR
Peripheral clock gating register
Reserved (1 byte)
0x00
0x00
Configurable clock control register
0x00 50C6
to
Reserved area (25 bytes)
0x00 50DF
Doc ID 15275 Rev 11
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Memory and register map
Table 7. General hardware register map (continued)
Address
STM8L101xx
Reset
status
Block
Register label
Register name
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
IWDG prescaler register
IWDG reload register
0xXX
0x00
0xFF
IWDG
0x00 50E3
to
Reserved area (13 bytes)
0x00 50EF
0x00 50F0
0x00 50F1
AWU_CSR
AWU_APR
AWU control/status register
0x00
0x3F
AWU asynchronous prescaler buffer
register
AWU
0x00 50F2
0x00 50F3
AWU_TBR
AWU timebase selection register
BEEP control/status register
0x00
0x1F
BEEP
BEEP_CSR
0x00 50F4
to
Reserved area (268 bytes)
0x00 51FF
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
SPI_CR1
SPI_CR2
SPI_ICR
SPI_SR
SPI_DR
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
0x00
0x00
0x00
0x02
0x00
SPI
SPI data register
0x00 5205
to
Reserved area (11 bytes)
0x00 520F
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
I2C_CR1
I2C_CR2
I2C control register 1
I2C control register 2
0x00
0x00
0x00
0x00
0x00
I2C_FREQR
I2C_OARL
I2C_OARH
I2C frequency register
I2C own address register low
I2C own address register high
Reserved area (1 byte)
I2C data register
I2C_DR
I2C_SR1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
I2C
I2C status register 1
I2C_SR2
I2C status register 2
I2C_SR3
I2C status register 3
I2C_ITR
I2C interrupt control register
I2C Clock control register low
I2C Clock control register high
I2C TRISE register
I2C_CCRL
I2C_CCRH
I2C_TRISER
26/81
Doc ID 15275 Rev 11
STM8L101xx
Table 7.
Address
Memory and register map
Reset
General hardware register map (continued)
Block
Register label
Register name
status
0x00 521E
to
0x00 522F
Reserved area (18 bytes)
USART status register
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
USART_SR
USART_DR
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
USART data register
USART baud rate register 1
USART baud rate register 2
USART control register 1
USART control register 2
USART control register 3
USART control register 4
USART_BRR1
USART_BRR2
USART_CR1
USART_CR2
USART_CR3
USART_CR4
USART
0x00 5238
to
Reserved area (18 bytes)
0x00 524F
Doc ID 15275 Rev 11
27/81
Memory and register map
Table 7. General hardware register map (continued)
Address
STM8L101xx
Reset
status
Block
Register label
Register name
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
TIM2_CR1
TIM2_CR2
TIM2 control register 1
TIM2 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM2_SMCR
TIM2_ETR
TIM2 slave mode control register
TIM2 external trigger register
TIM2 interrupt enable register
TIM2 status register 1
TIM2_IER
TIM2_SR1
TIM2_SR2
TIM2 status register 2
TIM2_EGR
TIM2 event generation register
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCER1
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_BKR
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare enable register 1
TIM2 counter high
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM2
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare register 2 high
TIM2 capture/compare register 2 low
TIM2 break register
TIM2_OISR
TIM2 output idle state register
0x00 5266
to
Reserved area (26 bytes)
0x00 527F
28/81
Doc ID 15275 Rev 11
STM8L101xx
Table 7.
Address
Memory and register map
Reset
General hardware register map (continued)
Block
Register label
Register name
status
0x00 5280
0x00 5281
0x00 5282
0x00 5283
0x00 5284
0x00 5285
0x00 5286
0x00 5287
0x00 5288
0x00 5289
0x00 528A
0x00 528B
0x00 528C
0x00 528D
0x00 528E
0x00 528F
0x00 5290
0x00 5291
0x00 5292
0x00 5293
0x00 5294
0x00 5295
TIM3_CR1
TIM3_CR2
TIM3 control register 1
TIM3 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM3_SMCR
TIM3_ETR
TIM3 slave mode control register
TIM3 external trigger register
TIM3 interrupt enable register
TIM3 status register 1
TIM3_IER
TIM3_SR1
TIM3_SR2
TIM3 status register 2
TIM3_EGR
TIM3 event generation register
TIM3 capture/compare mode register 1
TIM3 capture/compare mode register 2
TIM3 capture/compare enable register 1
TIM3 counter high
TIM3_CCMR1
TIM3_CCMR2
TIM3_CCER1
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM3_BKR
TIM3
TIM3 counter low
TIM3 prescaler register
TIM3 auto-reload register high
TIM3 auto-reload register low
TIM3 capture/compare register 1 high
TIM3 capture/compare register 1 low
TIM3 capture/compare register 2 high
TIM3 capture/compare register 2 low
TIM3 break register
TIM3_OISR
TIM3 output idle state register
0x00 5296
to
Reserved area (74 bytes)
0x00 52DF
0x00 52E0
0x00 52E1
0x00 52E2
0x00 52E3
0x00 52E4
0x00 52E5
0x00 52E6
0x00 52E7
0x00 52E8
TIM4_CR1
TIM4_CR2
TIM4_SMCR
TIM4_IER
TIM4 control register 1
TIM4 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
TIM4 Slave mode control register
TIM4 interrupt enable register
TIM4 Status register 1
TIM4
TIM4_SR1
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 event generation register
TIM4 counter
TIM4 prescaler register
TIM4 auto-reload register low
Doc ID 15275 Rev 11
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Memory and register map
Table 7. General hardware register map (continued)
Address Register name
STM8L101xx
Reset
status
Block
Register label
0x00 52E9
to
Reserved area (23 bytes)
0x00 52FE
0x00 52FF
0x00 5300
0x00 5301
0x00 5302
IRTIM
IR_CR
Infra-red control register
Comparator control register
0x00
0x00
0x00
0x00
COMP_CR
COMP_CSR
COMP_CCS
COMP
Comparator status register
Comparator channel selection register
Table 8.
Address
CPU/SWIM/debug module/interrupt controller registers
Reset
status
Block
Register label
Register name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
A
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x80
0x00
0x00
0x00
0x00
0x00
0x05
0xFF
0x28
PCE
PCH
PCL
XH
CPU
XL
YH
YL
SPH
SPL
CC
Stack pointer low
Condition code register
0x00 7F0B
to
0x00 7F5F
Reserved area (85 bytes)
Global configuration register
Reserved area (15 bytes)
0x00 7F60
CFG
CFG_GCR
0x00
0x00 7F61
0x00 7F6F
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Interrupt Software priority register 1
Interrupt Software priority register 2
Interrupt Software priority register 3
Interrupt Software priority register 4
Interrupt Software priority register 5
Interrupt Software priority register 6
Interrupt Software priority register 7
Interrupt Software priority register 8
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
ITC-SPR
(1)
30/81
Doc ID 15275 Rev 11
STM8L101xx
Table 8.
Address
Memory and register map
CPU/SWIM/debug module/interrupt controller registers (continued)
Reset
status
Block
Register label
Register name
0x00 7F78
to
0x00 7F79
Reserved area (2 bytes)
SWIM control status register
Reserved area (15 bytes)
0x00 7F80
SWIM
SWIM_CSR
0x00
0x00 7F81
to
0x00 7F8F
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
Breakpoint 1 register extended byte
Breakpoint 1 register high byte
Breakpoint 1 register low byte
Breakpoint 2 register extended byte
Breakpoint 2 register high byte
Breakpoint 2 register low byte
Debug module control register 1
Debug module control register 2
Debug module control/status register 1
Debug module control/status register 2
Enable function register
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DM
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
1. Refer to Table 7: General hardware register map on page 25 (addresses 0x00 50A0 to 0x00 50A5) for a
list of external interrupt registers.
Doc ID 15275 Rev 11
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Interrupt vector mapping
STM8L101xx
6
Interrupt vector mapping
Table 9.
Interrupt mapping
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
Wakeup
from Wait
(WFE
Wakeup
from Halt
mode
Vector
IRQ Source
Description
No.
block
address
mode)
mode)
RESET Reset
Yes
-
Yes
-
Yes
-
Yes
-
0x00 8000
0x00 8004
0x00 8008
0x00 800C
TRAP
Software interrupt
Reserved
0
1
FLASH EOP/WR_PG_DIS
Reserved
-
-
-
-
Yes
-
Yes(1)
-
0x00 8010
-0x00 8017
2-3
4
5
AWU
Auto wakeup from Halt
Reserved
-
Yes
-
Yes
-
Yes(1)
-
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8034
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
-
6
EXTIB External interrupt port B
EXTID External interrupt port D
EXTI0 External interrupt 0
EXTI1 External interrupt 1
EXTI2 External interrupt 2
EXTI3 External interrupt 3
EXTI4 External interrupt 4
EXTI5 External interrupt 5
EXTI6 External interrupt 6
EXTI7 External interrupt 7
Reserved
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
7
8
9
10
11
12
13
14
15
16
0x00 804C
-0x00 804F
17
18
19
Reserved
-
-
-
-
-
-
-
-
COMP Comparators
Yes
Yes
Yes(1)
Yes
0x00 8050
0x00 8054
Update
TIM2
/Overflow/Trigger/Break
20
21
22
TIM2
TIM3
TIM3
Capture/Compare
-
-
-
-
-
-
Yes
Yes
Yes
Yes
0x00 8058
0x00 805C
0x00 8060
Update /Overflow/Break
Capture/Compare
Yes(1)
Yes(1)
0x00 8064-
0x00 806B
23-
24
Reserved
-
-
-
-
25
26
TIM4
SPI
Update /Trigger
End of Transfer
-
-
Yes
Yes
Yes(1)
Yes(1)
0x00 806C
0x00 8070
Yes
Yes
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Doc ID 15275 Rev 11
STM8L101xx
Interrupt vector mapping
Wakeup
Table 9.
Interrupt mapping (continued)
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
Wakeup
from Halt
mode
Vector
IRQ Source
from Wait
(WFE
Description
No.
block
address
mode)
mode)
Transmission
USART complete/transmit data
register empty
27
-
-
Yes
Yes(1)
0x00 8074
Receive Register DATA
USART FULL/overrun/idle line
detected/parity error
28
29
-
-
Yes
Yes
Yes(1)
Yes(1)
0x00 8078
0x00 807C
I2C
I2C interrupt(2)
Yes
Yes
1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes
back to WFE mode. Refer to SectionWait for event (WFE) mode in the RM0013 reference manual.
2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
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Option bytes
STM8L101xx
7
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated row of the memory.
All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM
address. See Table 10 for details on option byte addresses.
Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM and Debug
Manual (UM0320) for information on SWIM programming procedures.
Table 10. Option bytes
Option
Option bits
3
Factory
default
setting
Addr.
Option name
byte
No.
7
6
5
4
2
1
0
Read-out
protection
(ROP)
0x4800
OPT1
ROP[7:0]
0x00
0x4807
0x4802
0x4803
-
-
Must be programmed to 0x00
UBC[7:0]
0x00
0x00
0x00
UBC (User
Boot code size)
OPT2
OPT3
DATASIZE
DATASIZE[7:0]
Independent
watchdog
option
OPT4
[1:0]
IWDG
_HALT
IWDG
_HW
0x4808
Reserved
0x00
Table 11. Option byte description
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Refer to Read-out protection section in the STM8L reference manual
(RM0013) for details.
OPT1
UBC[7:0] Size of the user boot code area
0x00: no UBC
0x01-0x02: UBC contains only the interrupt vectors.
0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to
store user boot code. Memory is write protected
...
OPT2
0x7F - Page 0 to 126 reserved for UBC, memory is write protected
Refer to User boot area (UBC) section in the STM8L reference manual
(RM0013) for more details.
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STM8L101xx
Table 11. Option byte description (continued)
Option bytes
DATASIZE[7:0] Size of the data EEPROM area
0x00: no data EEPROM area (1)
0x01: 1 page reserved for data storage from 0x9FC0 to 0x9FFF(1)
0x02: 2 pages reserved for data storage from 0x9F80 to 0x9FFF(1)
... (1)
OPT3
OPT4
0x20: 32 pages reserved for data storage from 0x9800 to 0x9FFF(1)
Refer to Data EEPROM (DATA) section in the STM8L reference manual
(RM0013) for more details.
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent window watchdog reset on Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
1. 0x00 is the only allowed value for 4 Kbyte STM8L101xx devices.
Caution:
After a device reset, read access to the program memory is not guaranteed if address
0x4807 is not programmed to 0x00.
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Unique ID
STM8L101xx
8
Unique ID
STM8L101xx devices feature a 96-bit unique device identifier which provides a reference
number that is unique for any device and in any context. The 96 bits of the identifier can
never be altered by the user.
The unique device identifier can be read in single bytes and may then be concatenated
using a custom algorithm.
The unique device identifier is ideally suited:
●
For use as serial numbers
●
For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software cryptograhic primitives and protocols
before programming the internal memory
●
To activate secure boot processes.
Table 12. Unique ID registers (96 bits)
Unique ID bits
Content
Address
description
7
6
5
4
3
2
1
0
0x4925
0x4926
0x4927
0x4928
0x4929
0x492A
0x492B
0x492C
0x492D
0x492E
0x492F
0x4930
U_ID[7:0]
X co-ordinate on
the wafer
U_ID[15:8]
U_ID[23:16]
U_ID[31:24]
U_ID[39:32]
U_ID[47:40]
U_ID[55:48]
U_ID[63:56]
U_ID[71:64]
U_ID[79:72]
U_ID[87:80]
U_ID[95:88]
Y co-ordinate on
the wafer
Wafer number
Lot number
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Doc ID 15275 Rev 11
STM8L101xx
Electrical parameters
9
Electrical parameters
9.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
9.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Note:
The values given at 85 °C <TA ≤ 125 °C are only valid for suffix 3 versions.
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
9.1.2
9.1.3
9.1.4
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3 V. They are given
only as design guidelines and are not tested.
A
DD
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Figure 9.
Pin loading conditions
STM8L PIN
50 pF
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Electrical parameters
STM8L101xx
9.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 10. Pin input voltage
STM8L PIN
V
IN
9.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 13. Voltage characteristics
Symbol
DD- VSS
Ratings
Min
Max
Unit
V
External supply voltage
-0.3
4.0
Input voltage on true open drain pins
(PC0 and PC1)(1)
VSS-0.3
VSS-0.3
VDD + 4.0
4.0
V
VIN
Input voltage on any other pin (2)
see Absolute maximum
ratings (electrical sensitivity)
on page 63
VESD
Electrostatic discharge voltage
1. Positive injection is not possible on these I/Os. VIN maximum must always be respected. IINJ(PIN) must
never be exceeded. A negative injection is induced by VIN<VSS
.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS
.
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STM8L101xx
Electrical parameters
Table 14. Current characteristics
Symbol
Ratings
Max.
Unit
IVDD
IVSS
Total current into VDD power line (source)
Total current out of VSS ground line (sink)
80
80
Output current sunk by IR_TIM pin (with high sink LED
driver capability)
80
IIO
Output current sunk by any other I/O and control pin
Output current sourced by any I/Os and control pin
25
-25
-5
mA
Injected current on true open-drain pins (PC0 and PC1)(1)
Injected current on any other pin (2)
IINJ(PIN)
5
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins) (3)
25
1. Positive injection is not possible on these I/Os. VIN maximum must always be respected. IINJ(PIN) must
never be exceeded. A negative injection is induced by VIN<VSS
.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS
.
3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 15. Thermal characteristics
Symbol
Ratings
Storage temperature range
Maximum junction temperature
Value
Unit
TSTG
TJ
-65 to +150
150
° C
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Electrical parameters
STM8L101xx
9.3
Operating conditions
Subject to general operating conditions for V and T .
DD
A
9.3.1
General operating conditions
Table 16. General operating conditions
Symbol Parameter
Master clock frequency
Conditions
Min
Max
Unit
(1)
fMASTER
VDD
1.65 V ≤VDD < 3.6 V
2
16
3.6
288
288
250
181
196
83
MHz
V
Standard operating voltage
1.65
LQFP32
UFQFPN32
UFQFPN28
TSSOP20
UFQFPN20
LQFP32
-
-
-
-
-
-
-
-
-
-
Power dissipation at TA= 85 °C
for suffix 6 devices
(2)
PD
mW
UFQFPN32
UFQFPN28
TSSOP20
UFQFPN20
185
62
Power dissipation at TA= 125 °C
for suffix 3 devices
45
49
1.65 V ≤VDD < 3.6 V
−40
−40
- 40
−40
85
(6 suffix version)
TA
Temperature range
°C
1.65 V ≤VDD < 3.6 V
(3 suffix version)
125
105
130
-40 °C ≤TA ≤85 °C
(6 suffix version)
°C
°C
TJ
Junction temperature range
-40 °C ≤TA ≤125 °C
(3 suffix version)
1. fMASTER = fCPU
2. To calculate PDmax(TA) use the formula given in thermal characteristics PDmax=(TJmax -TA)/ΘJA with TJmax in this table and
JA in table “Thermal characteristics”
Θ
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STM8L101xx
Electrical parameters
9.3.2
Power-up / power-down operating conditions
Table 17. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tVDD
VDD rise time rate
20
-
-
1300
-
µs/V
ms
tTEMP
Reset release delay VDD rising
1
Power on reset
threshold
(1)
VPOR
1.35
1.40
-
-
1.65(2)
V
V
Power down reset
threshold
(1)
VPDR
1.60
1. Data based on characterization results, not tested in production.
2. Data guaranteed, each individual device tested in production.
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Electrical parameters
STM8L101xx
9.3.3
Supply current characteristics
Total current consumption
The MCU is placed under the following conditions:
●
All I/O pins in input mode with a static value at V or V (no load)
DD SS
●
All peripherals are disabled except if explicitly mentioned.
Subject to general operating conditions for V and T .
DD
A
(1)
Table 18. Total current consumption in Run mode
Symbol Parameter
Conditions(2)
Typ
Max(3)
Unit
f
f
f
MASTER = 2 MHz
MASTER = 4 MHz
MASTER = 8 MHz
0.39
0.55
0.9
0.6
0.7
Code executed from
RAM
1.2
Supply
current in
fMASTER = 16 MHz
fMASTER = 2 MHz
fMASTER = 4 MHz
fMASTER = 8 MHz
1.6
2.1(6)
IDD (Run)
mA
Run
0.55
0.88
1.5
0.7
mode(4) (5)
1.8
Code executed from
Flash
2.5
fMASTER = 16 MHz
2.7
3.5
1. Based on characterization results, unless otherwise specified.
2. All peripherals off, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU=fMASTER
3. Maximum values are given for TA = −40 to 125 °C.
4. CPU executing typical data processing.
5. An approximate value of IDD(Run) can be given by the following formula:
I
DD(Run) = fMASTER x 150 µA/MHz +215 µA.
6. Data guaranteed, each individual device tested in production.
Figure 11. I
vs. V
f
= 2 MHz
Figure 12. I
vs. V , f = 16 MHz
DD CPU
DD(RUN)
DD, CPU
DD(RUN)
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
0
1.6 1.7 1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VDD [V]
3
3.1 3.2 3.3 3.4 3.5 3.6
2
1.6 1.7 1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VDD [V]
3
3.1 3.2 3.3 3.4 3.5 3.6
ai17018
ai17017
1. Typical current consumption measured with code executed from Flash.
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STM8L101xx
Electrical parameters
(1)
Table 19. Total current consumption in Wait mode
Symbol
Parameter
Conditions
Typ
Max(2)
Unit
fMASTER = 2 MHz
245
300
380
400
450
600
800
Supply
current in
Wait mode
CPU not clocked,
all peripherals off,
HSI internal RC osc.
f
f
MASTER = 4 MHz
MASTER = 8 MHz
IDD (Wait)
µA
fMASTER = 16 MHz 510
1. Based on characterization results, unless otherwise specified.
2. Maximum values are given for TA = -40 to 125 °C.
Figure 13. I
vs. V , f
= 2 MHz
Figure 14. I
vs. V , f
= 16 MHz
DD(WAIT)
DD CPU
DD(WAIT)
DD CPU
600
550
500
450
400
350
300
250
300
250
200
150
100
50
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
0
1.6 1.7 1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VDD [V]
3
3.1 3.2 3.3 3.4 3.5 3.6
200
1.6
2.1
2.6
3.1
3.6
VDD [V]
ai17015
ai17016
1. Typical current consumption measured with code executed from Flash.
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Electrical parameters
STM8L101xx
Table 20. Total current consumption and timing in Halt and Active-halt mode at
(1)(2)
V
= 1.65 V to 3.6 V
DD
Symbol
Parameter
Conditions
Typ Max Unit
TA = -40 °C to 25 °C 0.8
2
μA
μA
μA
μA
μA
TA = 55 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
1
2.5
3.2
7.5
13
Supply current in Active-halt LSI RC osc.
IDD(AH)
1.4
2.9
5.8
mode
(at 37 kHz)
Supply current during
IDD(WUFAH) wakeup time from Active-halt
mode
2
-
mA
Wakeup time from Active-
halt mode to Run mode
(3)
tWU(AH)
fCPU= 16 MHz
4
6.5
μs
TA = -40 °C to 25 °C
TA = 55 °C
0.35 1.2(4) μA
0.6
1
1.8
μA
IDD(Halt)
Supply current in Halt mode TA = 85 °C
TA = 105 °C
2.5(4) μA
2.5
6.5
μA
μA
TA = 125 °C
5.4 12(4)
Supply current during
wakeup time from Halt mode
IDD(WUFH)
2
4
-
mA
Wakeup time from Halt mode
fCPU = 16 MHz
(3)
tWU(Halt)
6.5
μs
to Run mode
1.
TA = -40 to 125 °C, no floating I/O, unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. Measured from interrupt event to interrupt vector fetch.
To get tWU for another CPU frequency use tWU(FREQ) = tWU(16 MHz) + 1.5 (TFREQ-T16 MHz).
The first word of interrupt routine is fetched 5 CPU cycles after tWU
.
4. Data guaranteed, each individual device tested in production.
Figure 15. Typ. I
vs. V
f
= 2 MHz and 16 MHz
DD(Halt)
DD, CPU
7
6
5
4
3
2
1
0
-40°C
25°C
85°C
125°C
1.6
2.1
2.6
3.1
3.6
VDD [V]
ai17014b
1. Typical current consumption measured with code executed from Flash.
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STM8L101xx
Electrical parameters
Current consumption of on-chip peripherals
Measurement made for f
= from 2 MHz to 16 MHz
MASTER
Table 21. Peripheral current consumption
Symbol
Parameter
TIM2 supply current (1)
Typ. VDD = 3.0 V
Unit
IDD(TIM2)
IDD(TIM3)
IDD(TIM4)
IDD(USART)
IDD(SPI)
9
9
TIM3 supply current (1)
TIM4 timer supply current (1)
USART supply current (2)
SPI supply current (2)
4
µA/MHz
7
4
IDD(I²C1)
I2C supply current (2)
4
IDD(COMP)
Comparator supply current (2)
20
µA
1. Data based on a differential IDD measurement between all peripherals off and a timer counter running at
16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pin toggling. Not tested in
production.
2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in
both cases. No I/O pin toggling. Not tested in production.
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Electrical parameters
STM8L101xx
9.3.4
Clock and timing characteristics
Internal clock sources
Subject to general operating conditions for V and T .
DD
A
High speed internal RC oscillator (HSI)
(1)
Table 22. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
VDD = 3.0 V
VDD = 3.0 V, TA = 25 °C
DD = 3.0 V, -10 °C ≤TA ≤ 85 °C
Min
Typ
Max
Unit
fHSI
-
16
-
1
MHz
%
-1
V
-2.5
-4.5
-1.5(2)
-2(2)
2
%
VDD = 3.0 V, -10 °C ≤TA ≤ 125 °C
VDD = 3.0 V, 0 °C ≤TA ≤ 55 °C
2
%
Accuracy of HSI
oscillator
(factory calibrated)
ACCHSI
1.5(2)
2(2)
%
VDD = 3.0 V, -10 °C ≤TA ≤ 70 °C
%
1.65 V ≤ VDD ≤ 3.6 V,
-40 °C ≤ TA ≤125 °C
-4.5(2)
3(2)
%
HSI oscillator power
consumption
IDD(HSI)
-
70
100(2)
µA
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
Figure 16. Typical HSI frequency vs. V
DD
17
16.8
16.6
16.4
16.2
16
-40°C
25°C
85°C
125°C
15.8
15.6
15.4
15.2
15
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85
VDD [V]
3
3.15 3.3 3.45 3.6
ai17013
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STM8L101xx
Figure 17. Typical HSI accuracy vs. temperature, V = 3 V
Electrical parameters
DD
3.5%
3.0%
2.5%
2.0%
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
-2.5%
-3.0%
-3.5%
-4.0%
-4.5%
-5.0%
3V min
3V typical
3V max
-50 -40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140
ai17021
Temperature (°C)
Figure 18. Typical HSI accuracy vs. temperature, V = 1.65 V to 3.6 V
DD
3.5%
Min 1.65V-3.6V
3.0%
Max 1.65V-3.6V
2.5%
3V typical
2.0%
1.5%
1.0%
0.5%
0.0%
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
-0.5%
-1.0%
-1.5%
-2.0%
-2.5%
-3.0%
-3.5%
-4.0%
-4.5%
-5.0%
ai17019
Temperature (°C)
Low speed internal RC oscillator (LSI)
(1)
Table 23. LSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max
Unit
fLSI
26
38
56
kHz
LSI oscillator frequency
drift(2)
fdrift(LSI)
0 °C ≤TA ≤ 85 °C
-12
-
11
%
1.
VDD = 1.65 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified.
2. For each individual part, this value is the frequency drift from the initial measured frequency.
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Electrical parameters
Figure 19. Typical LSI RC frequency vs. V
STM8L101xx
DD
45
43
41
39
37
35
33
31
29
27
25
-40°C
25°C
85°C
125°C
1.6
2.1
2.6
VDD [V]
3.1
3.6
ai17012b
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Electrical parameters
9.3.5
Memory characteristics
T = -40 to 125 °C unless otherwise specified.
A
Table 24. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM
Data retention mode (1)
Halt mode (or Reset)
1.4
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.
Flash memory
Table 25. Flash program memory
Max
Symbol
Parameter
Conditions
Min
Typ
Unit
(1)
Operating voltage
(all modes, read/write/erase)
VDD
fMASTER = 16 MHz
1.65
-
3.6
V
Programming time for 1- or 64-byte (block)
erase/write cycles (on programmed byte)
-
-
6
3
-
-
ms
ms
tprog
Programming time for 1- to 64-byte (block)
write cycles (on erased byte)
TA=+25 °C, VDD = 3.0 V
TA=+25 °C, VDD = 1.8 V
-
-
-
-
Iprog
Programming/ erasing consumption
0.7
-
mA
Data retention (program memory)
after 10k erase/write cycles
at TA = +85 °C
T
T
T
RET = 55 °C
RET = 55 °C
RET = 85 °C
20(1)
20(1)
1(1)
-
-
-
Data retention (data memory)
after 10k erase/write cycles
at TA = +85 °C
tRET
-
-
years
Data retention (data memory)
after 300k erase/write cycles
at TA = +125 °C
Erase/write cycles (program memory)
Erase/write cycles (data memory)
See notes (1)(2)
See notes (1)(3)
10(1)
-
-
-
-
NRW
kcycles
300(1)(4)
1. Data based on characterization results, not tested in production.
2. Retention guaranteed after cycling is 10 years at 55 °C.
3. Retention guaranteed after cycling is 1 year at 55 °C.
4. Data based on characterization performed on the whole data memory (2 Kbytes).
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Electrical parameters
STM8L101xx
9.3.6
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V and T unless otherwise specified. All
DD
A
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
(1)
Table 26. I/O static characteristics
Symbol
Parameter
Conditions
Standard I/Os
Min
Typ
Max
Unit
VSS-0.3
VSS-0.3
-
-
-
0.3 x VDD
0.3 x VDD
VDD+0.3
VIL
Input low level voltage(2)
V
True open drain I/Os
Standard I/Os
0.70 x VDD
True open drain I/Os
5.2
5.5
VIH
Input high level voltage (2)
VDD < 2 V
V
0.70 x VDD
-
True open drain I/Os
VDD ≥ 2 V
Standard I/Os
-
-
200
250
-
-
Vhys
Schmitt trigger voltage hysteresis (3)
mV
True open drain I/Os
VSS≤VIN≤VDD
Standard I/Os
-
-
-
-
50 (5)
VSS≤VIN≤VDD
True open drain I/Os
200(5)
Ilkg
Input leakage current (4)
nA
VSS≤VIN≤VDD
PA0 with high sink LED
driver capability
-
-
200(5)
RPU
Weak pull-up equivalent resistor(6)
I/O pin capacitance
VIN=VSS
30
-
45
5
60
-
kΩ
(7)
CIO
pF
1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in
Figure 22).
7. Data guaranteed by Design, not tested in production.
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Doc ID 15275 Rev 11
STM8L101xx
Figure 20. Typical V and V vs. V (standard I/Os)
Electrical parameters
IL
IH
DD
-40°C
3
25°C
85°C
2.5
125°C
2
1.5
1
0.5
0
2.1
3.1
3.6
1.6
2.6
VDD [V]
ai17011
Figure 21. Typical V and V vs. V (true open drain I/Os)
IL
IH
DD
3
2.5
2
-40°C
25°C
85°C
125°C
1.5
1
0.5
0
1.6
2.1
2.6
VDD [V]
3.1
3.6
ai17010
Figure 22. Typical pull-up resistance R vs. V with V =V
SS
PU
DD
IN
60
55
50
45
40
35
30
-40°C
25°C
85°C
125°C
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85
VDD [V]
3
3.15 3.3 3.45 3.6
ai17009
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Electrical parameters
STM8L101xx
Figure 23. Typical pull-up current I vs. V with V =V
SS
PU
DD
IN
120
100
80
60
40
20
0
-40°C
25°C
85°C
125°C
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85
VDD [V]
3
3.15 3.3 3.45 3.6
ai17008
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STM8L101xx
Electrical parameters
Output driving current
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 27. Output driving current (standard ports)
I/O
Symbol
Parameter
Conditions
Min
Max Unit
Type
IIO = +2 mA,
VDD = 3.0 V
-
0.45
V
V
V
V
V
V
Output low level voltage for an I/O pin
IIO = +2 mA,
VDD = 1.8 V
(1)
VOL
-
0.45
IIO = +10 mA,
VDD = 3.0 V
-
1.2
IIO = -2 mA,
VDD = 3.0 V
V
DD-0.45
-
-
-
IIO = -1 mA,
VDD = 1.8 V
(2)
VOH
Output high level voltage for an I/O pin
VDD-0.45
VDD-1.2
IIO = -10 mA,
VDD = 3.0 V
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 14 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD
.
Table 28. Output driving current (true open drain ports)
I/O
Symbol
Parameter
Conditions
Min
Max Unit
Type
I
IO = +3 mA,
-
-
0.45
0.45
V
V
VDD = 3.0 V
(1)
VOL
Output low level voltage for an I/O pin
IIO = +1 mA,
VDD = 1.8 V
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS
.
Table 29. Output driving current (PA0 with high sink LED driver capability)
I/O
Symbol
Parameter
Conditions
Min
Max Unit
Type
IIO = +20 mA,
VDD = 2.0 V
(1)
VOL
Output low level voltage for an I/O pin
-
0.9
V
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS
.
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Electrical parameters
STM8L101xx
Figure 24. Typ. V at V = 3.0 V (standard
Figure 25. Typ. V at V = 1.8 V (standard
OL DD
OL
DD
ports)
ports)
-40°C
25°C
85°C
125°C
0.5
0.4
0.3
0.2
0.1
0
1.5
1.25
1
-40°C
25°C
85°C
125°C
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
0
5
10
15
20
25
IOL [mA]
IOL [mA]
ai17004
ai17005
Figure 26. Typ. V at V = 3.0 V (true open Figure 27. Typ. V at V = 1.8 V (true open
OL
DD
OL
DD
drain ports)
drain ports)
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
0
1
2
3
4
5
6
0
0.5
1
1.5
2
2.5
3
IOL [mA]
IOL [mA]
ai17002
ai17003
Figure 28. Typ. V - V at V = 3.0 V
Figure 29. Typ. V - V at V = 1.8 V
DD OH DD
DD
OH
DD
(standard ports)
(standard ports)
2
1.75
1.5
1.25
1
-40°C
25°C
85°C
125°C
0.4
0.3
0.2
0.1
0
-40°C
25°C
85°C
125°C
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
16
18
20
22
24
0
1
2
3
4
5
6
IOH [mA]
IOH [mA]
ai17001
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STM8L101xx
Electrical parameters
NRST pin
The NRST pin input driver is CMOS. A permanent pull-up is present.
has the same value as R (see Table 26 on page 50).
R
PU(NRST)
PU
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 30. NRST pin characteristics
Symbol Parameter
Conditions
Min Typ (1)
Max
Unit
VIL(NRST) NRST input low level voltage (1)
VIH(NRST) NRST input high level voltage (1)
VOL(NRST) NRST output low level voltage
VSS
1.4
-
-
-
0.8
VDD
V
IOL = 2 mA
-
VDD-0.8
RPU(NRST) NRST pull-up equivalent resistor (2)
VF(NRST) NRST input filtered pulse (3)
tOP(NRST) NRST output pulse width
30
-
45
-
60
50
-
kΩ
ns
ns
ns
20
300
-
VNF(NRST) NRST input not filtered pulse (3)
-
-
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor (Figure 30). Corresponding IPU current
characteristics are described in Figure 31.
3. Data guaranteed by design, not tested in production.
Figure 30. Typical NRST pull-up resistance R vs. V
PU
DD
60
-40°C
25°C
55
85°C
125°C
50
45
40
35
30
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85
VDD [V]
3
3.15 3.3 3.45 3.6
ai17007
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Electrical parameters
Figure 31. Typical NRST pull-up current I vs. V
STM8L101xx
pu
DD
120
100
80
60
40
20
0
-40°C
25°C
85°C
125°C
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85
VDD [V]
3
3.15 3.3 3.45 3.6
ai17006
The reset network shown in Figure 32 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V max. level specified in
IL
Table 30. Otherwise the reset is not taken into account internally. For power consumption-
sensitive applications, the capacity of the external reset capacitor can be reduced to limit the
charge/discharge current. If the NRST signal is used to reset the external circuitry, the user
must pay attention to the charge/discharge time of the external capacitor to meet the reset
timing conditions of the external devices. The minimum recommended capacity is 10 nF
Figure 32. Recommended NRST pin configuration
V
DD
RPU
EXTERNAL
RESET
CIRCUIT
RSTIN
INTERNAL RESET
STM8L
Filter
0.1μF
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STM8L101xx
Electrical parameters
9.3.7
Communication interfaces
Serial peripheral interface (SPI)
Unless otherwise specified, the parameters given in Table 31 are derived from tests
performed under ambient temperature, f frequency and V supply voltage
MASTER
DD
conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 31. SPI characteristics
Symbol
Parameter
Conditions(1)
Master mode
Slave mode
Min
Max
Unit
0
0
8
8
fSCK
1/tc(SCK)
SPI clock frequency
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF
-
30
(2)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 x TMASTER
80
-
-
(2)
th(NSS)
(2)
tw(SCKH)
tw(SCKL)
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
SCK high and low time
Data input setup time
105
145
(2)
(2)
Master mode
30
3
-
tsu(MI)
tsu(SI)
(2)
Slave mode
-
(2)
Master mode
15
0
-
th(MI)
th(SI)
Data input hold time
ns
(2)
Slave mode
-
(2)(3)
ta(SO)
Data output access time
Data output disable time
Data output valid time
Slave mode
-
3x TMASTER
(2)(4)
tdis(SO)
Slave mode
30
-
-
(2)
(2)
(2)
(2)
tv(SO)
tv(MO)
th(SO)
th(MO)
Slave mode (after enable edge)
60
Master mode
(after enable edge)
Data output valid time
-
20
-
Slave mode (after enable edge)
15
1
Data output hold time
Master mode
(after enable edge)
-
1. Parameters are given by selecting 10-MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.
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Electrical parameters
STM8L101xx
Figure 33. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
t
t
h(NSS)
SU(NSS)
c(SCK)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
dis(SO)
v(SO)
r(SCK)
f(SCK)
h(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134
(1)
Figure 34. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM8L101xx
Electrical parameters
(1)
Figure 35. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
BIT6 IN
LSB IN
t
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical parameters
STM8L101xx
Inter IC control interface (I2C)
Subject to general operating conditions for V
,
, and T unless otherwise specified.
f
DD
A
MASTER
2
2
The STM8L I C interface meets the requirements of the Standard I C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 32. I2C characteristics
Standard mode
Fast mode I2C(1)
I2C
Symbol
Parameter
Unit
Min(2)
Max (2)
Min (2)
Max (2)
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
4.7
4.0
-
-
-
-
1.3
0.6
-
μs
-
250
0 (3)
100
0 (4)
-
th(SDA)
SDA data hold time
900 (3)
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
START condition hold time
4.0
4.7
4.0
4.7
-
-
0.6
0.6
0.6
1.3
-
-
μs
Repeated START condition setup
time
tsu(STA)
-
-
tsu(STO) STOP condition setup time
-
-
-
-
μs
μs
pF
STOP to START condition time
tw(STO:STA)
(bus free)
Cb
Capacitive load for each bus line
400
400
1. fSCK must be at least 8 MHz to achieve max fast I2C speed (400 kHz).
Data based on standard I2C protocol requirement, not tested in production.
2.
The maximum hold time of the START condition has only to be met if the interface does not stretch the low
period of SCL signal.
3.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
).
Note:
For speeds around 200 kHz, achieved speed can have 5% tolerance
For other speed ranges, achieved speed can have 2% tolerance
The above variations depend on the accuracy of the external components used.
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STM8L101xx
Figure 36.
Electrical parameters
Typical application with I2C bus and timing diagram1)
V
V
DD
DD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDA
SCL
2
I C BUS
STM8L
REPEATED START
START
t
t
su(STA)
w(STO:STA)
START
SDA
t
t
r(SDA)
f(SDA)
STOP
t
t
h(SDA)
su(SDA)
SCL
t
t
t
t
t
su(STO)
t
h(STA)
w(SCLH)
w(SCLL)
r(SCL)
f(SCL)
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
9.3.8
Comparator characteristics
Table 33. Comparator characteristics
Symbol
Parameter
Conditions
Min (1)
Typ
Max(1)
Unit
VIN(COMP_REF)
VIN
Comparator external reference
Comparator input voltage range
Comparator offset error
-0.1
-
-
-
-
-
VDD-1.25
VDD+0.25
20
V
V
-0.25
(2)
Voffset
-
-
-
mV
µs
µA
tSTART
Startup time (after BIAS_EN)
Analog comparator consumption
3(1)
25(1)
IDD(COMP)
Analog comparator consumption
during power-down
-
-
-
-
60(1)
nA
µs
100-mV input step
with 5-mV overdrive,
input rise time = 1 ns
(2)
tpropag
Comparator propagation delay
2(1)
1. Data guaranteed by design, not tested in production.
2. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the
comparator and must be avoided:
- Negative injection current on the I/Os close to the comparator inputs
- Switching on I/Os close to the comparator inputs
- Negative injection current on not used comparator input.
- Switching with a high dV/dt on not used comparator input.
These phenomena are even more critical when a big external serial resistor is added on the inputs.
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Electrical parameters
STM8L101xx
9.3.9
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
DD
SS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 34. EMS data
Level/
Class
Symbol
Parameter
Conditions
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
LQFP32, VDD = 3.3 V
3B
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
LQFP32, VDD = 3.3 V, fHSI
LQFP32, VDD = 3.3 V, fHSI/2
3B
4A
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STM8L101xx
Electrical parameters
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
(1)
Table 35. EMI data
Max vs.
Monitored
frequency band
Symbol
Parameter
Conditions
Unit
16 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
-3
-6
-5
1
VDD = 3.6 V,
TA = +25 °C,
LQFP32
conforming to
IEC61967-2
dBμV
SEMI
Peak level
-
1. Not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin).
This test conforms to the JESD22-A114A/A115A standard.
Table 36. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Unit
value (1)
Electrostatic discharge voltage
(human body model)
VESD(HBM)
2000
TA = +25 °C
V
Electrostatic discharge voltage
(charge device model)
VESD(CDM)
500
1. Data based on characterization results, not tested in production.
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Electrical parameters
STM8L101xx
Static latch-up
●
LU: 2 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
Table 37. Electrical sensitivities
Symbol
Parameter
Class
LU
Static latch-up class
II
9.4
Thermal characteristics
The maximum chip junction temperature (T
) must never exceed the values given in
Jmax
Table 16: General operating conditions on page 40.
The maximum chip-junction temperature, T
using the following equation:
, in degrees Celsius, may be calculated
Jmax
T
= T
+ (P
x Θ )
Jmax
Amax
Dmax JA
Where:
●
●
●
●
T
is the maximum ambient temperature in °C
is the package junction-to-ambient thermal resistance in ° C/W
Amax
Θ
JA
P
is the sum of P
and P
(P
= P
+ P
)
I/Omax
Dmax
INTmax
I/Omax
Dmax
INTmax
P
is the product of I and V , expressed in watts. This is the maximum chip
INTmax
DD
DD
internal power.
●
P
represents the maximum power dissipation on output pins
I/Omax
where:
P
= Σ (V *I ) + Σ((V -V *I ),
I/Omax
OL OL
DD OH) OH
taking into account the actual V /I
V
/I of the I/Os at low and high level in
OL OL and OH OH
the application.
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STM8L101xx
Electrical parameters
(1)
Table 38. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
60
°C/W
Thermal resistance junction-ambient
UFQFPN 32 - 5 x 5 mm
25
80
°C/W
°C/W
°C/W
°C/W
Thermal resistance junction-ambient
UFQFPN 28 - 4 x 4 mm
Θ
JA
Thermal resistance junction-ambient
UFQFPN 20 - 3 x 3 mm - 0.6 mm
102
110
Thermal resistance junction-ambient
TSSOP 20
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
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Package characteristics
STM8L101xx
10
Package characteristics
10.1
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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STM8L101xx
Package characteristics
10.2
Package mechanical data
Figure 37. UFQFPN32 - 32-lead ultra thin fine pitch
quad flat no-lead package outline
Figure 38. UFQFPN32 recommended
(1)(4)
footprint
(1)(2)(3)
(5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
b
E
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
A0B8_ME
1. Drawing is not to scale.
2. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-
side pad to PCB ground.
4. Dimensions are in millimeters.
Table 39. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A3
b
0.5
0.55
0.02
0.152
0.23
5.00
3.50
5.00
0.6
0.0197
0
0.0217
0.0008
0.006
0.0236
0.0020
0.00
0.05
0.18
4.90
0.28
5.10
0.0071
0.1929
0.0091
0.1969
0.1378
0.1969
0.0110
0.2008
D
D2
E
4.90
3.40
5.10
3.60
0.1929
0.1339
0.2008
0.1417
E2
e
3.50
0.1378
0.0197
0.500
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Package characteristics
STM8L101xx
Table 39. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5),
package mechanical data (continued)
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
L
0.30
0.40
0.08
0.50
0.0118
0.0157
0.0031
0.0197
ddd
Number of pins
32
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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STM8L101xx
Package characteristics
Figure 39. LQFP32 - 32-pin low profile quad flat
Figure 40. LQFP32 recommended
(1)
(1)(2)
package outline (7 x 7)
Seating
plane
footprint
C
A
A2
24
17
c
16
25
A1
b
0.25 mm
Gage plane
ccc
C
D
K
L
D1
A1
L1
D3
24
17
16
25
32
9
8
1
E3 E1
E
32
9
Pin 1
identification
1
8
5V_FT
e
5V_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 40. LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
1.6
0.15
1.45
0.45
0.2
0.063
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
0.05
1.35
0.3
0.002
0.0531
0.0118
0.0035
0.3465
0.2677
1.4
0.0551
0.0146
0.37
c
0.09
8.8
D
9
7
9.2
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
6.8
7.2
5.6
9
8.8
6.8
9.2
7.2
0.3465
0.2677
0.3622
0.2835
E1
E3
e
7
5.6
0.8
0.6
1
L
0.45
0.0°
0.75
7.0°
0.0177
0.0°
0.0295
7.0°
L1
K
3.5°
ccc
0.1
0.0039
Number of pins
32
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM8L101xx
Figure 41. UFQFPN28 - 28-lead ultra thin fine pitch
quad flat no-lead package outline (4 x 4)
Figure 42. UFQFPN28 recommended
(1)
(1)(2)
footprint
A
ddd
A3
A1
D
e
14
7
1
15
e
b
E
21
L1
L2
28
22
A0B0_ME
1. Drawing is not to scale
2. Dimensions are in millimeters
Table 41. UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4),
package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A3
b
0.5
0
0.55
0.02
0.152
0.25
4
0.6
0.0197
0
0.0217
0.0008
0.0060
0.0098
0.1575
0.1575
0.0197
0.0138
0.0157
0.0031
0.0236
0.002
0.05
0.18
0.3
0.0071
0.0118
D
E
4
e
0.5
L1
L2
ddd
0.25
0.3
0.35
0.4
0.45
0.5
0.0098
0.0118
0.0177
0.0197
0.08
Number of pins
28
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 43. UFQFPN20 3 x 3 mm 0.6 mm package
Figure 44. UFQFPN20 recommended
(1)
(1)(2)
outline
footprint
L1
D
e
ddd
L4
10
11
A3
L2
5
1
e
b
E
15
16
20
L3
A1
A
BJꢀꢁꢂꢃꢂ
A0A5_ME
1. Drawing is not to scale
2. Dimensions are in millimeters
Table 42. UFQFPN20 3 x 3 mm 0.6 mm mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
D
E
2.900
2.900
0.500
0
3.000
3.000
0.550
0.020
0.152
0.500
0.550
0.350
0.150
0.200
0.250
0.050
3.100
3.100
0.600
0.050
0.1181
0.1181
0.0217
0.0008
0.006
A
0.0197
0
0.0236
0.002
A1
A3
e
0.0197
0.0217
0.0138
0.0059
0.0079
0.0098
0.002
L1
L2
L3
L4
b
0.500
0.300
0.600
0.400
0.0197
0.0118
0.0236
0.0157
0.180
0.300
0.0071
0.0118
ddd
1. Values in inches are rounded to 4 decimal digits
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Package characteristics
STM8L101xx
Figure 45. TSSOP20 - 20-lead thin shrink small
Figure 46. TSSOP20 recommended
(1)
(1)(2)
package outline
footprint
D
20
11
c
E1
E
1
10
α
A1
L
A
A2
L1
CP
b
e
TSSOP20-M
BJꢀꢁꢂꢃꢀ
1. Drawing is not to scale
2. Dimensions are in millimeters
Table 43. 20-lead thin shrink small package, mechanical data
mm
inches(1)
Dim.
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.2
0.15
1.05
0.3
0.1
0.2
6.6
6.6
4.5
-
0.0472
0.0059
0.0413
0.0118
0.0039
0.0079
0.2598
0.2598
0.1772
-
0.05
0.8
0.002
0.0315
0.0075
1
0.0394
0.19
CP
c
0.09
6.4
6.2
4.3
-
0.0035
0.252
D
6.5
6.4
4.4
0.65
0.6
1
0.2559
0.252
E
0.2441
0.1693
0.1693
0.1693
E1
e
0.1732
0.0256
0.0236
0.0394
L
0.45
0.75
0.0295
L1
a
0°
8°
0°
8°
Number of pins
20
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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STM8L101xx
Device ordering information
11
Device ordering information
Figure 47. STM8L101xx ordering information scheme
Example:
STM8
L
101
F
3
U
6
A
TR
Product class
STM8 microcontroller
Family type
L = Low power
Sub-family type
101 = sub-family
Pin count
K = 32 pins
G = 28 pins
F = 20 pins
Program memory size
1 = 2 Kbytes
2 = 4 Kbytes
3 = 8 Kbytes
Package
U = UFQFPN
T = LQFP
P = TSSOP
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
COMP_REF availability on UFQFPN20 and UFQFPN28
A = COMP_REF available
Blank = COMP_REF not available
Shipping
TR = Tape and reel
Blank = Tray
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to
you.
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STM8 development tools
STM8L101xx
12
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
12.1
Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition,
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including profiling and coverage to help detect
and eliminate bottlenecks in application execution and dead code when fine tuning an
application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
STice key features
●
●
●
●
●
●
●
Occurrence and time profiling and code coverage (new features)
Program and data trace recording up to 128 KB records
Read/write on the fly of memory during emulation
In-circuit debugging/programming via SWIM protocol
8-bit probe analyzer
Power supply follower managing application voltages between 1.62 to 5.5 V
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements
●
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
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STM8L101xx
STM8 development tools
12.2
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code
is available.
12.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
●
●
●
●
●
●
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
12.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
●
●
●
Cosmic C compiler for STM8 – One free version that outputs up to 32 Kbytes of code
is available. For more information, see www.cosmic-software.com.
Raisonance C compiler for STM8 – One free version that outputs up to 32 Kbytes of
code. For more information, see www.raisonance.com.
STM8 assembler linker – Free assembly toolchain included in the STVD toolset,
which allows you to assemble and link your application source code.
12.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
Doc ID 15275 Rev 11
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Revision history
STM8L101xx
13
Revision history
Table 44. Document revision history
Date
Revision
Changes
19-Dec-2008
1
Initial release.
Added TSSOP28 package
Modified packages on first page
COMPx_OUT pins removed
Added Figure 6: 28-pin TSSOP package pinout on page 17
Modified Section 9: Electrical parameters on page 37.
Updated UBC[7:0] description in Section 7: Option bytes.
Updated low power current consumption on cover page.
Updated Table 13: Voltage characteristics, Table 20: Total current
consumption and timing in Halt and Active-halt mode at VDD = 1.65
V to 3.6 V, Table 26: I/O static characteristics, Table 30: NRST pin
characteristics, and Section 9.3.9: EMC characteristics.
22-Apr-2009
2
Updated PA1/NRST, PC0 and PC1 in Table 4: STM8L101xx pin
description.
Added ECC feature.
Changed internal RC frequency to 38 kHz.
Updated electrical characteristics in Table 16, Table 18, Table 19,
Table 20, Table 22, Table 23, and Table 26.
Corrected title on cover page.
Changed VFQFPN32 to WFQFPN32 and updated Table 39:
UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package
(5 x 5), package mechanical data.
24-Apr-2009
3
Updated Table 13, Table 26, and Table 33.
Replaced WFQFPN20 3 x 3 mm 0.8 mm package by UFQFPN20
3 x 3 mm 0.6 mm package (first page, Table 16: General operating
conditions on page 40, Table 38: Thermal characteristics on
page 65, Section 10.2: Package mechanical data on page 67)
Added one UFQFPN20 version with COMP_REF
Modified Figure 40: LQFP32 recommended footprint(1) on page 69
Added IPROG values in Table 25: Flash program memory on page 49
Updated Table 31: SPI characteristics on page 57
14-May-2009
15-May-2009
4
5
Added STM8L101F3U6ATR part number in Section 4: Pin
description on page 14 and in Figure 47: STM8L101xx ordering
information scheme on page 73
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STM8L101xx
Table 44. Document revision history (continued)
Revision history
Date
Revision
Changes
Removed TSSOP28 package
Modified consumption value on first page
Added BEEP_CSR (address 00 50F3h) in Table 7: General
hardware register map on page 25
TIM2_PSCRL replaced with TIM2_PSCR and CLK_PCKEN
replaced with CLK_PCKENR in Table 7: General hardware register
map on page 25
Added graphs in Section 9: Electrical parameters on page 37
Added tWU(AH) and tWU(Halt) max values in Table 20: Total current
consumption and timing in Halt and Active-halt mode at VDD = 1.65
V to 3.6 V on page 44
Modified Table 20: Total current consumption and timing in Halt and
Active-halt mode at VDD = 1.65 V to 3.6 V on page 44
12-Jun-2009
6
Updated Table 22: HSI oscillator characteristics on page 46,
Table 23: LSI oscillator characteristics on page 47 and Table 24:
RAM and hardware registers on page 49
Modified Table 27: Output driving current (standard ports) on
page 53
Removed note 1 in Table 37: Electrical sensitivities on page 64
Added note to Table 39: UFQFPN32 - 32-lead ultra thin fine pitch
quad flat no-lead package (5 x 5), package mechanical data on
page 67 and
Table 41: UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead
package (4 x 4), package mechanical data on page 70
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Revision history
Table 44. Document revision history (continued)
STM8L101xx
Date
Revision
Changes
Added STM8L101F2U6ATR, STM8L101G2U6ATR and
STM8L101G3U6ATR part numbers
Modified Section 2: Description on page 7.
Modified Table 2: Device features on page 8 (Flash)
Modified Figure 1: STM8L101xx device block diagram on page 9
Modified Section 3.5: Memory on page 11
Added note below Figure 2: Standard 20-pin UFQFPN package
pinout on page 14 and Figure 5: Standard 28-pin UFQFPN package
pinout on page 17
Added Figure 6: 28-pin UFQFPN package pinout for
STM8L101G3U6ATR and STM8L101G2U6ATR part numbers on
page 18
Modified reset values for Px_IDR registers in Table 6: I/O Port
hardware register map on page 24
Added Section 6: Interrupt vector mapping on page 32
Modified OPT numbers in Section 7: Option bytes on page 34
Modified OPT2 in Table 10: Option bytes on page 34
Added Section 8: Unique ID on page 36
TIM_IR pin replaced with IR_TIM pin
07-Sep-2009
7
Modified Table 20: Total current consumption and timing in Halt and
Active-halt mode at VDD = 1.65 V to 3.6 V on page 44
Modified Figure 15: Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and
16 MHz on page 44 and Figure 19: Typical LSI RC frequency vs.
VDD on page 48
Modified Table 27: Output driving current (standard ports) on
page 53
Updated Table 29: Output driving current (PA0 with high sink LED
driver capability) on page 53
Modified : Functional EMS (electromagnetic susceptibility) on
page 62
Modified conditions in Table 35: EMI data on page 63
Added note to Figure 37: UFQFPN32 - 32-lead ultra thin fine pitch
quad flat no-lead package outline (5 x 5) on page 67
Modified Figure 41: UFQFPN28 - 28-lead ultra thin fine pitch quad
flat no-lead package outline (4 x 4)(1) on page 70
Added Figure 44: UFQFPN20 recommended footprint (1) on
page 71
Added Figure 46: TSSOP20 recommended footprint (1) on page 72
CMP replaced with COMP
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STM8L101xx
Table 44. Document revision history (continued)
Revision history
Date
Revision
Changes
Modified status of the document (datasheet instead of preliminary
data)
Replaced WFQFPN32 with UFQFPN32 and WFQFPN28 with
UFQFPN28.
Modified title of the reference manual mentioned in Section 2:
Description on page 7
Added references to “low-density” in Section 2: Description on
page 7, Section 3.5: Memory on page 11 and in Figure 8: Memory
map on page 23
29-Nov-2009
8
Modified Figure 8: Memory map on page 23 (unique ID are added)
Table 7: General hardware register map on page 25: Modified
reserved areas and IR block replaced with IRTIM block
Modified tTEMP in Table 17: Operating conditions at power-up /
power-down on page 41
Modified Table 23: LSI oscillator characteristics on page 47
Modified Table 25: Flash program memory on page 49 (tPROG
)
Modified Table 16: General operating conditions on page 40 and
Table 38: Thermal characteristics on page 65
Modified Section 10: Package characteristics on page 66
Modified Introduction and Description
Modified one reserved area (0x00 5055 to 0x00 509F) in Table 7:
General hardware register map on page 25
ModifiedTable 4: STM8L101xx pin description on page 20: modified
note 2 and removed “wpu” for PC0 and PC1
Removed one note to Table 22: HSI oscillator characteristics on
page 46
Modified first paragraph in Section : NRST pin on page 55
Modified OPT3 description in Table 11: Option byte description on
page 34
18-Jun-2010
9
Added note 5 to Table 18: Total current consumption in Run mode on
page 42
Modified VESD(CDM) in Table 36: ESD absolute maximum ratings on
page 63
Modified Figure 36: Typical application with I2C bus and timing
diagram 1) on page 61
Modified COMP_REF availability information in Figure 47:
STM8L101xx ordering information scheme on page 73
Modified Section 12.2: Software tools on page 75
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Revision history
Table 44. Document revision history (continued)
STM8L101xx
Date
Revision
Changes
Modified Table 3: Legend/abbreviation for table 4 on page 20 and
Table 4: STM8L101xx pin description on page 20 (for PA0, PA1, PB0
and PB4)
21-Jul-2010
10
Modified Table 13: Voltage characteristics on page 38 and Table 14:
Current characteristics on page 39
Modified VIH in Table 26: I/O static characteristics on page 50
Added notes below UFQFPN32 package
Added STM8L101F1 devices:
Modified Table 1: Device summary on page 1, Table 2: Device
features on page 8 and Table 5: Flash and RAM boundary
addresses on page 24
Modified warning below Figure 3 on page 15 and belowTable 4:
STM8L101xx pin description on page 20
14-Oct-2010
11
Modified Figure 47: STM8L101xx ordering information scheme on
page 73
Modifed text above Figure 32: Recommended NRST pin
configuration on page 56
Modified Figure 32 on page 56
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8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1T3
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1T3A
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1T3ATR
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1T3TR
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1T6
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1T6A
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1T6ATR
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1T6TR
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
STM8L101F1U3
8-bit ultralow power microcontroller with up to 8 Kbytes Flash multifunction timers, comparators, USART, SPI, I2C
STMICROELECTR
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