STM32F042F6 [STMICROELECTRONICS]
Reset and power management;
| 型号： | STM32F042F6 |
| 厂家： | 
ST |
| 描述： | Reset and power management |
| 文件： | 总117页 (文件大小：1908K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F042x4 STM32F042x6
ARM®-based 32-bit MCU, up to 32 KB Flash, crystal-less USB
FS 2.0, CAN, 9 timers, ADC and comm. interfaces, 2.0 - 3.6 V
Datasheet - production data
Features
®
®
• Core: ARM 32-bit Cortex -M0 CPU,
frequency up to 48 MHz
UFQFPN48 7x7 mm
UFQFPN32 5x5 mm
UFQFPN28 4x4 mm
LQFP48 7x7 mm
LQFP32 7x7 mm
WLCSP36
2.6x2.7 mm
TSSOP20
6.5x4.4 mm
• Memories
– 16 to 32 Kbytes of Flash memory
• Nine timers
– 6 Kbytes of SRAM with HW parity
– One 16-bit advanced-control timer for six
channel PWM output
• CRC calculation unit
– One 32-bit and four 16-bit timers, with up to
four IC/OC, OCN, usable for IR control
decoding
• Reset and power management
– Digital and I/Os supply: V = 2 V to 3.6 V
DD
– Analog supply: V
= from V to 3.6 V
DD
DDA
– Independent and system watchdog timers
– SysTick timer
– Selected I/Os: V
= 1.65 V to 3.6 V
DDIO2
– Power-on/Power down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop, Standby
• Communication interfaces
2
– One I C interface supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink,
SMBus/PMBus and wakeup
– V
supply for RTC and backup registers
BAT
• Clock management
– Two USARTs supporting master
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
synchronous SPI and modem control, one
with ISO7816 interface, LIN, IrDA, auto
baud rate detection and wakeup feature
– Two SPIs (18 Mbit/s) with 4 to 16
2
programmable bit frames, one with I S
– Internal 48 MHz oscillator with automatic
trimming based on ext. synchronization
interface multiplexed
– CAN interface
• Up to 38 fast I/Os
– USB 2.0 full-speed interface, able to run
from internal 48 MHz oscillator and with
BCD and LPM support
– All mappable on external interrupt vectors
– Up to 24 I/Os with 5 V tolerant capability
and 8 with independent supply V
DDIO2
• HDMI CEC, wakeup on header reception
• Serial wire debug (SWD)
• 96-bit unique ID
• 5-channel DMA controller
• One 12-bit, 1.0 µs ADC (up to 10 channels)
– Conversion range: 0 to 3.6 V
®
• All packages ECOPACK 2
– Separate analog supply: 2.4 V to 3.6 V
Table 1. Device summary
• Up to 14 capacitive sensing channels for
touchkey, linear and rotary touch sensors
Reference
Part number
STM32F042F4, STM32F042G4,
STM32F042K4, STM32F042T4, STM32F042C4
• Calendar RTC with alarm and periodic wakeup
STM32F042x4
from Stop/Standby
STM32F042F6, STM32F042G6,
STM32F042K6, STM32F042T6, STM32F042C6
STM32F042x6
January 2017
DocID025832 Rev 5
1/117
This is information on a product in full production.
www.st.com
Contents
STM32F042x4 STM32F042x6
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
3.4
3.5
ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1
3.5.2
3.5.3
3.5.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
3.7
3.8
3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9.1
3.9.2
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 18
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
REFINT
3.10.3
V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
BAT
3.11 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12.2 General-purpose timers (TIM2, 3, 14, 16, 17) . . . . . . . . . . . . . . . . . . . . 22
3.12.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23
3.14 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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3.15 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25
3.16 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 26
3.17 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.20 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.21 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4
5
6
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 47
Embedded reset and power control block characteristics . . . . . . . . . . . 48
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.18
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
BAT
6.3.19 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.20 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
7.8.1
7.8.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 111
8
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F042x4/x6 device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitive sensing GPIOs available on STM32F042x4/x6 devices . . . . . . . . . . . . . . . . . . 20
No. of capacitive sensing channels available on STM32F042x devices. . . . . . . . . . . . . . . 21
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
Comparison of I C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
Table 9.
STM32F042x4/x6 I C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
STM32F042x4/x6 USART implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F042x4/x6 SPI/I S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM32F042x pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 37
Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 38
Alternate functions selected through GPIOF_AFR registers for port F. . . . . . . . . . . . . . . . 38
STM32F042x4/x6 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . 40
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 48
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Typical and maximum current consumption from V supply at V = 3.6 V . . . . . . . . . . 50
DD
DD
Typical and maximum current consumption from the V
supply . . . . . . . . . . . . . . . . . 52
DDA
Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 53
Typical and maximum current consumption from the V supply. . . . . . . . . . . . . . . . . . . 54
BAT
Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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List of tables
STM32F042x4 STM32F042x6
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
R
max for f
= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
AIN
ADC
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
BAT
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2
I C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2
I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
WLCSP36 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
WLCSP36 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LQFP32 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
TSSOP20 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6/117
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STM32F042x4 STM32F042x6
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LQFP48 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
WLCSP36 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LQFP32 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
UFQFPN32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TSSOP20 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. STM32F042x6 memory map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 65
Figure 20. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 21. HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 22. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 26. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 28. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 29. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 30. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2
Figure 31. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2
Figure 32. I S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 33. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 34. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 35. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 36. UFQFPN48 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 37. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 38. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 39. WLCSP36 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 40. Recommended pad footprint for WLCSP36 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 41. WLCSP36 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 42. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 43. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 44. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 45. UFQFPN32 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 46. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 47. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 48. UFQFPN28 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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8
List of figures
STM32F042x4 STM32F042x6
Figure 49. Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 50. UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 51. TSSOP20 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 52. Recommended footprint for TSSOP20 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 53. TSSOP20 package marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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STM32F042x4 STM32F042x6
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F042x4/x6 microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
®
®
®
For information on the ARM Cortex -M0 core, please refer to the Cortex -M0 Technical
Reference Manual, available from the www.arm.com website.
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27
Description
STM32F042x4 STM32F042x6
2
Description
The STM32F042x4/x6 microcontrollers incorporate the high-performance
®
®
ARM Cortex -M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed
embedded memories (up to 32 Kbytes of Flash memory and 6 Kbytes of SRAM), and an
extensive range of enhanced peripherals and I/Os. All devices offer standard
2
2
communication interfaces (one I C, two SPIs/one I S, one HDMI CEC and two USARTs),
one USB Full-speed device (crystal-less), one CAN, one 12-bit ADC, four 16-bit timers, one
32-bit timer and an advanced-control PWM timer.
The STM32F042x4/x6 microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
The STM32F042x4/x6 microcontrollers include devices in seven different packages ranging
from 20 pins to 48 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included.
These features make the STM32F042x4/x6 microcontrollers suitable for a wide range of
applications such as application control and user interfaces, hand-held equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.
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STM32F042x4 STM32F042x6
Description
STM32F042C
Table 2. STM32F042x4/x6 device features and peripheral counts
STM32F042Fx STM32F042G STM32F042K STM32F042T
16 32 16 32 16 32 16 32
Peripheral
Flash memory (Kbyte)
SRAM (Kbyte)
Advanced
16
32
6
1 (16-bit)
control
Timers
4 (16-bit)
1 (32-bit)
General
purpose
SPI [I2S](1)
I2C
1 [1]
2 [1]
1
2
1
1
1
USART
Comm.
interfaces
CAN
USB
CEC
12-bit ADC
1
1
(number of channels)
(9 ext. + 3 int.)
(10 ext. + 3 int.)
26
28
GPIOs
16
24
11
30
14
38
14
13
14
Capacitive sensing
channels
7
Max. CPU frequency
Operating voltage
48 MHz
2.0 to 3.6 V
Ambient operating temperature: -40°C to 85°C / -40°C to 105°C
Junction temperature: -40°C to 105°C / -40°C to 125°C
Operating temperature
Packages
LQFP32
LQFP48
TSSOP20
UQFPN28
WLCSP36
UQFPN32
UFQFPN48
1. The SPI interfaces can be used either in SPI mode or in I2S audio mode.
DocID025832 Rev 5
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27
Description
STM32F042x4 STM32F042x6
Figure 1. Block diagram
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12/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Functional overview
3
Functional overview
Figure 1 shows the general block diagram of the STM32F042x4/x6 devices.
3.1
ARM®-Cortex®-M0 core
®
®
The ARM Cortex -M0 is a generation of ARM 32-bit RISC processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
®
®
The ARM Cortex -M0 processors feature exceptional code-efficiency, delivering the high
performance expected from an ARM core, with memory sizes usually associated with 8- and
16-bit devices.
The STM32F042x4/x6 devices embed ARM core and are compatible with all ARM tools and
software.
3.2
Memories
The device has the following features:
•
6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
•
The non-volatile memory is divided into two arrays:
–
–
16 to 32 Kbytes of embedded Flash memory for programs and data
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
–
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
®
–
Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and
boot in RAM selection disabled
3.3
Boot modes
At startup, the boot pin and boot selector option bits are used to select one of the three boot
options:
•
•
•
boot from User Flash memory
boot from System Memory
boot from embedded SRAM
The boot pin is shared with the standard GPIO and can be disabled through the boot
selector option bits. The boot loader is located in System Memory. It is used to reprogram
2
the Flash memory by using USART on pins PA14/PA15, or PA9/PA10 or I C on pins
PB6/PB7 or through the USB DFU interface.
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3.4
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5
Power management
3.5.1
Power supply schemes
•
V
= V
= 2.0 to 3.6 V: external power supply for I/Os (V
) and the internal
DDIO1
DD
DDIO1
regulator. It is provided externally through VDD pins.
•
V
= from V to 3.6 V: external analog power supply for ADC, Reset blocks, RCs
DDA
DD
and PLL (minimum voltage to be applied to V
provided externally through VDDA pin. The V
is 2.4 V when the ADC is used). It is
voltage level must be always greater
DDA
DDA
or equal to the V voltage level and must be established first.
DD
•
V
= 1.65 to 3.6 V: external power supply for marked I/Os. V
is provided
DDIO2
DDIO2
externally through the VDDIO2 pin. The V
voltage level is completely independent
DDIO2
from V or V
, but it must not be provided without a valid supply on V . The
DD
DDA
DD
V
supply is monitored and compared with the internal reference voltage
DDIO2
(V
). When the V
is below this threshold, all the I/Os supplied from this rail
REFINT
DDIO2
are disabled by hardware. The output of this comparator is connected to EXTI line 31
and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for
concerned I/Os list.
•
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
For more details on how to connect power pins, refer to Figure 13: Power supply scheme.
3.5.2
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V
, without the need for an external reset circuit.
POR/PDR
•
The POR monitors only the V supply voltage. During the startup phase it is required
DD
that V
should arrive first and be greater than or equal to V
.
DDA
DD
•
The PDR monitors both the V and V
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V is higher than or
supply voltages, however the V
power
DD
DDA
DDA
DDA
equal to V
.
DD
The device features an embedded programmable voltage detector (PVD) that monitors the
power supply and compares it to the V threshold. An interrupt can be generated
V
DD
PVD
when V drops below the V
threshold and/or when V is higher than the V
DD
PVD
DD PVD
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threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.5.3
3.5.4
Voltage regulator
The regulator has two operating modes and it is always enabled after reset.
•
•
Main (MR) is used in normal operating mode (Run).
Low power (LPR) can be used in Stop mode where the power demand is reduced.
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
Low-power modes
The STM32F042x4/x6 microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC, I2C1 USART1, USB
or the CEC.
The CEC, USART1 and I2C1 peripherals can be configured to enable the HSI RC
oscillator so as to get clock for processing incoming data. If this is used when the
voltage regulator is put in low power mode, the regulator is first switched to normal
mode before the clock is provided to the given peripheral.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
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3.6
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL
input source. This oscillator can be automatically fine-trimmed by the means of the CRS
peripheral using the external synchronization.
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Figure 2. Clock tree
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3.7
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
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The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.8
Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers
(except TIM14) and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
®
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M0) and 4
priority levels.
•
•
•
•
•
•
•
•
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 38
GPIOs can be connected to the 16 external interrupt lines.
3.10
Analog-to-digital converter (ADC)
The 12-bit analog-to-digital converter has up to 10 external and 3 internal (temperature
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sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
that varies linearly with
SENSE
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
VDDA= 3.3 V (± 10 mV)
TS_CAL1
0x1FFF F7B8 - 0x1FFF F7B9
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
TS_CAL2
0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V (± 10 mV)
3.10.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC. V
is internally connected to the ADC_IN17 input channel. The precise voltage
REFINT
of V
is individually measured for each part by ST during production test and stored in
REFINT
the system memory area. It is accessible in read-only mode.
Table 4. Internal voltage reference calibration values
Calibration value name
Description
Memory address
Raw data acquired at a
VREFINT_CAL
temperature of 30 °C (± 5 °C),
0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V (± 10 mV)
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3.10.3
V
battery voltage monitoring
BAT
This embedded hardware feature allows the application to measure the V
battery voltage
BAT
using the internal ADC channel ADC_IN18. As the V
voltage may be higher than V
,
BAT
DDA
and thus outside the ADC input range, the V
pin is internally connected to a bridge
BAT
divider by 2. As a consequence, the converted digital value is half the V
voltage.
BAT
3.11
Touch sensing controller (TSC)
The STM32F042x4/x6 devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 14 capacitive sensing channels
distributed over 5 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists in
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
For operation, one capacitive sensing GPIO in each group is connected to an external
capacitor and cannot be used as effective touch sensing channel.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 5. Capacitive sensing GPIOs available on STM32F042x4/x6 devices
Capacitive sensing
signal name
Pin
name
Capacitive sensing
signal name
Pin
name
Group
Group
TSC_G1_IO1
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
TSC_G2_IO2
TSC_G2_IO3
TSC_G2_IO4
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
TSC_G5_IO1
TSC_G5_IO2
TSC_G5_IO3
TSC_G5_IO4
PA9
PA10
PA11
PA12
PB3
1
4
PB4
2
3
5
PB6
PB7
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Table 6. No. of capacitive sensing channels available on STM32F042x devices
Number of capacitive sensing channels
STM32F042Cx
LQPF48
STM32F042Kx
Analog I/O group
STM32F042Tx
STM32F042Gx STM32F042Fx
LQFP32
WLCSP36
UQFPN28
TSSOP20
UQFPN48
UQFPN32
G1
G2
3
3
3
3
3
3
3
3
3
3
1
2
G3
2
2
1
0
G4
G5
3
3
3
3
3
3
1
3
1
0
13
14
Number of capacitive
sensing channels
14
14
11
7
3.12
Timers and watchdogs
The STM32F042x4/x6 devices include up to five general-purpose timers and an advanced
control timer.
Table 7 compares the features of the different timers.
Table 7. Timer feature comparison
DMA
Timer
type
Counter
resolution
Counter
type
Prescaler
factor
Capture/compare Complementary
Timer
request
generation
channels
outputs
Advanced
control
Up, down, integer from
up/down 1 to 65536
TIM1
TIM2
TIM3
TIM14
16-bit
32-bit
16-bit
16-bit
16-bit
Yes
Yes
Yes
No
4
4
4
1
1
3
-
Up, down, integer from
up/down 1 to 65536
Up, down, integer from
-
up/down
1 to 65536
General
purpose
integer from
1 to 65536
Up
-
TIM16
TIM17
integer from
1 to 65536
Up
Yes
1
3.12.1
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
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can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
•
•
•
•
input capture
output compare
PWM generation (edge or center-aligned modes)
one-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.12.2
General-purpose timers (TIM2, 3, 14, 16, 17)
There are five synchronizable general-purpose timers embedded in the STM32F042x4/x6
devices (see Table 7 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F042x4/x6 devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17
Both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
They each have a single channel for input capture/output compare, PWM or one-pulse
mode output.
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TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
3.12.3
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.12.4
3.12.5
System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•
•
•
•
a 24-bit down counter
autoreload capability
maskable system interrupt generation when the counter reaches 0
programmable clock source (HCLK or HCLK/8)
3.13
Real-time clock (RTC) and backup registers
The RTC and the five backup registers are supplied through a switch that takes power either
on V supply when present or through the V
pin. The backup registers are five 32-bit
DD
BAT
registers used to store 20 bytes of user application data when V power is not present.
DD
They are not reset by a system or power reset, or at wake up from Standby mode.
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The RTC is an independent BCD timer/counter. Its main features are the following:
•
calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
•
•
•
automatic correction for 28, 29 (leap year), 30, and 31 day of the month
programmable alarm with wake up from Stop and Standby mode capability
on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock
•
•
•
digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
two anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection
timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection
•
reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
The RTC clock sources can be:
•
•
•
•
a 32.768 kHz external crystal
a resonator or oscillator
the internal low-power RC oscillator (typical frequency of 40 kHz)
the high-speed external clock divided by 32
3.14
Inter-integrated circuit interface (I2C)
2
The I C interface (I2C1) can operate in multimaster or slave modes. It can support Standard
mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)
with 20 mA output drive.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). It also includes programmable analog and digital
noise filters.
2
Table 8. Comparison of I C analog and digital filters
Aspect
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2Cx peripheral clocks
≥ 50 ns
–Extra filtering capability vs.
standard requirements
Benefits
Available in Stop mode
–Stable length
Wakeup from Stop on address
match is not available when digital
filter is enabled.
Variations depending on
temperature, voltage, process
Drawbacks
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
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from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripheral can be served by the DMA controller.
2
Table 9. STM32F042x4/x6 I C implementation
I2C features(1)
I2C1
7-bit addressing mode
X
X
X
X
X
X
X
X
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
Independent clock
SMBus
Wakeup from STOP
1. X = supported.
3.15
Universal synchronous/asynchronous receiver/transmitter
(USART)
The device embeds two universal synchronous/asynchronous receivers/transmitters
(USART1, USART2) which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. USART1 supports also SmartCard communication (ISO
7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a
clock domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.
The USART interfaces can be served by the DMA controller.
Table 10. STM32F042x4/x6 USART implementation
USART modes/features(1)
USART1
USART2
Hardware flow control for modem
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
Continuous communication using DMA
Multiprocessor communication
Synchronous mode
Smartcard mode
Single-wire half-duplex communication
IrDA SIR ENDEC block
X
-
LIN mode
-
Dual clock domain and wakeup from Stop mode
Receiver timeout interrupt
-
-
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27
Functional overview
STM32F042x4 STM32F042x6
Table 10. STM32F042x4/x6 USART implementation (continued)
USART modes/features(1)
USART1
USART2
Modbus communication
X
X
X
-
-
Auto baud rate detection
Driver Enable
X
1. X = supported.
3.16
Serial peripheral interface (SPI) / Inter-integrated sound
interface (I2S)
Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
2
One standard I S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at half-duplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit
programmable linear prescaler. When operating in master mode, it can output a clock for an
external audio component at 256 times the sampling frequency.
2
Table 11. STM32F042x4/x6 SPI/I S implementation
SPI features(1)
SPI1
SPI2
Hardware CRC calculation
X
X
X
X
X
X
X
X
-
Rx/Tx FIFO
NSS pulse mode
I2S mode
TI mode
X
1. X = supported.
3.17
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.18
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
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DocID025832 Rev 5
STM32F042x4 STM32F042x6
Functional overview
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.19
Universal serial bus (USB)
The STM32F042x4/x6 embeds a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up-to 1 KB (the last 256 byte are used for CAN peripheral if
enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be
generated from the internal main PLL (the clock source must use an HSE crystal oscillator)
or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this
oscillator can be taken from the USB data stream itself (SOF signalization) which allows
crystal-less operation.
3.20
3.21
Clock recovery system (CRS)
The STM32F042x4/x6 embeds a special block which allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from USB SOF signalization, from LSE oscillator, from an
external signal on CRS_SYNC pin or generated by user software. For faster lock-in during
startup it is also possible to combine automatic trimming with manual trimming action.
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
DocID025832 Rev 5
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27
Pinouts and pin descriptions
STM32F042x4 STM32F042x6
4
Pinouts and pin descriptions
Figure 3. LQFP48 package pinout
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28/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Pinouts and pin descriptions
Figure 5. WLCSP36 package pinout
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1. The above figure shows the package in top view, changing from bottom view in the previous document
versions.
Figure 6. LQFP32 package pinout
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DocID025832 Rev 5
29/117
38
Pinouts and pin descriptions
STM32F042x4 STM32F042x6
Figure 7. UFQFPN32 package pinout
7RSꢅYLHZ
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1. Pin pair PA11/12 can be remapped in place of pin pair PA9/10 using the SYSCFG_CFGR1 register.
30/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Pinouts and pin descriptions
Figure 9. TSSOP20 package
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1. Pin pair PA11/12 can be remapped in place of pin pair PA9/10 using the SYSCFG_CFGR1 register.
Table 12. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
Pin name
S
Supply pin
Pin type
I/O
Input / output pin
FT
5 V-tolerant I/O
FTf
TTa
TC
5 V-tolerant I/O, FM+ capable
3.3 V-tolerant I/O directly connected to ADC
Standard 3.3 V I/O
I/O structure
Notes
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Pin
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
DocID025832 Rev 5
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38
Pinouts and pin descriptions
Pin numbers
STM32F042x4 STM32F042x6
Pin functions
Table 13. STM32F042x pin definitions
Pin name
Pin
(function upon
type
Additional
functions
Alternate function
reset)
1
2
-
-
-
-
-
-
-
-
-
VBAT
PC13
S
-
-
Backup power supply
WKUP2,
(1)
(2)
RTC_TAMP1,
A6
I/O
TC
-
RTC_TS,
RTC_OUT
PC14-
OSC32_IN
(PC14)
(1)
(2)
3
4
B6
C6
-
-
-
-
-
-
-
-
I/O
I/O
TC
TC
-
-
OSC32_IN
PC15-
OSC32_OUT
(PC15)
(1)
(2)
OSC32_OUT
CRS_ SYNC
I2C1_SDA
PF0-OSC_IN
(PF0)
5
6
7
B5
C5
D5
2
3
4
2
3
4
2
3
4
2
3
4
I/O
I/O
FTf
FTf
-
-
OSC_IN
PF1-OSC_OUT
(PF1)
I2C1_SCL
OSC_OUT
Device reset input / internal reset output
(active low)
NRST
I/O RST
-
(3)
8
9
D6 32
0
5
16
5
15
5
VSSA
VDDA
S
S
Analog ground
E5
5
-
-
Analog power supply
RTC_
USART2_CTS,
TAMP2,
10 F6
11 D4
6
6
7
6
7
6
7
PA0
PA1
I/O TTa
I/O TTa
TIM2_CH1_ETR,
WKUP1,
TSC_G1_IO1
ADC_IN0,
USART2_RTS,
TIM2_CH2,
TSC_G1_IO2,
7
-
ADC_IN1
EVENTOUT
USART2_TX,
ADC_IN2,
12 E4
13 F5
8
9
8
9
8
9
8
9
PA2
PA3
I/O TTa
I/O TTa
-
-
TIM2_CH3,
WKUP4
TSC_G1_IO3
USART2_RX,
TIM2_CH4,
ADC_IN3
TSC_G1_IO4
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STM32F042x4 STM32F042x6
Pinouts and pin descriptions
Pin functions
Table 13. STM32F042x pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Pin
type
Additional
Alternate function
functions
SPI1_NSS, I2S1_WS,
TIM14_CH1,
14 C3 10 10 10
10
11
12
PA4
PA5
PA6
I/O TTa
I/O TTa
I/O TTa
-
-
-
TSC_G2_IO1,
USART2_CK
USB_NOE
ADC_IN4
ADC_IN5
ADC_IN6
SPI1_SCK, I2S1_CK,
CEC,
TIM2_CH1_ETR,
TSC_G2_IO2
15 D3 11 11
11
SPI1_MISO, I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
TIM16_CH1,
16 E3 12 12 12
TSC_G2_IO3,
EVENTOUT
SPI1_MOSI, I2S1_SD,
TIM3_CH2, TIM14_CH1,
TIM1_CH1N,
17 F4 13 13 13
13
PA7
PB0
I/O TTa
-
-
ADC_IN7
ADC_IN8
TIM17_CH1,
TSC_G2_IO4,
EVENTOUT
TIM3_CH3,
TIM1_CH2N,
TSC_G3_IO2,
EVENTOUT
18 F3 14 14 14
-
I/O TTa
I/O TTa
TIM3_CH4,TIM14_CH1,
TIM1_CH3N,
19 F2 15 15 15
14
-
PB1
PB2
-
-
-
ADC_IN9
TSC_G3_IO3
20 D2
-
-
16
-
-
-
I/O
I/O
FT
TSC_G3_IO4
-
-
SPI2_SCK, CEC,
TSC_SYNC, TIM2_CH3,
I2C1_SCL
21
22
-
-
-
PB10
FTf
TIM2_CH4,
EVENTOUT,
I2C1_SDA
-
-
-
-
PB11
I/O
FTf
-
-
-
23 F1 16
0
-
16
17
15
16
VSS
VDD
S
S
-
-
-
-
Ground
24
25
-
-
-
-
Digital power supply
TIM1_BKIN, SPI2_NSS,
EVENTOUT
-
-
-
PB12
I/O
FT
-
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38
Pinouts and pin descriptions
STM32F042x4 STM32F042x6
Pin functions
Table 13. STM32F042x pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Pin
type
Additional
functions
Alternate function
SPI2_SCK,
TIM1_CH1N,
I2C1_SCL
26
-
-
-
-
-
PB13
I/O
FTf
-
-
-
SPI2_MISO,
TIM1_CH2N,
I2C1_SDA
27
28
-
-
-
-
-
-
-
-
-
-
PB14
PB15
I/O
I/O
FTf
FT
-
-
SPI2_MOSI,
TIM1_CH3N
WKUP7,
RTC_REFIN
USART1_CK,
TIM1_CH1,
EVENTOUT, MCO,
CRS_SYNC
(4)
(4)
29 E2 18 18
-
-
PA8
PA9
I/O
I/O
FT
-
-
USART1_TX,
TIM1_CH2,
TSC_G4_IO1,
I2C1_SCL
30 D1 19 19 19
17
FTf
USART1_RX,
TIM1_CH3,
TIM17_BKIN,
TSC_G4_IO2,
I2C1_SDA
(4)
(4)
(4)
31 C1 20 20 20
18
PA10
PA11
I/O
I/O
FTf
FTf
-
CAN_RX,
USART1_CTS,
TIM1_CH4,
TSC_G4_IO3,
EVENTOUT,
I2C1_SCL
32 C2 21 21 19(5) 17(5)
USB_DM
CAN_TX,USART1_RTS,
TIM1_ETR,
33 A1 22 22 20(5) 18(5)
PA12
PA13
I/O
I/O
FTf
FT
TSC_G4_IO4,
EVENTOUT,
USB_DP
I2C1_SDA
(4)
(6)
IR_OUT, SWDIO
USB_NOE
34 B1 23 23 21
35
19
-
-
-
-
-
-
VSS
S
S
-
-
-
-
Ground
36 E1 17 17 18
37 B2 24 24 22
16
VDDIO2
Digital power supply
(4)
(6)
20
PA14
I/O
FT
USART2_TX, SWCLK
-
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STM32F042x4 STM32F042x6
Pinouts and pin descriptions
Pin functions
Table 13. STM32F042x pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Pin
type
Additional
Alternate function
functions
SPI1_NSS, I2S1_WS,
USART2_RX,
TIM2_CH1_ETR,
EVENTOUT,
USB_NOE
(4)
38 A2 25 25 23
39 B3 26 26 24
40 A3 27 27 25
-
-
-
PA15
PB3
PB4
I/O
I/O
I/O
FT
FT
FT
-
-
-
SPI1_SCK, I2S1_CK,
TIM2_CH2,
-
-
TSC_G5_IO1,
EVENTOUT
SPI1_MISO, I2S1_MCK,
TIM17_BKIN,
TIM3_CH1,
TSC_G5_IO2,
EVENTOUT
SPI1_MOSI, I2S1_SD,
I2C1_SMBA,
41 E6 28 28 26
42 C4 29 29 27
43 A4 30 30 28
-
-
PB5
PB6
I/O
I/O
FT
-
-
WKUP6
TIM16_BKIN,
TIM3_CH2
I2C1_SCL,
USART1_TX,
TIM16_CH1N,
TSC_G5_I03
FTf
-
-
I2C1_SDA,
USART1_RX,
TIM17_CH1N,
TSC_G5_IO4
-
-
PB7
I/O
I/O
I/O
FTf
FT
-
-
-
Boot memory
selection
44
-
-
-
31
-
-
PF11-BOOT0
PB8-BOOT0
-
I2C1_SCL, CEC,
TIM16_CH1,
TSC_SYNC,
CAN_RX
Boot memory
selection
B4 31
1
1
FTf
I2C1_SCL, CEC,
TIM16_CH1,
TSC_SYNC,
CAN_RX
45
-
-
32
-
-
PB8
I/O
FTf
-
-
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38
Pinouts and pin descriptions
STM32F042x4 STM32F042x6
Pin functions
Table 13. STM32F042x pin definitions (continued)
Pin numbers
Pin name
(function upon
reset)
Pin
type
Additional
functions
Alternate function
SPI2_NSS,
I2C1_SDA, IR_OUT,
TIM17_CH1,
46
47
-
-
-
-
-
-
PB9
I/O
FTf
-
-
EVENTOUT,
CAN_TX
32
1
0
1
-
-
-
-
VSS
VDD
S
S
-
-
-
-
Ground
48 A5
Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to
the RTC domain and RTC register descriptions in the reference manual.
3. Distinct VSSA pin is only available on 48-pin packages. On all other packages, the pin number corresponds to the VSS
pin to which VSSA pad of the silicon die is connected.
4. PA8, PA9, PA10, PA11, PA12, PA13, PA14 and PA15 I/Os are supplied by VDDIO2.
5. Pin pair PA11/12 can be remapped in place of pin pair PA9/10 using SYSCFG_CFGR1 register.
6. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO
pin and the internal pull-down on the SWCLK pin are activated.
36/117
DocID025832 Rev 5
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PA0
PA1
-
EVENTOUT
-
USART2_CTS TIM2_CH1_ETR TSC_G1_IO1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
CEC
TIM2_CH2
TIM2_CH3
TIM2_CH4
USB_NOE
TSC_G1_IO2
TSC_G1_IO3
TSC_G1_IO4
TSC_G2_IO1
-
-
-
PA2
-
-
-
PA3
-
-
-
-
PA4
SPI1_NSS, I2S1_WS
SPI1_SCK, I2S1_CK
SPI1_MISO, I2S1_MCK
SPI1_MOSI, I2S1_SD
MCO
TIM14_CH1
-
-
PA5
TIM2_CH1_ETR TSC_G2_IO2
-
-
-
PA6
TIM3_CH1
TIM1_BKIN
TIM1_CH1N
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
USB_NOE
-
TSC_G2_IO3
TSC_G2_IO4
EVENTOUT
TSC_G4_IO1
TSC_G4_IO2
TSC_G4_IO3
TSC_G4_IO4
-
-
TIM16_CH1
EVENTOUT
PA7
TIM3_CH2
TIM14_CH1
CRS_SYNC
I2C1_SCL
I2C1_SDA
CAN_RX
CAN_TX
-
TIM17_CH1
EVENTOUT
PA8
USART1_CK
USART1_TX
USART1_RX
USART1_CTS
USART1_RTS
IR_OUT
-
-
-
-
-
-
-
-
-
PA9
-
MCO
PA10
PA11
PA12
PA13
PA14
PA15
TIM17_BKIN
EVENTOUT
EVENTOUT
SWDIO
-
I2C1_SCL
I2C1_SDA
-
SWCLK
USART2_TX
USART2_RX
-
-
-
SPI1_NSS, I2S1_WS
TIM2_CH1_ETR EVENTOUT
-
USB_NOE
Table 15. Alternate functions selected through GPIOB_AFR registers for port B
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
PB0
PB1
EVENTOUT
TIM14_CH1
-
TIM3_CH3
TIM3_CH4
-
TIM1_CH2N
TIM1_CH3N
-
TSC_G3_IO2
TSC_G3_IO3
TSC_G3_IO4
TSC_G5_IO1
TSC_G5_IO2
I2C1_SMBA
TSC_G5_IO3
TSC_G5_IO4
TSC_SYNC
EVENTOUT
TSC_SYNC
-
-
-
-
-
PB2
-
-
PB3
SPI1_SCK, I2S1_CK
SPI1_MISO, I2S1_MCK
SPI1_MOSI, I2S1_SD
USART1_TX
USART1_RX
CEC
EVENTOUT
TIM3_CH1
TIM3_CH2
I2C1_SCL
I2C1_SDA
I2C1_SCL
I2C1_SDA
I2C1_SCL
I2C1_SDA
EVENTOUT
-
TIM2_CH2
EVENTOUT
TIM16_BKIN
TIM16_CH1N
TIM17_CH1N
TIM16_CH1
TIM17_CH1
TIM2_CH3
TIM2_CH4
TIM1_BKIN
TIM1_CH1N
TIM1_CH2N
TIM1_CH3N
-
-
PB4
-
TIM17_BKIN
PB5
-
-
PB6
-
-
PB7
-
-
PB8
CAN_RX
-
PB9
IR_OUT
CAN_TX
SPI2_NSS
PB10
PB11
PB12
PB13
PB14
PB15
CEC
-
-
-
-
-
-
SPI2_SCK
EVENTOUT
SPI2_NSS
-
-
-
SPI2_SCK
-
I2C1_SCL
I2C1_SDA
-
SPI2_MISO
SPI2_MOSI
-
-
-
-
Table 16. Alternate functions selected through GPIOF_AFR registers for port F
Pin name
AF0
AF1
PF0
PF1
CRS_SYNC
-
I2C1_SDA
I2C1_SCL
STM32F042x4 STM32F042x6
Memory mapping
5
Memory mapping
To the difference of STM32F042x6 memory map in Figure 10, the two bottom code memory
spaces of STM32F042x4 end at 0x0000 3FFF and 0x0800 3FFF, respectively.
Figure 10. STM32F042x6 memory map
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DocID025832 Rev 5
39/117
41
Memory mapping
STM32F042x4 STM32F042x6
Table 17. STM32F042x4/x6 peripheral register boundary addresses
Bus
Boundary address
Size
Peripheral
0x4800 1800 - 0x5FFF FFFF
0x4800 1400 - 0x4800 17FF
0x4800 0C00 - 0x4800 13FF
0x4800 0800 - 0x4800 0BFF
0x4800 0400 - 0x4800 07FF
0x4800 0000 - 0x4800 03FF
0x4002 4400 - 0x47FF FFFF
0x4002 4000 - 0x4002 43FF
0x4002 3400 - 0x4002 3FFF
0x4002 3000 - 0x4002 33FF
0x4002 2400 - 0x4002 2FFF
0x4002 2000 - 0x4002 23FF
0x4002 1400 - 0x4002 1FFF
0x4002 1000 - 0x4002 13FF
0x4002 0400 - 0x4002 0FFF
0x4002 0000 - 0x4002 03FF
0x4001 8000 - 0x4001 FFFF
0x4001 5C00 - 0x4001 7FFF
0x4001 5800 - 0x4001 5BFF
0x4001 4C00 - 0x4001 57FF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 3C00 - 0x4001 43FF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
0x4001 0800 - 0x4001 23FF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
0x4000 8000 - 0x4000 FFFF
~384 MB
1 KB
2 KB
1 KB
1 KB
1 KB
~128 MB
1 KB
3 KB
1 KB
3 KB
1 KB
3 KB
1 KB
3 KB
1 KB
32 KB
9 KB
1 KB
3 KB
1 KB
1 KB
2 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
7 KB
1 KB
1 KB
32 KB
Reserved
GPIOF
Reserved
GPIOC
AHB2
GPIOB
GPIOA
Reserved
TSC
Reserved
CRC
Reserved
Flash memory interface
Reserved
RCC
AHB1
Reserved
DMA
Reserved
Reserved
DBGMCU
Reserved
TIM17
TIM16
Reserved
USART1
Reserved
SPI1/I2S1
TIM1
APB
Reserved
ADC
Reserved
EXTI
SYSCFG
Reserved
40/117
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STM32F042x4 STM32F042x6
Memory mapping
Table 17. STM32F042x4/x6 peripheral register boundary addresses (continued)
Bus
Boundary address
Size
Peripheral
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
3 KB
1 KB
2 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
6 KB
1 KB
1 KB
Reserved
CEC
Reserved
PWR
CRS
0x4000 6800 - 0x4000 6BFF0
Reserved
BxCAN
USB/CAN RAM
USB
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 4800 - 0x4000 53FF
0x4000 4400 - 0x4000 47FF
0x4000 3C00 - 0x4000 43FF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 0800 - 0x4000 1FFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
Reserved
I2C1
Reserved
USART2
Reserved
SPI2
APB
Reserved
IWDG
WWDG
RTC
Reserved
TIM14
Reserved
TIM3
TIM2
DocID025832 Rev 5
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41
Electrical characteristics
STM32F042x4 STM32F042x6
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = V = 3.3 V. They
DDA
are given only as design guidelines and are not tested.
A
DD
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
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DocID025832 Rev 5
STM32F042x4 STM32F042x6
Electrical characteristics
6.1.6
Power supply scheme
Figure 13. Power supply scheme
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Caution:
Each power supply pair (V /V , V
/V
etc.) must be decoupled with filtering ceramic
DD SS DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DocID025832 Rev 5
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89
Electrical characteristics
STM32F042x4 STM32F042x6
6.1.7
Current consumption measurement
Figure 14. Current consumption measurement scheme
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44/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Electrical characteristics
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
(1)
Table 18. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
V
DD–VSS External main supply voltage
- 0.3
- 0.3
4.0
V
V
VDDIO2–VSS External I/O supply voltage
VDDA–VSS External analog supply voltage
4.0
- 0.3
4.0
V
VDD–VDDA Allowed voltage difference for VDD > VDDA
-
0.4
V
VBAT–VSS External backup supply voltage
- 0.3
4.0
V
Input voltage on FT and FTf pins
VSS - 0.3
VSS - 0.3
VSS - 0.3
-
VDDIOx + 4.0 (3)
V
(2)
VIN
Input voltage on TTa pins
4.0
4.0
50
V
Input voltage on any other pin
V
|∆VDDx
|
Variations between different VDD power pins
mV
Variations between all the different ground
pins
|VSSx - VSS
|
-
50
mV
-
Electrostatic discharge voltage
(human body model)
see Section 6.3.12: Electrical
sensitivity characteristics
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum
allowed injected current values.
3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is
enabled, the maximum limit is 4 V.
DocID025832 Rev 5
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89
Electrical characteristics
Symbol
STM32F042x4 STM32F042x6
Table 19. Current characteristics
Ratings
Max.
Unit
ΣIVDD
ΣIVSS
Total current into sum of all VDD power lines (source)(1)
Total current out of sum of all VSS ground lines (sink)(1)
Maximum current into each VDD power pin (source)(1)
Maximum current out of each VSS ground pin (sink)(1)
Output current sunk by any I/O and control pin
120
-120
100
-100
25
IVDD(PIN)
IVSS(PIN)
IIO(PIN)
Output current source by any I/O and control pin
Total output current sunk by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os and control pins(2)
Total output current sourced by sum of all I/Os supplied by VDDIO2
Injected current on FT and FTf pins
-25
80
ΣIIO(PIN)
-80
mA
-40
-5/+0(4)
(3)
IINJ(PIN)
Injected current on TC and RST pin
± 5
Injected current on TTa pins(5)
± 5
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(6)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 18: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 56: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 20. Thermal characteristics
Symbol
Ratings
Storage temperature range
Maximum junction temperature
Value
Unit
TSTG
TJ
–65 to +150
150
°C
°C
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STM32F042x4 STM32F042x6
Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 21. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK
VDD
Internal AHB clock frequency
Internal APB clock frequency
Standard operating voltage
-
-
-
0
0
48
48
MHz
2.0
3.6
V
V
Must not be supplied if VDD
is not present
VDDIO2
I/O supply voltage
1.65
VDD
2.4
3.6
3.6
3.6
Analog operating voltage
(ADC not used)
Must have a potential equal
to or higher than VDD
VDDA
V
Analog operating voltage
(ADC used)
VBAT
Backup operating voltage
-
TC and RST I/O
TTa I/O
1.65
-0.3
-0.3
-0.3
-
3.6
V
V
VDDIOx+0.3
VIN
I/O input voltage
V
DDA+0.3(1)
5.5(1)
364
FT and FTf I/O
LQFP48
UFQFPN48
-
606
WLCSP36
-
313
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(2)
PD
LQFP32
-
351
mW
UFQFPN32
-
526
UFQFPN28
-
170
TSSOP20
-
263
Maximum power dissipation
Low power dissipation(3)
Maximum power dissipation
Low power dissipation(3)
Suffix 6 version
Suffix 7 version
–40
–40
–40
–40
–40
–40
85
Ambient temperature for the
suffix 6 version
°C
°C
°C
105
TA
TJ
105
Ambient temperature for the
suffix 7 version
125
105
Junction temperature range
125
1. For operation with a voltage higher than VDDIOx + 0.3 V, the internal pull-up resistor must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. See Section 7.8: Thermal characteristics.
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:
Thermal characteristicsSection 7.8: Thermal characteristics).
6.3.2
Operating conditions at power-up / power-down
The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
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89
Electrical characteristics
Symbol
STM32F042x4 STM32F042x6
Table 22. Operating conditions at power-up / power-down
Parameter
Conditions
Min
0
Max
∞
Unit
VDD rise time rate
VDD fall time rate
VDDA rise time rate
VDDA fall time rate
tVDD
-
20
0
∞
µs/V
∞
tVDDA
-
20
∞
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 23. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Falling edge(2)
1.96(3)
2.00
-
1.80
1.84(3)
-
1.88
1.92
40
V
V
Power on/power down
reset threshold
(1)
VPOR/PDR
Rising edge
VPDRhyst
PDR hysteresis
-
-
mV
ms
(4)
tRSTTEMPO
Reset temporization
1.50
2.50
4.50
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD
.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Data based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
Table 24. Programmable voltage detector characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
2.1
2
2.18
2.08
2.28
2.18
2.38
2.28
2.48
2.38
2.58
2.48
2.68
2.58
2.26
2.16
2.37
2.27
2.48
2.38
2.58
2.48
2.69
2.59
2.79
2.69
V
V
V
V
V
V
V
V
V
V
V
V
VPVD0
PVD threshold 0
2.19
2.09
2.28
2.18
2.38
2.28
2.47
2.37
2.57
2.47
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
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Electrical characteristics
Table 24. Programmable voltage detector characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rising edge
Falling edge
Rising edge
Falling edge
-
2.66
2.56
2.76
2.66
-
2.78
2.68
2.88
2.78
100
2.9
2.8
3
V
V
VPVD6
PVD threshold 6
V
VPVD7
PVD threshold 7
2.9
V
(1)
VPVDhyst
IDD(PVD)
PVD hysteresis
-
mV
µA
PVD current consumption
-
-
0.15 0.26(1)
1. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 25 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 25. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Internal reference voltage –40 °C < TA < +105 °C
1.2
1.23 1.25
V
V
REFINT
ADC_IN17 buffer startup
time
tSTART
-
-
-
-
10(1)
µs
µs
ADC sampling time when
reading the internal
reference voltage
4(1)
tS_vrefint
-
-
Internal reference voltage
spread over the
temperature range
10(1)
∆VREFINT
VDDA = 3 V
-
-
-
mV
- 100(1)
100(1)
TCoeff
Temperature coefficient
-
ppm/°C
1. Guaranteed by design, not tested in production.
6.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
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Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the f frequency:
HCLK
–
–
0 wait state and Prefetch OFF from 0 to 24 MHz
1 wait state and Prefetch ON above 24 MHz
= f
•
When the peripherals are enabled f
PCLK
HCLK
The parameters given in Table 26 to Table 28 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
Table 26. Typical and maximum current consumption from V supply at V = 3.6 V
DD
DD
All peripherals enabled(1)
All peripherals disabled
(2)
(2)
Max @ TA
Max @ TA
Conditions
fHCLK
Unit
Typ
Typ
25 °C
85 °C 105 °C
25 °C 85 °C 105 °C
HSI48
48 MHz 20.3
48 MHz 20.2
32 MHz 14.0
24 MHz 11.0
23.2
22.9
16.0
13.5
5.2
23.4
23.0
16.1
13.7
5.3
24.6
23.9
16.7
13.8
5.6
12.7 14.4
12.6 14.1
14.4
14.3
9.7
14.7
14.4
10.3
8.2
HSEbypass,
PLL on
8.7
6.9
2.6
0.7
9.5
7.6
3.1
1.0
7.8
8 MHz
1 MHz
3.9
0.9
3.2
3.3
HSEbypass,
PLL off
IDD
mA
1.3
1.5
1.8
1.1
1.3
48 MHz 20.5
32 MHz 14.3
24 MHz 11.2
23.1
15.6
13.6
23.3
15.9
13.8
23.6
17.0
14.8
12.8 14.6
14.6
9.7
15.0
10.0
7.7
HSI clock,
PLL on
8.6
6.9
9.5
7.4
7.5
HSI clock,
PLL off
8 MHz
4.1
5.2
5.3
5.6
2.6
3.1
3.1
3.3
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Electrical characteristics
Table 26. Typical and maximum current consumption from V supply at V = 3.6 V (continued)
DD
DD
All peripherals enabled(1)
All peripherals disabled
(2)
(2)
Max @ TA
Max @ TA
Conditions
fHCLK
Unit
Typ
Typ
25 °C
85 °C 105 °C
25 °C 85 °C 105 °C
HSI48
48 MHz 19.3
21.9
22.1
22.0
15.9
13.0
4.3
23.7
11.9
13.4
13.6
13.7
48 MHz 19.2 21.8(3)
22.1(3) 11.7 13.3(3) 13.5 13.7(3)
HSEbypass,
PLL on
32 MHz 13.4
24 MHz 10.3
15.8
12.6
4.1
16.0
13.4
4.4
7.9
6.2
2.0
0.4
11.8
8.0
6.5
8.8
8.0
2.1
0.5
13.6
8.8
8.0
8.9
8.2
2.1
0.6
13.8
9.1
8.1
9.7
8.3
2.5
0.8
13.9
9.9
8.4
8 MHz
1 MHz
3.6
0.8
HSEbypass,
PLL off
0.9
0.9
1.1
48 MHz 19.5
32 MHz 13.5
24 MHz 10.5
22.0
16.3
12.8
22.1
16.4
13.0
22.5
16.6
13.8
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz
3.7
4.7
5.0
5.3
2.1
2.3
2.4
3.0
IDD
mA
HSI48
48 MHz 12.4
15.1
16.3
16.0
11.2
8.5
16.7
16.2(3)
11.7
8.7
3.0
2.9
1.9
1.6
0.7
0.1
3.0
2.1
1.6
3.2
3.2(3)
2.1
3.3
3.3
2.2
1.8
0.8
0.3
3.2
2.2
1.7
3.4
3.4(3)
2.5
48 MHz 12.3 15.0(3)
HSEbypass,
PLL on
32 MHz
24 MHz
8 MHz
8.5
6.5
2.3
0.4
10.6
8.1
1.8
1.9
3.0
3.1
3.2
0.8
0.9
HSEbypass,
PLL off
1 MHz
0.4
0.4
0.6
0.3
0.4
48 MHz 12.4
15.3
10.7
8.4
15.7
11.3
8.7
15.9
11.6
8.9
3.0
3.4
HSI clock,
PLL on
32 MHz
24 MHz
8.6
6.6
2.2
2.5
1.6
1.9
HSI clock,
PLL off
8 MHz
2.4
3.2
3.4
3.6
0.6
0.8
0.9
1.0
1. USB is kept disabled as this IP functions only with a 48 MHz clock.
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
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Table 27. Typical and maximum current consumption from the V
supply
= 3.6 V
DDA
DDA
V
= 2.4 V
V
DDA
Para-
meter
Conditions
(2)
(2)
Symbol
fHCLK
Unit
Max @ TA
25 °C 85 °C 105 °C
Max @ TA
25 °C 85 °C 105 °C
(1)
Typ
Typ
HSI48
48 MHz 309
325
332
176
124
99
342
317
334
338
344
197(3)
137
48 MHz 148 167(3)
179(3) 161 181(3) 193
HSE
bypass,
PLL on
Supply
current in
Run or
Sleep
32 MHz 102
24 MHz 80
119
95
126
100
4.5
111
88
128
102
4.7
135
106
5.2
108
HSE
bypass,
PLL off
8 MHz
1 MHz
2.7
2.7
3.7
4.2
3.5
5.5
mode,
IDDA
code
µA
3.7
4.2
4.2
3.6
4.7
5.2
5.5
executing
from
Flash
memory
or RAM
48 MHz 220
32 MHz 173
24 MHz 151
242
193
169
251
200
175
254
202
177
242
191
167
264
211
184
275
219
191
279
221
193
HSI clock,
PLL on
HSI clock,
PLL off
8 MHz
72
82
85
85
82
92
95
95
1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, IDDA is independent from
the frequency.
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
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Electrical characteristics
Table 28. Typical and maximum consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA
)
Max(1)
Conditions
TA = TA = TA =
25°C 85°C 105°C
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
Regulator in run
mode, all
oscillators OFF
14.3
2.9
14.5
3.1
14.6
3.2
14.7
3.3
14.8
3.4
14.9 21.0 47.0 64.0
Supply
current in
Regulator in low-
Stop mode
power mode, all
3.5
6.5 32.0 44.0
IDD
oscillators OFF
LSI ON and IWDG
ON
Supply
current in
Standby
mode
0.8
0.6
0.9
0.7
1.1
0.8
1.2
0.9
1.3
1.0
1.5
1.1
-
-
-
LSI OFF and IWDG
OFF
2.0
2.5
3.0
Regulator in
run mode, all
oscillators
OFF
2.0
2.0
2.1
2.1
2.2
2.2
2.4
2.4
2.5
2.5
2.7
2.7
3.5
3.5
3.5
3.5
4.5
4.5
Supply
current in
Stop mode
Regulator in
low-power
mode, all
oscillators
OFF
µA
LSI ON and
IWDG ON
Supply
current in
Standby
mode
2.4
1.9
2.6
2.0
2.8
2.1
3.0
2.3
3.1
2.4
3.4
2.5
-
-
-
LSI OFF and
IWDG OFF
3.4
3.5
4.5
IDDA
Regulator in
run mode, all
oscillators
OFF
1.3
1.3
1.3
1.3
1.3
1.3
1.4
1.4
1.4
1.4
1.5
1.5
-
-
-
-
-
-
Supply
current in
Stop mode
Regulator in
low-power
mode, all
oscillators
OFF
LSI ON and
IWDG ON
Supply
current in
Standby
mode
1.7
1.1
1.8
1.2
1.8
1.2
2.0
1.3
2.1
1.3
2.2
1.4
-
-
-
-
-
-
LSI OFF and
IWDG OFF
1. Data based on characterization results, not tested in production unless otherwise specified.
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Table 29. Typical and maximum current consumption from the V
supply
Max(1)
BAT
Typ @ VBAT
Symbol Parameter
Conditions
Unit
TA =
TA =
TA =
25 °C 85 °C 105 °C
LSE & RTC ON; “Xtal
mode”: lower driving
capability;
0.5 0.5 0.6 0.7 0.9 1.1
1.2
1.6
1.5
2.0
2.0
2.6
RTC
domain
supply
current
LSEDRV[1:0] = '00'
IDD VBAT
_
µA
LSE & RTC ON; “Xtal
mode” higher driving
capability;
0.8 0.9 1.1 1.2 1.4 1.5
LSEDRV[1:0] = '11'
1. Data based on characterization results, not tested in production.
Typical current consumption
The MCU is placed under the following conditions:
•
•
•
V
= V
= 3.3 V
DDA
DD
All I/O pins are in analog input configuration
The Flash memory access time is adjusted to f
frequency:
HCLK
–
–
0 wait state and Prefetch OFF from 0 to 24 MHz
1 wait state and Prefetch ON above 24 MHz
= f
•
•
•
When the peripherals are enabled, f
PCLK
HCLK
PLL is used for frequencies greater than 8 MHz
AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
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Electrical characteristics
Table 30. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal
Typical consumption in
Run mode
Typical consumption in
Sleep mode
Symbol Parameter
fHCLK
Unit
Peripherals Peripherals Peripherals Peripherals
enabled
disabled
enabled
disabled
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
20.7
15.9
14.3
11.0
7.7
12.8
9.9
9.0
7.1
5.0
3.0
2.0
1.5
1.2
1.1
12.3
9.5
8.5
6.6
4.7
2.7
1.7
1.2
1.0
0.8
3.4
2.7
2.5
2.1
1.6
1.2
0.9
0.8
0.8
0.7
Current
consumption
from VDD
supply
IDD
mA
4.3
4 MHz
2.6
2 MHz
1.8
1 MHz
1.4
500 kHz
48 MHz
36 MHz
32 MHz
24 MHz
16 MHz
8 MHz
1.2
163.3
124.3
111.9
87.1
62.5
2.5
Current
consumption
from VDDA
supply
IDDA
μA
4 MHz
2.5
2 MHz
2.5
1 MHz
2.5
500 kHz
2.5
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 50: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
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trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 32: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
ISW = VDDIOx × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the I/O supply voltage
DDIOx
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C
+ C
+ C
EXT S
INT
C is the PCB board capacitance including the pad pin.
S
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics
Table 31. Switching output I/O current consumption
I/O toggling
frequency (fSW
Symbol
Parameter
Conditions(1)
Typ
Unit
)
4 MHz
0.07
8 MHz
16 MHz
24 MHz
48 MHz
4 MHz
0.15
0.31
0.53
0.92
0.18
0.37
0.76
1.39
2.188
0.32
0.64
1.25
2.23
4.442
0.49
0.94
2.38
3.99
0.64
1.25
3.24
5.02
0.81
1.7
VDDIOx = 3.3 V
C =CINT
8 MHz
VDDIOx = 3.3 V
CEXT = 0 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
8 MHz
VDDIOx = 3.3 V
CEXT = 10 pF
16 MHz
24 MHz
48 MHz
4 MHz
C = CINT + CEXT+ CS
I/O current
consumption
ISW
mA
VDDIOx = 3.3 V
8 MHz
CEXT = 22 pF
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 33 pF
8 MHz
16 MHz
24 MHz
4 MHz
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 47 pF
8 MHz
C = CINT + CEXT+ CS
C = Cint
16 MHz
3.67
4 MHz
8 MHz
0.66
1.43
2.45
4.97
VDDIOx = 2.4 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
16 MHz
24 MHz
1. CS = 7 pF (estimated value).
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On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 32. The MCU is placed
under the following conditions:
•
•
•
All I/O pins are in analog mode
All peripherals are disabled unless otherwise mentioned
The given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
•
Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
Table 32. Peripheral current consumption
Peripheral
BusMatrix(1)
Typical consumption at 25 °C
Unit
2.2
1.9
5.1
15.0
8.2
7.7
2.1
1.8
1.1
4.9
49.8
CRC
DMA
Flash memory interface
GPIOA
AHB
GPIOB
µA/MHz
GPIOC
GPIOF
SRAM
TSC
All AHB peripherals
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Electrical characteristics
Table 32. Peripheral current consumption (continued)
Peripheral
Typical consumption at 25 °C
Unit
APB-Bridge(2)
2.9
3.9
ADC(3)
CAN
12.9
1.5
CEC
CRS
1.0
DBG (MCU Debug Support)
0.2
I2C1
3.6
PWR
1.4
SPI1
8.5
SPI2
6.1
SYSCFG
TIM1
1.8
APB
µA/MHz
15.1
16.8
11.7
5.5
TIM2
TIM3
TIM14
TIM16
7.0
TIM17
6.9
USART1
USART2
USB
17.8
5.6
4.9
WWDG
All APB peripherals
1.4
136.7
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus.
3. The power consumption of the analog part (IDDA) of peripherals such as ADC is not included. Refer to the
tables of characteristics in the subsequent sections.
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6.3.6
Wakeup time from low-power mode
The wakeup times given in Table 33 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 21: General operating conditions..
Table 33. Low-power mode wakeup timings
Typ @VDD = VDDA
Symbol
Parameter
Conditions
Max Unit
= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V
Regulator in run
mode
3.2
7.0
3.1
5.8
2.9
5.2
2.9
4.9
52
2.8
4.6
51
5
Wakeup from Stop
mode
tWUSTOP
Regulator in low
power mode
9
µs
Wakeup from
Standby mode
tWUSTANDBY
-
-
60.4
55.6
53.5
-
Wakeup from Sleep
mode
tWUSLEEP
4 SYSCLK cycles
-
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 15: High-speed external clock
source AC timing diagram.
Table 34. High-speed external user clock characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
fHSE_ext User external clock source frequency
VHSEH OSC_IN input pin high level voltage
-
8
-
32
MHz
0.7 VDDIOx
VSS
VDDIOx
V
VHSEL
OSC_IN input pin low level voltage
OSC_IN high or low time
-
0.3 VDDIOx
tw(HSEH)
tw(HSEL)
15
-
-
-
-
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
20
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Electrical characteristics
1. Guaranteed by design, not tested in production.
Figure 15. High-speed external clock source AC timing diagram
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Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 16.
Table 35. Low-speed external user clock characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
fLSE_ext User external clock source frequency
VLSEH OSC32_IN input pin high level voltage
VLSEL OSC32_IN input pin low level voltage
-
32.768
1000
VDDIOx
kHz
0.7 VDDIOx
VSS
-
-
V
0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
450
-
-
-
-
ns
tr(LSE)
OSC32_IN rise or fall time
tf(LSE)
50
1. Guaranteed by design, not tested in production.
Figure 16. Low-speed external clock source AC timing diagram
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Electrical characteristics
STM32F042x4 STM32F042x6
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 36. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 36. HSE oscillator characteristics
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
fOSC_IN Oscillator frequency
-
4
-
8
200
-
32
-
MHz
RF
Feedback resistor
-
kΩ
During startup(3)
-
8.5
VDD = 3.3 V,
Rm = 30 Ω,
CL = 10 pF@8 MHz
-
-
-
-
-
0.4
0.5
0.8
1
-
-
-
-
-
VDD = 3.3 V,
Rm = 45 Ω,
CL = 10 pF@8 MHz
VDD = 3.3 V,
IDD
HSE current consumption
mA
Rm = 30 Ω,
CL = 5 pF@32 MHz
VDD = 3.3 V,
Rm = 30 Ω,
CL = 10 pF@32 MHz
VDD = 3.3 V,
Rm = 30 Ω,
1.5
CL = 20 pF@32 MHz
gm
Oscillator transconductance
Startup time
Startup
10
-
-
-
-
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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Figure 17. Typical application with an 8 MHz crystal
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Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 37. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions(1)
Min(2) Typ Max(2) Unit
low drive capability
medium-low drive capability
medium-high drive capability
high drive capability
-
-
0.5
0.9
-
-
1
IDD
LSE current consumption
µA
-
1.3
-
-
1.6
low drive capability
5
8
15
25
-
-
-
-
-
-
-
medium-low drive capability
medium-high drive capability
high drive capability
-
Oscillator
transconductance
gm
µA/V
s
-
-
(3)
tSU(LSE)
Startup time
VDDIOx is stabilized
2
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
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STM32F042x4 STM32F042x6
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 18. Typical application with a 32.768 kHz crystal
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An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8
Internal clock source characteristics
The parameters given in Table 38 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
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High-speed internal (HSI) RC oscillator
(1)
Table 38. HSI oscillator characteristics
Symbol
Parameter
Frequency
HSI user trimming step
Conditions
Min
Typ
Max
Unit
fHSI
-
-
-
8
-
-
-
-
-
-
-
-
-
-
MHz
%
TRIM
-
1(2)
55(2)
3.8(3)
2.3(3)
2(3)
2(3)
2(3)
1
DuCy(HSI) Duty cycle
-
45(2)
-2.8(3)
-1.9(3)
-1.9(3)
-1.3(3)
-1(3)
-1
%
TA = -40 to 105°C
TA = -10 to 85°C
TA = 0 to 85°C
TA = 0 to 70°C
TA = 0 to 55°C
TA = 25°C(4)
-
Accuracy of the HSI
oscillator
ACCHSI
%
tsu(HSI)
HSI oscillator startup time
1(2)
2(2)
µs
HSI oscillator power
consumption
IDDA(HSI)
-
-
80
100(2)
µA
1. VDDA = 3.3 V, TA = -40 to 105°C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
4. Factory calibrated, parts not soldered.
Figure 19. HSI oscillator accuracy characterization results for soldered parts
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STM32F042x4 STM32F042x6
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
(1)
Table 39. HSI14 oscillator characteristics
Symbol
Parameter
Frequency
HSI14 user-trimming step
Conditions
Min
Typ
Max
Unit
fHSI14
TRIM
-
-
-
-
-
14
-
-
MHz
%
1(2)
DuCy(HSI14) Duty cycle
45(2)
-
55(2)
5.1(3)
3.1(3)
2.3(3)
1
%
TA = –40 to 105 °C –4.2(3)
TA = –10 to 85 °C –3.2(3)
-
%
-
%
Accuracy of the HSI14
oscillator (factory calibrated)
ACCHSI14
TA = 0 to 70 °C
–2.5(3)
-
%
TA = 25 °C
-
–1
-
%
tsu(HSI14) HSI14 oscillator startup time
1(2)
-
2(2)
µs
HSI14 oscillator power
IDDA(HSI14)
-
-
100 150(2)
µA
consumption
1.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Figure 20. HSI14 oscillator accuracy characterization results
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Electrical characteristics
High-speed internal 48 MHz (HSI48) RC oscillator
(1)
Table 40. HSI48 oscillator characteristics
Symbol
Parameter
Frequency
HSI48 user-trimming step
Conditions
Min
Typ
Max
Unit
fHSI48
TRIM
-
-
-
-
48
-
MHz
%
0.09(2)
45(2)
0.14
0.2(2)
55(2)
4.7(3)
3.7(3)
3.4(3)
2.9
DuCy(HSI48) Duty cycle
-
-
-
-
-
-
%
TA = –40 to 105 °C -4.9(3)
%
TA = –10 to 85 °C
TA = 0 to 70 °C
TA = 25 °C
-
-4.1(3)
-3.8(3)
-2.8
-
%
Accuracy of the HSI48
oscillator (factory calibrated)
ACCHSI48
%
%
tsu(HSI48) HSI48 oscillator startup time
6(2)
µs
HSI48 oscillator power
IDDA(HSI48)
-
-
312
350(2)
µA
consumption
1.
VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 21. HSI48 oscillator accuracy characterization results
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STM32F042x4 STM32F042x6
Low-speed internal (LSI) RC oscillator
(1)
Table 41. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI
Frequency
30
-
40
-
50
85
kHz
µs
(2)
tsu(LSI)
LSI oscillator startup time
(2)
IDDA(LSI)
LSI oscillator power consumption
-
0.75
1.2
µA
1.
VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 42. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max
PLL input clock(1)
1(2)
40(2)
16(2)
-
8.0
24(2)
60(2)
48
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
-
-
-
-
fPLL_OUT
tLOCK
MHz
µs
200(2)
300(2)
JitterPLL
Cycle-to-cycle jitter
-
ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT
.
2. Guaranteed by design, not tested in production.
6.3.10
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 105 °C unless otherwise specified.
A
Table 43. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
tprog
16-bit programming time TA = - 40 to +105 °C
40
20
20
-
53.5
60
40
40
10
12
µs
ms
ms
mA
mA
tERASE Page (1 KB) erase time TA = - 40 to +105 °C
-
-
-
-
tME
Mass erase time
TA = - 40 to +105 °C
Write mode
IDD
Supply current
Erase mode
-
1. Guaranteed by design, not tested in production.
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Electrical characteristics
Table 44. Flash memory endurance and data retention
Symbol
Parameter
Conditions
Min(1)
Unit
NEND
Endurance
TA = –40 to +105 °C
kcycle
10
30
10
20
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
10 kcycle(2) at TA = 55 °C
tRET
Data retention
Year
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709.
Table 45. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP48, TA = +25 °C,
fHCLK = 48 MHz,
conforming to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
3B
4B
Fast transient voltage burst limits to be
VDD = 3.3 V, LQFP48, TA = +25°C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 48 MHz,
pins to induce a functional disturbance
conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
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Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 46. EMI characteristics
Max vs. [fHSE/fHCLK
8/48 MHz
]
Monitored
frequency band
Symbol Parameter
Conditions
Unit
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
EMI Level
-9
9
VDD = 3.6 V, TA = 25 °C,
LQFP48 package
compliant with
dBµV
-
SEMI
Peak level
17
3
IEC 61967-2
6.3.12
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
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Maximum
Table 47. ESD absolute maximum ratings
Conditions
Symbol
Ratings
Packages Class
Unit
value(1)
Electrostatic discharge voltage TA = +25 °C, conforming
VESD(HBM)
All
All
2
2000
V
V
(human body model)
to JESD22-A114
Electrostatic discharge voltage TA = +25 °C, conforming
VESD(CDM)
C4
500
(charge device model)
to ANSI/ESD STM5.3.1
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 48. Electrical sensitivities
Symbol
Parameter
Conditions
Class
II level A
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
6.3.13
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V
(for standard, 3.3 V-capable I/O pins) should be avoided during normal
DDIOx
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 49.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
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Table 49. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
Injected current on PA12 pin
-0
-5
+5
Injected current on PA9, PB3, PB13, PF11 pins with induced
leakage current on adjacent pins less than 50 µA
NA
IINJ
mA
Injected current on PB0, PB1 and all other FT and FTf pins
Injected current on all other TC, TTa and RST pins
-5
-5
NA
+5
6.3.14
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 50. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TC and TTa I/O
FT and FTf I/O
All I/Os
-
-
0.3 VDDIOx+0.07(1)
Low level input
voltage
VIL
-
-
0.475 VDDIOx–0.2(1)
V
-
-
0.3 VDDIOx
TC and TTa I/O
FT and FTf I/O
All I/Os
0.445 VDDIOx+0.398(1)
-
-
-
-
-
-
High level input
voltage
VIH
0.5 VDDIOx+0.2(1)
-
V
0.7 VDDIOx
-
TC and TTa I/O
FT and FTf I/O
-
-
200(1)
100(1)
Schmitt trigger
hysteresis
Vhys
mV
TC, FT and FTf I/O
TTa in digital mode
VSS ≤ VIN ≤ VDDIOx
-
-
± 0.1
TTa in digital mode
VDDIOx ≤ VIN ≤ VDDA
-
-
-
-
-
-
1
Input leakage
current(2)
Ilkg
µA
TTa in analog mode
VSS ≤ VIN ≤ VDDA
± 0.2
10
FT and FTf I/O
VDDIOx ≤ VIN ≤ 5 V
Weak pull-up
RPU
equivalent resistor VIN = VSS
25
40
55
kΩ
(3)
72/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Electrical characteristics
Table 50. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Weak pull-down
equivalent
RPD
CIO
VIN = - VDDIOx
-
25
-
40
5
55
-
kΩ
resistor(3)
I/O pin capacitance
pF
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 49:
I/O current injection susceptibility.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 22 for standard I/Os, and in Figure 23 for
5 V-tolerant I/Os. The following curves are design simulation results, not tested in
production.
DocID025832 Rev 5
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89
Electrical characteristics
STM32F042x4 STM32F042x6
Figure 22. TC and TTa I/O input characteristics
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74/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed V /V ).
OL OH
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on V
, plus the maximum
DDIOx
consumption of the MCU sourced on V , cannot exceed the absolute maximum rating
DD
ΣI
(see Table 18: Voltage characteristics).
VDD
•
The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of
SS
the MCU sunk on V , cannot exceed the absolute maximum rating ΣI
(see
SS
VSS
Table 18: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).
(1)
Table 51. Output voltage characteristics
Symbol
VOL
Parameter
Conditions
Min
Max Unit
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
CMOS port(2)
|IIO| = 8 mA
VDDIOx ≥ 2.7 V
-
0.4
V
VOH
VDDIOx–0.4
-
VOL
TTL port(2)
|IIO| = 8 mA
VDDIOx ≥ 2.7 V
-
0.4
V
VOH
2.4
-
(3)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3
V
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
(3)
VOH
VDDIOx–1.3
-
(3)
VOL
-
0.4
V
-
|IIO| = 6 mA
(3)
VDDIOx ≥ 2 V
VOH
VDDIOx–0.4
-
(4)
VOL
0.4
-
V
V
|IIO| = 4 mA
(4)
VOH
VDDIOx–0.4
|IIO| = 20 mA
VDDIOx ≥ 2.7 V
-
-
0.4
0.4
V
V
Output low level voltage for an FTf I/O pin in
Fm+ mode
(3)
VOLFm+
|IIO| = 10 mA
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣI
.
IO
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
4. Data based on characterization results. Not tested in production.
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89
Electrical characteristics
STM32F042x4 STM32F042x6
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 52, respectively. Unless otherwise specified, the parameters given are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 21: General operating conditions.
(1)(2)
Table 52. I/O AC characteristics
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
ns
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
125
125
1
CL = 50 pF, VDDIOx ≥ 2 V
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
x0
MHz
ns
CL = 50 pF, VDDIOx < 2 V
CL = 50 pF, VDDIOx ≥ 2 V
CL = 50 pF, VDDIOx < 2 V
125
125
10
25
25
4
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
MHz
ns
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
01
MHz
ns
62.5
62.5
50
30
20
10
5
tr(IO)out Output rise time
CL = 30 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V
CL = 50 pF, VDDIOx < 2 V
fmax(IO)out Maximum frequency(3)
MHz
CL = 30 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V
CL = 50 pF, VDDIOx < 2 V
8
11
tf(IO)out Output fall time
12
25
5
ns
CL = 30 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, VDDIOx ≥ 2.7 V
CL = 50 pF, 2 V ≤ VDDIOx < 2.7 V
CL = 50 pF, VDDIOx < 2 V
8
tr(IO)out Output rise time
12
25
76/117
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STM32F042x4 STM32F042x6
Electrical characteristics
(1)(2)
Table 52. I/O AC characteristics
Parameter
(continued)
OSPEEDRy
[1:0] value(1)
Symbol
Conditions
Min
Max
Unit
MHz
ns
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
-
-
-
-
-
-
2
CL = 50 pF, VDDIOx ≥ 2 V
12
34
0.5
16
44
Fm+
tr(IO)out Output rise time
fmax(IO)out Maximum frequency(3)
tf(IO)out Output fall time
configuration
(4)
MHz
ns
CL = 50 pF, VDDIOx < 2 V
tr(IO)out Output rise time
Pulse width of external
tEXTIpw signals detected by the
EXTI controller
-
-
10
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a
description of GPIO Port configuration register.
2. Guaranteed by design, not tested in production.
3. The maximum frequency is defined in Figure 24.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091
for a detailed description of Fm+ I/O configuration.
Figure 24. I/O AC characteristics definition
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6.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, R
.
PU
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
Table 53. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST) NRST input low level voltage
VIH(NRST) NRST input high level voltage
-
-
-
-
-
0.3 VDD+0.07(1)
-
V
0.445 VDD+0.398(1)
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89
Electrical characteristics
STM32F042x4 STM32F042x6
Table 53. NRST pin characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
NRST Schmitt trigger voltage
hysteresis
Vhys(NRST)
-
-
200
-
mV
Weak pull-up equivalent
resistor(2)
RPU
VIN = VSS
25
40
55
kΩ
VF(NRST) NRST input filtered pulse
-
-
-
-
-
100(1)
ns
2.7 < VDD < 3.6
2.0 < VDD < 3.6
300(3)
500(3)
-
-
VNF(NRST) NRST input not filtered pulse
ns
1. Data based on design simulation only. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
3. Data based on design simulation only. Not tested in production.
Figure 25. Recommended NRST pin protection
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1. The external capacitor protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
6.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 54. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage for
ADC ON
VDDA
-
2.4
-
3.6
V
Current consumption of
the ADC(1)
IDDA (ADC)
fADC
VDDA = 3.3 V
-
0.9
-
mA
ADC clock frequency
Sampling rate
-
0.6
-
-
14
1
MHz
MHz
(2)
fS
12-bit resolution
0.043
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DocID025832 Rev 5
STM32F042x4 STM32F042x6
Electrical characteristics
Table 54. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fADC = 14 MHz,
12-bit resolution
-
-
823
kHz
(2)
External trigger frequency
fTRIG
12-bit resolution
-
-
-
-
17
1/fADC
V
VAIN
Conversion voltage range
External input impedance
0
VDDA
See Equation 1 and
Table 55 for details
(2)
RAIN
-
-
-
-
-
-
50
1
kΩ
kΩ
pF
Sampling switch
resistance
(2)
-
-
RADC
Internal sample and hold
capacitor
(2)
8
CADC
f
ADC = 14 MHz
5.9
83
µs
(2)(3)
Calibration time
tCAL
-
1/fADC
1.5 ADC
cycles + 3
fPCLK cycles
1.5 ADC
cycles + 2
fPCLK cycles
ADC clock = HSI14
-
-
ADC_DR register ready
latency
(2)(4)
WLATENCY
fPCLK
cycle
ADC clock = PCLK/2
ADC clock = PCLK/4
-
-
4.5
8.5
-
-
fPCLK
cycle
fADC = fPCLK/2 = 14 MHz
fADC = fPCLK/2
0.196
5.5
µs
1/fPCLK
µs
(2)
Trigger conversion latency fADC = fPCLK/4 = 12 MHz
fADC = fPCLK/4
0.219
10.5
-
tlatr
1/fPCLK
µs
fADC = fHSI14 = 14 MHz
0.179
-
0.250
-
ADC jitter on trigger
fADC = fHSI14
JitterADC
1
1/fHSI14
conversion
f
ADC = 14 MHz
0.107
1.5
-
-
17.1
µs
(2)
Sampling time
tS
-
-
239.5
1/fADC
1/fADC
(2)
tSTAB
Stabilization time
14
f
ADC = 14 MHz,
1
-
18
µs
12-bit resolution
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
12-bit resolution
1/fADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD should be taken into account.
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
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89
Electrical characteristics
Equation 1: R
STM32F042x4 STM32F042x6
max formula
AIN
TS
RAIN < --------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 55. R
max for f
tS (µs)
= 14 MHz
ADC
AIN
Ts (cycles)
RAIN max (kΩ)(1)
1.5
7.5
0.11
0.54
0.96
2.04
2.96
3.96
5.11
17.1
0.4
5.9
13.5
28.5
41.5
55.5
71.5
239.5
11.4
25.2
37.2
50
NA
NA
1. Guaranteed by design, not tested in production.
(1)(2)(3)
Table 56. ADC accuracy
Symbol
Parameter
Test conditions
Typ
Max(4)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±1.3
±1
±2
±1.5
±1.5
±1
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
VDDA = 3 V to 3.6 V
TA = 25 °C
Gain error
±0.5
±0.7
±0.8
±3.3
±1.9
±2.8
±0.7
±1.2
±3.3
±1.9
±2.8
±0.7
±1.2
LSB
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
±1.5
±4
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
±2.8
±3
Gain error
LSB
LSB
VDDA = 2.7 V to 3.6 V
TA = - 40 to 105 °C
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
±1.3
±1.7
±4
ET
EO
EG
ED
EL
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 kΩ
±2.8
±3
Gain error
VDDA = 2.4 V to 3.6 V
TA = 25 °C
Differential linearity error
Integral linearity error
±1.3
±1.7
1. ADC DC accuracy values are measured after internal calibration.
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STM32F042x4 STM32F042x6
Electrical characteristics
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
Figure 26. ADC accuracy characteristics
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1. Refer to Table 54: ADC characteristics for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 13: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
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89
Electrical characteristics
STM32F042x4 STM32F042x6
6.3.17
Temperature sensor characteristics
Table 57. TS characteristics
Symbol
Parameter
VSENSE linearity with temperature
Avg_Slope(1) Average slope
Min
Typ
Max
Unit
(1)
TL
-
4.0
1.34
-
± 1
4.3
1.43
-
± 2
4.6
°C
mV/°C
V
V30
Voltage at 30 °C (± 5 °C)(2)
1.52
10
(1)
(1)
tSTART
ADC_IN16 buffer startup time
µs
ADC sampling time when reading the
temperature
tS_temp
4
-
-
µs
1. Guaranteed by design, not tested in production.
2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:
Temperature sensor calibration values.
6.3.18
V
monitoring characteristics
BAT
Table 58. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
2 x 50
-
-
kΩ
-
Ratio on VBAT measurement
Error on Q
2
-
Er(1)
–1
4
+1
-
%
µs
(1)
tS_vbat
ADC sampling time when reading the VBAT
-
1. Guaranteed by design, not tested in production.
6.3.19
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 59. TIMx characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tTIMxCLK
ns
-
-
-
-
1
-
-
-
tres(TIM)
Timer resolution time
fTIMxCLK = 48 MHz
-
20.8
Timer external clock
frequency on CH1 to
CH4
fTIMxCLK/2
MHz
fEXT
fTIMxCLK = 48 MHz
-
24
-
MHz
216
tTIMxCLK
-
-
-
-
-
-
-
-
-
16-bit timer maximum
period
fTIMxCLK = 48 MHz
-
1365
µs
tMAX_COUNT
232
tTIMxCLK
32-bit counter
maximum period
fTIMxCLK = 48 MHz
89.48
s
82/117
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STM32F042x4 STM32F042x6
Electrical characteristics
(1)
Table 60. IWDG min/max timeout period at 40 kHz (LSI)
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Prescaler divider PR[2:0] bits
Unit
/4
/8
0
0.1
0.2
0.4
0.8
1.6
3.2
6.4
409.6
819.2
1
/16
/32
/64
/128
/256
2
1638.4
3276.8
6553.6
13107.2
26214.4
3
4
ms
5
6 or 7
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 61. WWDG min/max timeout value at 48 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
2
4
8
0
1
2
3
0.0853
0.1706
0.3413
0.6826
5.4613
10.9226
21.8453
43.6906
ms
6.3.20
Communication interfaces
I2C interface characteristics
2
2
The I C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
2
The I C timings requirements are guaranteed by design when the I2Cx peripheral is
properly configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
is disabled, but is still present. Only FTf I/O pins
DDIOx
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
2
port characteristics for the I C I/Os characteristics.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
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89
Electrical characteristics
STM32F042x4 STM32F042x6
2
(1)
Table 62. I C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum width of spikes that are
suppressed by the analog filter
tAF
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI/I2S characteristics
2
Unless otherwise specified, the parameters given in Table 63 for SPI or in Table 64 for I S
are derived from tests performed under the ambient temperature, f frequency and
PCLKx
supply voltage conditions summarized in Table 21: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
2
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).
(1)
Table 63. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
-
-
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 15 pF
-
6
ns
ns
%
tsu(NSS)
th(NSS)
tw(SCKH)
NSS setup time
NSS hold time
Slave mode
Slave mode
4Tpclk
-
-
2Tpclk + 10
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
Data input setup time
Tpclk/2 -2
Tpclk/2 + 1
tw(SCKL)
Master mode
Slave mode
Master mode
Slave mode
4
5
-
tsu(MI)
tsu(SI)
-
th(MI)
th(SI)
4
-
Data input hold time
5
-
(2)
ta(SO)
Data output access time Slave mode, fPCLK = 20 MHz
Data output disable time Slave mode
0
3Tpclk
(3)
tdis(SO)
0
18
tv(SO)
tv(MO)
th(SO)
th(MO)
Data output valid time
Data output valid time
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
-
22.5
-
6
-
11.5
2
Data output hold time
-
SPI slave input clock
duty cycle
DuCy(SCK)
Slave mode
25
75
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
84/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Electrical characteristics
Figure 28. SPI timing diagram - slave mode and CPHA = 0
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Figure 29. SPI timing diagram - slave mode and CPHA = 1
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
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89
Electrical characteristics
STM32F042x4 STM32F042x6
Figure 30. SPI timing diagram - master mode
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD
.
2
(1)
Table 64. I S characteristics
Conditions
Symbol
Parameter
Min
Max
Unit
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
1.597
1.601
fCK
1/tc(CK)
I2S clock frequency
MHz
Slave mode
0
-
6.5
tr(CK)
tf(CK)
I2S clock rise time
I2S clock fall time
I2S clock high time
I2S clock low time
WS valid time
10
12
-
Capacitive load CL = 15 pF
-
tw(CKH)
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
306
312
2
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
-
ns
%
Master mode
Master mode
Slave mode
Slave mode
-
WS hold time
2
-
WS setup time
7
-
WS hold time
0
-
I2S slave input clock duty
cycle
DuCy(SCK)
Slave mode
25
75
86/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Electrical characteristics
2
(1)
Table 64. I S characteristics (continued)
Parameter Conditions
Master receiver
Symbol
Min
Max
Unit
tsu(SD_MR)
tsu(SD_SR)
6
2
-
-
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Slave receiver
(2)
th(SD_MR)
Master receiver
Slave receiver
4
-
(2)
th(SD_SR)
0.5
-
-
ns
(2)
tv(SD_MT)
Master transmitter
Slave transmitter
Master transmitter
Slave transmitter
4
20
-
(2)
tv(SD_ST)
th(SD_MT)
th(SD_ST)
-
0
13
-
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns.
2
Figure 31. I S slave timing diagram (Philips protocol)
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1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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89
Electrical characteristics
STM32F042x4 STM32F042x6
2
Figure 32. I S master timing diagram (Philips protocol)
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06Yꢀꢓꢂꢇꢋ9ꢁ
1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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DocID025832 Rev 5
STM32F042x4 STM32F042x6
USB characteristics
Electrical characteristics
The STM32F042x4/x6 USB interface is fully compliant with the USB specification version
2.0 and is USB-IF certified (for Full-speed device operation).
Table 65. USB electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ
Max.
Unit
USB transceiver operating
voltage
VDDIO2
-
-
-
3.0(1)
-
-
-
3.6
1.0
1.5
V
(2)
tSTARTUP
USB transceiver startup time
µs
Embedded USB_DP pull-up
value during idle
RPUI
1.1
1.26
kΩ
Embedded USB_DP pull-up
value during reception
RPUR
-
2.0
28
2.26
40
2.6
44
Driving high
and low
(2)
ZDRV
Output driver impedance(3)
Ω
1. The STM32F042x4/x6 USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V voltage range.
2. Guaranteed by design, not tested in production.
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
DocID025832 Rev 5
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89
Package information
STM32F042x4 STM32F042x6
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
7.1
LQFP48 package information
LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
Figure 33. LQFP48 package outline
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1. Drawing is not to scale.
90/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Package information
inches(1)
Table 66. LQFP48 package mechanical data
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
A1
A2
b
0.050
1.350
0.170
0.090
8.800
6.800
-
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 34. Recommended footprint for LQFP48 package
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1. Dimensions are expressed in millimeters.
DocID025832 Rev 5
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113
Package information
STM32F042x4 STM32F042x6
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 35. LQFP48 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
92/117
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STM32F042x4 STM32F042x6
Package information
7.2
UFQFPN48 package information
UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 36. UFQFPN48 package outline
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1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
DocID025832 Rev 5
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113
Package information
STM32F042x4 STM32F042x6
Table 67. UFQFPN48 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 37. Recommended footprint for UFQFPN48 package
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1. Dimensions are expressed in millimeters.
94/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 38. UFQFPN48 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID025832 Rev 5
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113
Package information
STM32F042x4 STM32F042x6
7.3
WLCSP36 package information
WLCSP36 is a 36-ball, 2.605 x 2.703 mm, 0.4 mm pitch wafer-level chip-scale package.
Figure 39. WLCSP36 package outline
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1. Drawing is not to scale.
Table 68. WLCSP36 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3(2)
b(3)
D
0.525
0.555
0.175
0.380
0.025
0.250
2.605
2.703
0.400
2.000
2.000
0.585
0.0207
0.0219
0.0069
0.0150
0.0010
0.0098
0.1026
0.1064
0.0157
0.0787
0.0787
0.0230
-
-
-
-
-
-
-
-
-
-
-
-
0.220
0.280
0.0087
0.0110
2.570
2.640
0.1012
0.1039
E
2.668
2.738
0.1050
0.1078
e
-
-
-
-
-
-
-
-
-
-
-
-
e1
e2
96/117
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STM32F042x4 STM32F042x6
Package information
Table 68. WLCSP36 package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
F
-
-
-
-
-
-
-
0.3025
-
-
-
-
-
-
-
-
0.0119
-
G
0.3515
-
0.0138
-
aaa
bbb
ccc
ddd
eee
-
-
-
-
-
0.100
0.100
0.100
0.050
0.050
-
-
-
-
-
0.0039
0.0039
0.0039
0.0020
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 40. Recommended pad footprint for WLCSP36 package
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Table 69. WLCSP36 recommended PCB design rules
Dimension
Recommended values
Pitch
Dpad
Dsm
0.4 mm
260 µm max. (circular)
220 µm recommended
300 µm min. (for 260 µm diameter pad)
PCB pad design
Non-solder mask defined via underbump allowed
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113
Package information
STM32F042x4 STM32F042x6
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 41. WLCSP36 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
98/117
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STM32F042x4 STM32F042x6
Package information
7.4
LQFP32 package information
LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.
Figure 42. LQFP32 package outline
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1. Drawing is not to scale.
DocID025832 Rev 5
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Package information
STM32F042x4 STM32F042x6
Table 70. LQFP32 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.300
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.450
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
-
-
-
1.400
0.370
-
0.0551
0.0146
-
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 43. Recommended footprint for LQFP32 package
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1. Dimensions are expressed in millimeters.
100/117
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STM32F042x4 STM32F042x6
Device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 44. LQFP32 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
7.5
UFQFPN32 package information
UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package.
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Package information
STM32F042x4 STM32F042x6
Figure 45. UFQFPN32 package outline
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1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device
ground and must be connected. It is referred to as pin 0 in Table: Pin definitions.
102/117
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STM32F042x4 STM32F042x6
Package information
Table 71. UFQFPN32 package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A3
b
0.500
0.000
-
0.550
0.020
0.152
0.230
5.000
3.500
3.500
5.000
3.500
3.500
0.500
0.400
-
0.600
0.050
-
0.0197
0.0000
-
0.0217
0.0008
0.0060
0.0091
0.1969
0.1378
0.1378
0.1969
0.1378
0.1378
0.0197
0.0157
-
0.0236
0.0020
-
0.180
4.900
3.400
3.400
4.900
3.400
3.400
-
0.280
5.100
3.600
3.600
5.100
3.600
3.600
-
0.0071
0.1929
0.1339
0.1339
0.1929
0.1339
0.1339
-
0.0110
0.2008
0.1417
0.1417
0.2008
0.1417
0.1417
-
D
D1
D2
E
E1
E2
e
L
0.300
-
0.500
0.080
0.0118
-
0.0197
0.0031
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 46. Recommended footprint for UFQFPN32 package
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1. Dimensions are expressed in millimeters.
DocID025832 Rev 5
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113
Package information
STM32F042x4 STM32F042x6
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 47. UFQFPN32 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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STM32F042x4 STM32F042x6
Package information
7.6
UFQFPN28 package information
UFQFPN28 is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 48. UFQFPN28 package outline
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1. Drawing is not to scale.
(1)
Table 72. UFQFPN28 package mechanical data
millimeters
Typ
inches
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
-
0.550
0.000
4.000
3.000
4.000
3.000
0.400
0.350
0.152
0.250
0.500
0.600
0.050
4.100
3.100
4.100
3.100
0.500
0.450
-
0.0197
-
0.0217
0.0000
0.1575
0.1181
0.1575
0.1181
0.0157
0.0138
0.0060
0.0098
0.0197
0.0236
0.0020
0.1614
0.1220
0.1614
0.1220
0.0197
0.0177
-
3.900
2.900
3.900
2.900
0.300
0.250
-
0.1535
0.1142
0.1535
0.1142
0.0118
0.0098
-
D1
E
E1
L
L1
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
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Package information
STM32F042x4 STM32F042x6
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 49. Recommended footprint for UFQFPN28 package
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1. Dimensions are expressed in millimeters.
106/117
DocID025832 Rev 5
STM32F042x4 STM32F042x6
Device marking
Package information
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 50. UFQFPN28 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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113
Package information
STM32F042x4 STM32F042x6
7.7
TSSOP20 package information
TSSOP20 is a 20-lead thin shrink small-outline, 6.5 x 4.4 mm, 0.65 mm pitch, package.
Figure 51.TSSOP20 package outline
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1. Drawing is not to scale.
Table 73. TSSOP20 package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.200
0.150
1.050
0.300
0.200
6.600
6.600
4.500
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.2598
0.2598
0.1772
-
0.050
0.800
0.190
0.090
6.400
6.200
4.300
-
-
0.0020
0.0315
0.0075
0.0035
0.2520
0.2441
0.1693
-
-
1.000
-
0.0394
-
c
-
-
D(2)
6.500
6.400
4.400
0.650
0.600
0.2559
0.2520
0.1732
0.0256
0.0236
E
E1(3)
e
L
0.450
0.750
0.0177
0.0295
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STM32F042x4 STM32F042x6
Package information
Table 73. TSSOP20 package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
L1
k
-
0°
-
1.000
-
-
0°
-
0.0394
-
-
-
8°
-
-
8°
aaa
0.100
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
Figure 52. Recommended footprint for TSSOP20 package
ꢋꢈꢇꢎ
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1. Dimensions are expressed in millimeters.
DocID025832 Rev 5
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113
Package information
STM32F042x4 STM32F042x6
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 53. TSSOP20 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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STM32F042x4 STM32F042x6
Package information
7.8
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 21: General operating conditions.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ ((V
– V ) × I ),
DDIOx OH OH
I/O
OL
OL
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 74. Package thermal characteristics
Parameter
Symbol
Value
Unit
Thermal resistance junction-ambient
LQFP48 - 7 mm x 7 mm
55
Thermal resistance junction-ambient
UFQFPN48 - 7 mm x 7 mm
33
64
Thermal resistance junction-ambient
WLCSP36 2.6 mm x 2.7 mm
Thermal resistance junction-ambient
LQFP32 - 7 mm x 7 mm
ΘJA
57
°C/W
Thermal resistance junction-ambient
UFQFPN32 - 5 mm x 5 mm
38
Thermal resistance junction-ambient
UFQFPN28 - 4 mm x 4 mm
118
76
Thermal resistance junction-ambient
TSSOP20 - 6.5 mm x 6.4 mm
7.8.1
7.8.2
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
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Package information
STM32F042x4 STM32F042x6
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F042x4/x6 at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
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STM32F042x4 STM32F042x6
Ordering information
8
Ordering information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Table 75. Ordering information scheme
Example:
STM32
F
042
C
6
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
042 = STM32F042xx
Pin count
F = 20 pins
G = 28 pins
K = 32 pins
T = 36 pins
C = 48 pins
User code memory size
4 = 16 Kbyte
6 = 32 Kbyte
Package
P = TSSOP
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = –40 to 85 °C
7 = –40 to 105 °C
Options
xxx = code ID of programmed parts (includes packing type)
TR = tape and reel packing
blank = tray packing
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Revision history
STM32F042x4 STM32F042x6
9
Revision history
Table 76. Document revision history
Changes
Date
Revision
25-Feb-2014
1
Initial release.
Added the sample engineering sections for all the packages in the
chapter Package information:
Updated tables:
– STM32F042x4/x6 USART implementation: added one table
footnote.
– STM32F042x pin definitions,
– Current characteristics,
– Typical and maximum current consumption from VDD supply at VDD
= 3.6 V,
– Typical and maximum current consumption from the VDDA supply,
– Typical and maximum consumption in Stop and Standby modes,
– Typical and maximum current consumption from the VBAT supply,
– Typical current consumption, code executing from Flash, running
from HSE 8 MHz crystal,
– Flash memory characteristics,
– I/O static characteristics,
03-Apr-2014
2
– I/O current injection susceptibility,
– EMS characteristics,
– EMI characteristics,
Updated figures:
– UFQFPN32 32-pin package pinout,
– UQFPN28 28-pin package,
– Power supply scheme,
– TC and TTa I/O input characteristics,
– Five volt tolerant (FT and FTf) I/O input characteristics.
– LQFP48 marking example (package top view),
– UFQFPN48 marking example (package top view),
– WLCSP36 marking example (package top view),
– LQFP32 marking example (package top view),
– UFQFPN28 marking example (package top view),
– UFQFPN32 marking example (package top view),
– TSSOP20 marking example (package top view)
Cover page: number of I/Os and timers updated.
Updates in Section 2: Description:
– updated Figure 1: Block diagram
Updates in Section 3: Functional overview:
– updated Figure 2: Clock tree
26-Oct-2015
3
– addition of the number of complementary outputs for the advanced
control timer and for TIM16, TIM17 general purpose timers in
Table 7: Timer feature comparison
– removal of USART2 from Figure 3.5.4: Low-power modes
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Revision history
Table 76. Document revision history (continued)
Revision Changes
Date
– Table 9: STM32F042x4/x6 I2C implementation - adding 20 mA
Updates in Section 4: Pinouts and pin descriptions
– Table 12: Legend/abbreviations used in the pinout table - removing
“I” pin type
Updates in Section 5: Memory mapping:
– Figure 10: STM32F042x6 memory map, x4 difference described in
text
Updates in Section 6: Electrical characteristics:
– the condition “Regulator in run mode, all oscillators OFF” in Table 28:
Typical and maximum consumption in Stop and Standby modes,
– footnote for VIN max value in Table 18: Voltage characteristics,
– footnote for max VIN in Table 21: General operating conditions,
– tSTART parameter definition in Table 25: Embedded internal
reference voltage
– addition of tSTART parameter in Table 25: Embedded internal
reference voltage, removal of -40°C to 85°C condition and the
associated footnote
– Table 26: Typical and maximum current consumption from VDD
supply at VDD = 3.6 V: removing “code executing from Flash or
RAM”
– removal of the min value for tSTART parameter in Table 57: TS
characteristics
26-Oct-2015
3
– the typical value for R parameter in Table 58: VBAT monitoring
characteristics
– removal of ResTM parameter line from Table 59: TIMx characteristics
and putting all values in new Typ column, substitution of tCOUNTER
with tMAX_COUNT, values defined as powers of two
– VESD(CDM) class in Table 47: ESD absolute maximum ratings
– reorganization of Table 64: I2S characteristics and filling max value
of tv(SD_ST)
– adding definition of levels in Figure 32: I2S master timing diagram
(Philips protocol)
Updates in Section 7: Package information:
– heading and display of columns in Table 68: WLCSP36 package
mechanical data.,
– Figure 38: UFQFPN48 package marking example
– Figure 41: WLCSP36 package marking example
– Figure 50: UFQFPN28 package marking example
– Figure 41: WLCSP36 package marking example
– Figure 51: TSSOP20 package outline - correcting GAGE to GAUGE
– removing “die 445” from Table 74: Package thermal characteristics
Updates in Section 8: Part numbering:
– adding tray packing to options
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Revision history
STM32F042x4 STM32F042x6
Table 76. Document revision history (continued)
Date
Revision
Changes
Section 3: Functional overview:
– Figure 2: Clock tree modified
Section 4: Pinouts and pin descriptions:
– Package pinout figures updated (look and feel)
– Figure 5: WLCSP36 package pinout- now presented in top view
– Table 13: STM32F042x pin definitions - note 3 added; CIMP1_OUT
and USART4_CTS removed
– Table 15: Alternate functions selected through GPIOB_AFR
registers for port B - change of I2C2_SDA and I2C2_SCL to
I2C1_SDA and I2C1_SCL
16-Dec-2015
4
Section 5: Memory mapping:
– Table 17: STM32F042x4/x6 peripheral register boundary addresses
- change of “SYSCFG + COMP” to “SYSCFG”
Section 6: Electrical characteristics:
– Table 50: I/O static characteristics- removed note
– Section 6.3.16: 12-bit ADC characteristics - changed introductory
sentence
Section 7: Package information:
– Figure 49: Recommended footprint for UFQFPN28 package
distance between corner pads added
Section 6: Electrical characteristics:
– Table 37: LSE oscillator characteristics (fLSE = 32.768 kHz) -
information on configuring different drive capabilities removed. See
the corresponding reference manual.
– Table 25: Embedded internal reference voltage - VREFINT values
10-Jan-2017
5
– Figure 28: SPI timing diagram - slave mode and CPHA = 0 and
Figure 29: SPI timing diagram - slave mode and CPHA = 1
enhanced and corrected
Section 8: Ordering information:
– The name of the section changed from the previous “Part
numbering”
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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