STHDLS101 [STMICROELECTRONICS]
AC coupled HDMI level shifter; AC耦合HDMI电平转换器
| 型号： | STHDLS101 |
| 厂家： | 
ST |
| 描述： | AC coupled HDMI level shifter |
| 文件： | 总25页 (文件大小：488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STHDLS101
AC coupled HDMI level shifter
Features
■ Converts low-swing alternating current (AC)
coupled differential input to high-definition
multimedia interface (HDMI) rev 1.3 compliant
■ HDMI level shifting operation up to 2.7 Gbps
per lane
■ Integrated 50 Ω termination resistors for
AC-coupled differential inputs
■ Input/output transition minimized differential
QFN-48
signaling (TMDS) enable/disable
(7 x 7 mm)
■ Output slew rate control on TMDS outputs to
minimize electromagnetic interference (EMI)
■ Fail-safe outputs for backdrive protection
■ No re-timing or configuration required
■ Inter-pair output skew < 250 ps
Description
■ Intra-pair output skew < 10 ps
The STHDLS101 is a high-speed high-definition
multimedia interface (HDMI) level shifter that
converts low-swing AC coupled differential input
to HDMI 1.3 compliant open-drain current
steering RX-terminated differential output.
Through the existing PCI-E pins in the graphics
and memory controller hub (GMCH) of PCs or
notebook motherboards, the pixel clock provides
the required bandwidth (1.±5 Gbps, 2.25 Gbps)
for the video supporting 720p, 1080i, 1080p with a
total of 3±-bit resolution. The HDMI is multiplexed
onto the PCIe pins in the motherboard where the
AC coupled HDMI at 1.2 V is output by GMCH.
The AC coupled HDMI is then level shifter by this
device to 3.3 V DC coupled HDMI output. The
STHDLS101 supports up to 2.7 Gbps, which is
enough for 12 bits of color depth per channel, as
indicated in HDMI rev 1.3. The device operates
from a single 3.3 V supply and is available in a
48-pin QFN package.
■ Single power supply of 3.3 V
■ ESD protection: ±± KV HBM on all I/O pins
■ Integrated display data channel (DDC) level
shifters. Pass-gate voltage limiters allow 3.3 V
termination on graphics and memory controller
hub (GMCH) pins and 5 V DDC termination on
HDMI connector pins
■ Hot-plug detect (HPD) signal level shifter from
HDMI/DVI connector
■ Integrated pull-down resistor on HPD_SINK
and OE_N inputs
Applications
■ Notebooks
■ PC motherboards and graphic cards
■ Dongles/cable adapters
Table 1.
Device summary
Order code
Package
Packing
STHDLS101QTR
QFN-48
Tape and reel
December 2008
Rev 4
1/25
www.st.com
25
Contents
STHDLS101
Contents
1
2
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1
5.1.2
Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
5.3
5.4
5.5
5.±
5.7
TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1±
DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
±.1
±.2
±.3
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/25
STHDLS101
Block diagram
1
Block diagram
Figure 1.
STHDLS101 block diagram
3/25
System interface
STHDLS101
2
System interface
Figure 2.
System inferface
PCI-Express
SDVO
HDMI
Graphics chipset
Level shifter
STHDLS101
HDMI output
connector
(GMCH) on the
motherboard
CS00374
Figure 3.
Cable adapter
($-)ꢅ$6)
$ONGLE OR
ADAPTER
CABLE
ꢄꢀꢄ
34($,3
$0
!-ꢀꢀꢁꢂꢃ6ꢄ
4/25
STHDLS101
System interface
Figure 4.
DP to HDMI/DVI cable adapter
HPD_SINK
HPD
HPD_SOURCE
HDMI/DVI
Transmitter
DC TMDS
DDC
STHDLS101
HDMI/DVI Cable
Adaptor
AC_TMDS
DDC
AC_TMDS
DDC
PC chipset
!-ꢀꢀꢁꢂꢆ6ꢄ
5/25
Pin configuration
STHDLS101
3
Pin configuration
Figure 5.
STHDLS101 pin configuration
GND
24
23
22
GND
37
OUT_D1-
OUT_D1+
VCC33
IN_D1-
38
IN_D1+
39
21
20
19
VCC33
40
OUT_D2-
OUT_D2+
IN_D2-
41
IN_D2+
QFN-48
42
GND
18
GND
43
17
OUT_D3-
OUT_D3+
VCC33
IN_D3-
44
1±
15
14
13
IN_D3+
45
VCC33
4±
OUT_D4-
OUT_D4+
IN_D4-
47
IN_D4+
48
CS000118
±/25
STHDLS101
Pin configuration
3.1
Pin description
Table 2.
Pin description
Pin
number
Name
Type
Function
1
2
GND
Power
Power
Ground
VCC33
3.3 V±10% DC supply
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
control or test
pins
For normal operation, these pins are tied to GND or
VCC33.
3
FUNCTION1
For consistent interoperability, GND is the preferred
default connection for these signals.
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
control or test
pins
For normal operation, these pins are tied to GND or
VCC33.
4
5
FUNCTION2
GND
For consistent interoperability, GND is the preferred
default connection for these signals.
Power
Ground
Connection to external resistor. Resistor value
specified by device manufacturer.
Acceptable connections to this pin are:
6
REXT
Analog
- Resistor to GND
- Resistor to 3.3 V
- NC (direct connections to VCC or GND are through a
0 Ω resistor for layout compatibility
0 to 3.3 V (nominal) output signal. This is level-shifted
version of the HPD_SINK signal.
7
8
HPD_SOURCE
SDA_SOURCE
Output
I/O
3.3 V DDC data I/O. Pulled-up by external termination
to 3.3 V. Connected to SDA_SINK through voltage-
limiting integrated NMOS pass-gate.
3.3 V DDC clock I/O. Pulled-up by external termination
to 3.3 V. Connected to SCL_SINK through voltage-
limiting integrated NMOS pass-gate.
9
SCL_SOURCE
ANALOG2
Input
Analog connection determined by vendor. Acceptable
connections to this pin are:
- Resistor or capacitor to GND
- Resistor or capacitor to 3.3 V
- Short to 3.3 V or to GND
- NC
10
Analog
11
12
VCC33
GND
Power
Power
3.3 V ±10% DC supply
Ground
HDMI 1.3 compliant TMDS output.
OUT_D4+ makes a differential output signal with
OUT_D4-.
13
OUT_D4+
Output
7/25
Pin configuration
Table 2.
STHDLS101
Pin description (continued)
Pin
number
Name
Type
Function
HDMI 1.3 compliant TMDS output.
14
15
1±
OUT_D4-
VCC33
Output
Power
Output
OUT_D4- makes a differential output signal with
OUT_D4+.
3.3 V±10% DC supply
HDMI 1.3 compliant TMDS output.
OUT_D3+ makes a differential output signal with
OUT_D3-.
OUT_D3+
HDMI 1.3 compliant TMDS output.
OUT_D3- makes a differential output signal with
OUT_D3+.
17
18
19
OUT_D3-
GND
Output
Power
Output
Ground
HDMI 1.3 compliant TMDS output.
OUT_D2+ makes a differential output signal with
OUT_D2-.
OUT_D2+
HDMI 1.3 compliant TMDS output.
OUT_D2- makes a differential output signal with
OUT_D2+.
20
OUT_D2-
Output
21
22
VCC33
Power
Output
3.3 V±10% DC supply
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-.
OUT_D1+
HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+.
23
24
OUT_D1-
GND
Output
Power
Ground
Enable for level shifter path. 3.3 V tolerant low-voltage
single-ended input. Internal pull-down enables the
device when unconnected.
IN_D
termination
OUT_D
Outputs
25
OE_N
Input
OE_N
1
0
High-Z
High-Z
Active
50Ω
2±
27
VCC33
GND
Power
Power
3.3 V±10% DC supply
Ground
5 V DDC clock I/O. Pulled-up by external termination to
5 V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS pass-gate.
28
29
SCL_SINK
SDA_SINK
Output
I/O
5V DDC data I/O. Pulled-up by external termination to
5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS pass-gate.
8/25
STHDLS101
Pin configuration
Table 2.
Pin description (continued)
Pin
number
Name
Type
Function
Low-frequency, 0 to 5 V (nominal) input signal. This
signal comes from the HDMI connector. Voltage high
indicates “plugged” state; voltage low indicates
“unplugged” state. HPD_SINK is pulled down by an
integrated 160 KΩ pull-down resistor.
30
31
HPD_SINK
GND
Input
Power
Ground
Enables bias voltage to the DDC pass-gate level shifter
gates. (May be implemented as a bias voltage
connection to the DDC pass-gate themselves).
32
DDC_EN
Input
DDC_EN
Pass-gate
0 V
Disabled
Enabled
3.3 V
33
34
VCC33
Power
3.3 V ± 10% DC supply
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
control or test
pins
For normal operation, these pins are tied to GND or
VCC33.
FUNCTION3
For consistent interoperability, GND is the preferred
default connection for these signals.
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
control or test
pins
For normal operation, these pins are tied to GND or
VCC33.
35
FUNCTION4
For consistent interoperability, GND is the preferred
default connection for these signals.
3±
37
GND
GND
Power
Power
Ground
Ground
Low-swing differential input from GMCH PCIE outputs.
IN_D1- makes a differential pair with IN_D1+.
38
IN_D1-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1-.
39
40
41
IN_D1+
VCC33
IN_D2-
Input
Power
Input
3.3 V±10% DC supply
Low-swing differential input from GMCH PCIE outputs.
IN_D2- makes a differential pair with IN_D2+.
Low-swing differential input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2-.
42
43
44
IN_D2+
GND
Input
Power
Input
Ground
Low-swing differential input from GMCH PCIE outputs.
IN_D3- makes a differential pair with IN_D3+.
IN_D3-
Low-swing differential input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3-.
45
IN_D3+
Input
9/25
Pin configuration
Table 2.
STHDLS101
Pin description (continued)
Pin
number
Name
Type
Function
4±
47
VCC33
IN_D4-
Power
Input
3.3 V±10% DC supply
Low-swing differential input from GMCH PCIE outputs.
IN_D4- makes a differential pair with IN_D4+.
Low-swing differential input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4-.
48
IN_D4+
Input
10/25
STHDLS101
Functional description
4
Functional description
This section describes the basic functionality of the STHDLS101 device.
Power supply
The STHDLS101 is powered by a single DC power supply of 3.3 V ± 10%.
Clocking
This device does not retime any data. The device contains no state machines. No inputs or
outputs of the device are latched or clocked.
Reset
This device acts as a level shifter, reset is not required.
OE_N function
When OE_N is asserted (low level), the IN_D and OUT_D signals are fully functional. Input
termination resistors are enabled and any internal bias circuits are turned on.
The OE_N pin has an internal pull-down that enables the chip if left unconnected.
When OE_N is de-asserted (high level), the OUT_D outputs are in high impedance state.
The IN_D input buffers are disabled and the IN_D termination resistors are disabled.
Internal bias circuits for the differential inputs and outputs are turned off. Power consumption
of the chip is minimized.
The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and
SDA pass-gates are not affected by OE_N.
Table 3.
OE_N
OE_N description
Device state
Comments
Asserted
(low level)
Differential input buffers and output
buffers enabled. Input impedance =
50 Ω
Normal functioning state for IN_D to
OUT_D level shifting function.
or unconnected
Intended for lowest power condition
when:
Low-power state.
Differential input buffers and
terminations are disabled. Differential
input buffers are in high-impedance
state.
• No display is plugged in or
• The level shifted data path is disabled
HPD_SINK input and HPD_SOURCE
output are not affected by OE_N.
De-asserted
(high level)
OUT_D level shifting outputs are
disabled. OUT_D level shifting outputs
are in a high-impedance state.
SCL_SOURCE, SCL_SINK,
SDA_SOURCE and SDA_SINK signals
and functions are not affected by OE_N.
Internal bias currents are turned off.
11/25
Functional description
Table 4.
STHDLS101
OE_N function
OE_N
OUT_Dx
(TMDS outputs)
IN_Dx
Notes
Device disabled.
Low power state.
Internal bias currents are
disabled.
De-asserted
(high level)
High-Z
High-Z
Asserted
(low level) or
unconnected
Level shifting mode
enabled.
50 Ω termination
Enabled
12/25
STHDLS101
Maximum ratings
5
Maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
VI
Supply voltage to ground potential
DC input voltage (TMDS and PCIe ports)
Control pins
-0.5 to +4.0
-0.5 to +4.0
-0.5 to +4.0
-0.5 to +±
120
V
V
V
SDA_SINK, SCL_SINK, HPD_SINK pins
DC output current
V
IO
mA
W
°C
°C
PD
Power dissipation
1
TSTG Storage temperature
-±5 to +150
300
TL
Lead temperature (10 sec)
Electrostatic discharge
VESD
Human body model
±±
kV
voltage on IOs(1)
1. In accordance with the MIL standard 883 method 3015
Table 6.
Symbol
θJA
Thermal data
Parameter
Junction-ambient thermal coefficient
QFN-48
48
Unit
°C/W
13/25
Maximum ratings
STHDLS101
5.1
Recommended operating conditions
5.1.1
Power supply and temperature range
Table 7.
Power supply and temperature range
Symbol
VCC33
Parameter
3.3 V power supply
Comments
Min
Typ
Max
Unit
3.0
3.3
3.±
V
Total current from VCC
3.3 V power supply
ICC
Maximum power supply current
Operating temperature range
100
85
mA
oC
T
-40
5.1.2
Differential inputs (IN_D signals)
Table 8.
Symbol
Differential input characteristics for IN_D signals
Parameter
Comments
Min
Typ Max
Unit
Tbit is determined by the
display mode. Nominal bit
rate ranges from 250 Mbps
to 2.5 Gbps per lane.
Nominal Tbit at
Tbit
Unit interval
3±0
ps
2.5 Gbps = 400 ps. 3±0 ps
= 400 ps – 10%
VRX-DIFFp-p=2*|VRX-D+
VRX-D-|. Applies to IN_D
signals.
-
Differential input peak to peak
voltage
VRX-DIFFp-p
0.175
0.8
1.2
V
Minimum eye width at IN_D input
pair
The level shifter may add a
maximum of 0.02UI jitter
TRX-EYE
Tbit
VCM-AC-pp=|VRX-D+ +
VRX-D-|/2 – VRX-CM-DC.
AC peak common mode input
voltage
VRX-CM-DC=DC(avg) of
|VRX-D+ + VRX-D-|/2
VCM-AC-pp
100
mV
VCM-AC-pp includes all
frequencies above 30 kHz.
Applies to IN_D+ as well as
IN_D- pins
(50 Ω ± 20% tolerance)
ZRX-DC
DC single-ended input impedance
40
0
50
±0
2
Ω
V
Intended to limit power-up
stress on chipset’s PCIE
output buffers
VRX-Bias
RX input termination voltage
Single-ended input resistance for
ZRX-HIGH-Z IN_Dx when inputs are in high-Z
state
Differential inputs must be
in a high impedance state
100
KΩ
14/25
STHDLS101
Maximum ratings
5.2
TMDS outputs (OUT_D signals)
The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The
HDMI 1.3 specification is assumed to be the correct reference in instances where this
document conflicts with the HDMI 1.3 specification.
Table 9.
Symbol
Differential output characteristics for TMDS OUT_D signals
Parameter
Comments
Min
Typ
Max
Unit
AVCC is the DC
Single-ended
high level output
voltage
termination voltage in the
HDMI or DVI sink. AVCC is
nominally 3.3 V
VH
VL
AVCC-10 mV
AVCC
AVCC+10 mV
V
Single-ended low
level output
voltage
The open-drain output
pulls down form AVCC
AVCC-±00 mV AVCC-500 mV AVCC-400 mV
V
V
Single-ended
Swing down from TMDS
termination voltage
(3.3 V±10%)
VSWING output swing
voltage
400 mV
500 mV
±00 mV
10
Measured with TMDS
outputs pulled up to AVCC
max (3.± V) through 50 Ω
resistors
Single-ended
current in high-Z
state
IOFF
µA
Maximum rise/fall time @
2.7 Gbps = 148 ps.
125 ps = 148 – 15%
TR
TF
Rise time
Fall time
125 ps
125 ps
0.4 Tbit
0.4 Tbit
ps
ps
Maximum rise/fall time @
2.7 Gbps = 148 ps.
125 ps = 148 – 15%
This differential skew
budget is in addition to the
skew presented between
D+ and D- paired input
pins.
TSKEW- Intra-pair
differential skew
10
250
7.4
ps
ps
ps
INTRA
This lane-to-lane skew
TSKEW- Inter-pair lane to budget is in addition to the
lane output skew skew between differential
input pairs.
INTER
Jitter budget for TMDS
signals as they pass
Jitter added to
TJIT
through the level shifter.
TMDS signals
7.4 ps = 0.02 Tbit at
2.7 Gbps
15/25
Maximum ratings
STHDLS101
5.3
HPD input and output characteristics
Table 10. HPD_SINK input and HPS_SOURCE output
Symbol
Parameter
Comment
Min
Typ
Max
Unit
Low speed input changes
state on cable plug/unplug
VIH-HPD_SINK
VIL-HPD_SINK
HPD_SINK input high level
HPD_SINK input low level
2
0
5.0
5.3
0.8
V
V
Measured with HPD_SINK
at VIH-HPD max and VIL-
HPD min
HPD_SINK input leakage
current
IIN-HPD_SINK
50
µA
VOH-
HPD_SOURCE output high
level
VCC = 3.3 V±10%
2.5
0
VCC
0.02
V
V
HPD_SOURCE
VOL-
HPD_SOURCE output low level
HPD_SOURCE
Time from HPD_SINK
changing state to
HPD_SOURCE changing
state. Includes
HPD_SOURCE rise/fall
time
HPD_SINK to HPD_SOURCE
propagation delay
THPD
200
ns
ns
CL = 10 pF
Time required to transition
from
VOH-HPD_SOURCE to VOL-
HPD_SOURCE or from VOL-
HPD_SOURCE to VOH-
TRF-HPD
HPD_SOURCE rise/fall time
1
20
HPD_SOURCE
CL=10 pF
1±/25
STHDLS101
Maximum ratings
5.4
DDC input and output chatacteristics
Table 11. SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics
Symb
Parameter
Comment
Min Typ Max Unit
ol
Voltage on the DDC pins on
connector end
VI
Input voltage on SDA_SINK, SCL_SINK pins
0
5.5
V
VCC = 3.3 V
VI = 0.1 VDD to 0.9 VDD to
isolated DDC inputs
Input leakage current on SDA_SINK, SCL_SINK
pins
ILKG
-10
10
µA
VDD = external pull-up
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
VCC = 0.0 V
VI = 0.1 VDD to 0.9 VDD to
DDC sink inputs
VDD = external pull-up
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
Power-down leakage current on SDA_SINK,
SCL_SINK pins
IOFF
-10
10
µA
SDA_SOURCE,
SCL_SOURCE = 0.0 V
V
I(pp) = 1 V, 100 KHz
VCC = 3.3 V, T = 25 ° C
I(pp) = 1 V, 100 KHz
CI/O Input/output capacitance (switch off)
CI/O Input/output capacitance (switch on)
RON Switch resistance
5
pF
pF
Ω
V
10
40
VCC = 3.3 V, T = 25 ° C
IO=3 mA, VO = 0.4 V
VCC = 3.3 V
27
Time from DDC_SINK
changing state to
DDC_SOURCE changing
state while the pass gate is
enabled.
TPD DDC_SINK to DDC_SOURCE propagation delay
8
8
15
15
ns
ns
CL=10 pF
RPU=1.5 K (min), 2.0 K
(max)
CL = 10 pF
Switch time from DDC_EN to the valid state on
TSX
RPU = 1.5 K (min), 2.0 K
(max)
DDC_SOURCE
17/25
Maximum ratings
STHDLS101
5.5
OE_ input characteristics
Table 12. OE_N input characteristics
Symbol
Parameter
Comment
Min
Typ
Max
Unit
VIH-OE_N Input high level
VIL-OE_N Input low level
2
0
VCC33
0.8
V
V
Measured with OE_N at
VIH-OE_N max and
VIL-OE_N mix
IIN-OE_N Input leakage current
200
µA
5.6
HPD input resistor
Table 13. HDP input resistor
Symbol
Parameter
Comment
Min
Typ
Max Unit
Guarantees HPD_SINK is
LOW when no display is
plugged in
RHPD
HPD_SINK input pull-down resistor
130 K 1±0 K 190 K
Ω
5.7
ESD performance
Table 14. ESD performance
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Human body model
(HBM)
ESD
MIL STD 883 method 3015 (all pins)
-±
+±
kV
18/25
STHDLS101
Application information
6
Application information
6.1
6.2
6.3
Power supply sequencing
A proper power supply sequencing is advised for all CMOS devices. It is
recommended to always apply VCC before applying any signals to the input/output
or control pins.
Supply bypassing
Bypass each of the V pins with 0.1µF and 1nF capacitors in parallel as close to the device
CC
as possible, with the smaller valued capacitor as close to the V pin of the device as
possible.
CC
Differential traces
The high-speed inputs and TMDS outputs are the most critical parts for the device. There
are several considerations to minimize discontinuities on these transmission lines between
the connectors and the device.
a) Maintain 100 Ω differential transmission line impedance into and out of the device.
b) Keep an uninterrupted ground plane below the high-speed I/Os.
c) Keep the ground-path vias to the device as close as possible to allow the shortest
return current path.
d) Layout of the TMDS differential outputs should be with the shortest stubs from the
connectors.
Output trace characteristics affect the performance of the STHDLS101. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 ° C turns and minimize the number of vias to further
prevent impedance discontinuities.
19/25
Package mechanical data
STHDLS101
7
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
20/25
STHDLS101
Package mechanical data
Figure 6.
QFN-48 (7 x 7 mm) package outline
21/25
Package mechanical data
STHDLS101
Table 15. QFN-48 (7 x 7 mm) package mechanical data
Millimeters
Typ
Inches
Typ
Symbol
Min
Max
Min
Max
A
A1
A2
A3
b
0.80
0.90
0.02
0.±5
0.25
0.23
7.00
4.70
7.00
4.70
0.50
0.40
1.00
0.05
1.00
0.80
0.85
0.01
0.±5
0.20
0.23
7.00
1.00
0.05
0.18
±.85
2.25
±.85
2.25
0.45
0.30
0.30
7.15
5.25
7.15
5.25
0.55
0.50
0.08
0.18
±.90
0.30
7.10
D
D2
E
See exposed pad variations
±.90
7.00
7.10
E2
e
See exposed pad variations
0.45
0.30
0.50
0.40
0.55
L
0.50
0.08
ddd
Figure 7.
QFN-48 tape information
22/25
STHDLS101
Package mechanical data
Figure 8.
Reel information
0084±94_J
Table 16. Reel mechanical data (dimensions in mm)
A
C
N
T
330.2
13 ±0.25
100
1±.4
23/25
Revision history
STHDLS101
8
Revision history
Table 17. Document revision history
Date
Revision
Changes
15-Apr-2008
23-Apr-2008
10-Jun-2008
1
2
3
Initial release.
Modified: Figure 5.
Document status promoted from preliminary data to datasheet.
Updated: Features section, Table 2: Pin description on page 7 and
Chapter 4 and Chapter 5: Maximum ratings on page 13.
Added: Figure 3: Cable adapter on page 4, Figure 4: DP to
HDMI/DVI cable adapter on page 5, Figure 8: Reel information on
page 23 and Table 16: Reel mechanical data (dimensions in mm) on
page 23.
01-Dec-2008
4
24/25
STHDLS101
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