STHDLS101TQTR [STMICROELECTRONICS]
SPECIALTY CONSUMER CIRCUIT, QCC48, 7 X 7 MM, ROHS COMPLIANT, QFN-48;
| 型号： | STHDLS101TQTR |
| 厂家： | 
ST |
| 描述： | SPECIALTY CONSUMER CIRCUIT, QCC48, 7 X 7 MM, ROHS COMPLIANT, QFN-48 商用集成电路 |
| 文件： | 总26页 (文件大小：373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STHDLS101T
AC coupled HDMI level shifter
with configurable HPD output
Features
■ Converts low-swing alternating current (AC)
coupled differential input to high-definition
multimedia interface (HDMI) rev 1.3 compliant
■ HDMI level shifting operation up to 2.7 Gbps
per lane
■ Integrated 50-Ω termination resistors for AC-
coupled differential inputs
■ Input/output transition minimized differential
signaling (TMDS) enable/disable
QFN-48
(7 x 7 mm)
■ Output slew rate control on TMDS outputs to
minimize electromagnetic interference (EMI)
■ Fail safe outputs for backdrive protection
■ No re-timing or configuration required
■ Inter-pair output skew < 250 ps
Description
■ Intra-pair output skew < 10 ps
The STHDLS101T is a high-speed high-definition
multimedia interface (HDMI) level shifter that
converts low-swing AC coupled differential input
to HDMI 1.3 compliant open-drain current
■ Single power supply of 3.3 V
■ ESD protection: 6 KV HBM on all I/O pins
■ Integrated display data chnel (DDC) level
shifters. Pass-gate volte limiters allow 3.3 V
termination on grphics and memory controller
hub (GMCH) pins and 5 V DDC termination on
HDMI connector pins
steering RX-terminated differential output.
Through the existing PCI-E pins in the graphics
and memory controller hub (GMCH) of PCs or
notebook motherboards, the pixel clock provides
the required bandwidth (1.65 Gbps, 2.25 Gbps)
for the video supporting 720p, 1080i, 1080p with a
total of 36-bit resolution. The HDMI is multiplexed
onto the PCIe pins in the motherboard where the
AC coupled HDMI at 1.2 V is output by GMCH.
The AC coupled HDMI is then level shifter by this
device to 3.3 V DC coupled HDMI output.
■ Levl shifter and configurable output for HPD
signal from HDMI/DVI connector
■ Integrated pull-down resistor on HPD_SINK
and OE_N inputs
Applications
The STHDLS101T supports up to 2.7 Gbps,
which is enough for 12-bits of color depth per
channel, as indicated in HDMI rev 1.3. The device
operates from a single 3.3 V supply and is
available in a 48-pin QFN package.
■ Notebooks
■ PC motherboards and graphic cards
■ Dongles/cable adapters
Table 1.
Device summary
Order code
Package
Packaging
STHDLS101TQTR
QFN-48
Tape and reel
December 2008
Rev 3
1/26
www.st.com
26
Contents
STHDLS101T
Contents
1
2
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1
5.1.2
Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
5.3
5.4
5.5
5.6
5.7
TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DDC input and output chataeristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Appliation information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
6.2
6.3
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/26
STHDLS101T
Contents
3/26
Block diagram
STHDLS101T
1
Block diagram
Figure 1.
STHDLS101T block diagram
0V
VCC33
OUT_D4+
OUT_D4-
50 ±±1%
Ω
IN_D4+
IN_D4-
OE_N
RX
RX
RX
RX
10mA current
driver
1V
OUT_D3+
OUT_D3-
Ω
50 ±±1%
IN_D3+
IN_D3-
10mA current
driver
1V
OUT_D2+
OUT_D2-
50 ±±1%
Ω
IN_D2+
IN_D2-
±1mA current
driver
1V
OUT_D1+
OUT_D1-
50Ω±±1%
IN_D1+
IN_D1-
REXT
10mA current
driver
HPD level
HPD
shifter
HPD_SOURCE
HPD_SINK
±61
K
DDC_EN
SCL_SOURCE
SDA_SOURCE
SCL_SINK
SDA_SINK
4/26
STHDLS101T
System interface
2
System interface
Figure 2.
System inferface
PCI-Express
SDVO
HDMI
Graphics chipset
Level shifter
HDMI output
connector
(GMCH) on the
motherboard
STHDLS101T
CS00375
Figure 3.
Cable adapter
($-)ꢄ$6)
$ONGLE OR
ADAPTER
CABLE
ꢃꢀꢃ4
34($,3
$0
5/26
System interface
Figure 4.
STHDLS101T
DP to HDMI/DVI cable adapter
HPD_SINK
DC TMDS
HPD
HPD_SOURCE
HDMI/DVI
Transmitter
STHDLS101T
HDMI/DVI Cable
Adaptor
AC_TMDS
DDC
AC_TMDS
DDC
DDC
PC chipset
!-ꢀꢀꢁꢂꢃ6ꢃ
6/26
STHDLS101T
Pin configuration
3
Pin configuration
Figure 5.
STHDLS101T pin configuration
GND
24
23
22
GND
37
OUT_D1-
OUT_D1+
VCC33
IN_D1-
38
IN_D1+
39
21
20
19
VCC33
40
OUT_D2-
OUT_D2+
IN_D2-
41
IN_D2+
QFN-48
42
GND
18
GND
43
17
OUT_D3-
OUT_D3+
VCC33
IN_D3-
44
45
16
15
14
13
IN_D3+
VCC33
IN_D4-
IN_D4+
46
47
48
OUT_D4-
OUT_D4+
CS000118
7/26
Pin configuration
STHDLS101T
3.1
Pin description
Table 2.
Pin description
Name
Pin
number
Type
Function
1
2
GND
Power
Power
Ground
VCC33
3.3V 10% DC supply
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
control or test
pins
For normal operation, these pins are tied to GND or
VCC33.
3
FUNCTION1
For consistent interoperability, GND is the preferred
default connection for these signals
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
control or test
pins
For normal operation, these s are tied to GND or
VCC33.
4
5
FUNCTION2
GND
For consistent interoperability, GND is the preferred
default connection for these signals
Power
Ground
Connection to external resistor. Resistor value
scified by device manufacturer.
Acceptable connections to this pin are:
6
REXT
Analog
- Resistor to GND
- Resistor to 3.3V;
- NC (direct connections to VCC or GND are through a
0-Ù resistor for layout compatibility
Buffer from the 0 V to 5 V input signal. The output
buffer stage is configurable based on the FUNCTION3
pin settings as desribed in the table below:
7
HP_SOURCE
Output
FUNCTION3
HPD_SINK
HPD_SOURCE
Open-drain,
connected an
external pull up to
the desired
0
Low
supply
(normally 1 V)
0
1
1
High (5 V)
Low (0 V)
High (5 V)
Low (0 V)
Low (0 V)
High (3 V)
3.3 V DDC data I/O. Pulled-up by external termination
to 3.3 V. Connected to SDA_SINK through voltage-
limiting integrated NMOS pass-gate
8
9
SDA_SOURCE
SCL_SOURCE
I/O
3.3 V DDC clock I/O. Pulled-up by external termination
to 3.3 V. Connected to SCL_SINK through voltage-
limiting integrated NMOS pass-gate
Input
8/26
STHDLS101T
Table 2.
Pin configuration
Pin description (continued)
Pin
number
Name
Type
Function
Analog connection determined by vendor.
Acceptable connections to this pin are:
- Resistor or capacitor to GND
- Resistor or capacitor to 3.3 V
- Short to 3.3 V or to GND
- NC
10
ANALOG2
Analog
11
12
VCC33
GND
Power
Power
3.3 V 10% DC supply
Ground
HDMI 1.3 compliant TMDS output.
OUT_D4+ makes a differential output signal with
OUT_D4-.
13
OUT_D4+
Output
HDMI 1.3 compliant TMDS output.
OUT_D4- makes a differential ouut signal with
OUT_D4+.
14
15
16
OUT_D4-
VCC33
Output
Power
Output
3.3 V 10% DC supply
HDMI 1.3 compliant TMDS output.
OUT_D3+ makes a differential output signal with
OUT_D
OUT_D3+
HMI 1.3 compliant TMDS output.
OUT_D3- makes a differential output signal with
OUT_D3+.
17
18
19
OUT_D3-
GND
Output
Power
Output
Ground
HDMI 1.3 compliant TMDS output.
OUT_D2+ makes a differential output signal with
OUT_D2-.
OUT_D2+
HDMI 1.3 compliant TMDS output.
OUT_D2- makes a differential output signal with
OUT_D2+.
20
OUT_D2-
Output
21
22
VCC33
Power
Output
3.3 V 10% DC supply
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-.
OUT_D1+
HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+.
23
24
OUT_D1-
GND
Output
Power
Ground
Enable for level shifter path. 3.3 V tolerant low-voltage
single-ended input. Internal pull-down enables chip
when unconnected.
IN_D
termination
25
26
OE_N
Input
OE_N
OUT_D Outputs
1
0
High-Z
High-Z
Active
50 Ω
VCC33
Power
3.3 V 10% DC supply
9/26
Pin configuration
Table 2.
STHDLS101T
Pin description (continued)
Pin
number
Name
Type
Function
27
GND
Power
Ground
5 V DDC Clock I/O. Pulled-up by external termination
to 5 V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS pass-gate
28
SCL_SINK
SDA_SINK
Output
I/O
5V DDC Data I/O. Pulled-up by external termination to
5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS pass-gate
29
Low-frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage high
indicates “plugged” state; voltage low indicates
“unplugged” state. HPD_SINK is pulled down by an
integrated 160KΩ pull-down resistor.
30
31
HPD_SINK
GND
Input
Power
Ground
Enables bias voltage te DDC pass-gate level shifter
gates. (May be implemented as a bias voltage
connection to the DDC pass-gate themselves).
32
DDC_EN
Input
DDC_EN
Pass-gate
0 V
3.3 V
Disabled
Enabled
33
34
VCC33
Power
Input
3.3V 10% DC supply
Used for polarity control of the HPD_SOURCE output.
When L, the HPD_SOURCE is an open-drain output
sand when H, the HPD_SOURCE is a buffered output
FUNCTION3
(O V to VCC
)
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
control or test
pins
For normal operation, these pins are tied to GND or
VCC33.
35
FUNCTION4
For consistent interoperability, GND is the preferred
default connection for these signals
36
37
GND
GND
Power
Power
Ground
Ground
Low-swing differential input from GMCH PCIE outputs.
IN_D1- makes a differential pair with IN_D1+.
38
IN_D1-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1-.
39
40
41
IN_D1+
VCC33
IN_D2-
Input
Power
Input
3.3 V 10% DC supply
Low-swing differential input from GMCH PCIE outputs.
IN_D2- makes a differential pair with IN_D2+.
Low-swing differential input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2-.
42
IN_D2+
Input
10/26
STHDLS101T
Table 2.
Pin configuration
Pin description (continued)
Pin
number
Name
Type
Function
43
44
GND
Power
Input
Ground
Low-swing differential input from GMCH PCIE outputs.
IN_D3- makes a differential pair with IN_D3+.
IN_D3-
Low-swing differential input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3-.
45
46
47
IN_D3+
VCC33
IN_D4-
Input
Power
Input
3.3 V 10% DC supply
Low-swing differential input from GMCH PCIE outputs.
IN_D4- makes a differential pair with IN_D4+.
Low-swing differential input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4-.
48
IN_D4+
Input
11/26
Functional description
STHDLS101T
4
Functional description
The section describes the basic functionality of the STHDLS101T device.
Power supply
The STHDLS101T is powered by a single DC power supply of 3.3 V 10%.
Clocking
This device does not retime any data. The device contains no state machines. No inputs or
outputs of the device are latched or clocked.
Reset
This device acts as a level shifter, reset is not required.
OE_N function
When OE_N is asserted (low level), the IN_D and OUT_D sigls are fully functional. Input
termina-tion resistors are enabled and any internal bias circuits are turned on.
OE_N pin has an internal pull-down that enables the chip if left unconnected.
When OE_N is de-asserted (high level), the OUD outputs are in high impedance state.
The IN_D input buffers are disabled and the IN_D termination resistors are disabled.
Internal bias circuits for the differential utand outputs are turned off. Power consumption
of the chip is minimized.
The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and
SDA pass-gates are not affected by OE_N.
Table 3.
OE_N description
O_N
Device state
Comments
Differential input buffers and
output buffers enabled. Input
impedance = 50Ù
Asserted (low level)
or unconnected
Normal functioning state for IN_D
to OUT_D level shifting function.
Low-power state.
Intended for lowest power
condition when:
• No display is plugged in or
• The level shifted data path is
disabled
Differential input buffers and
terminations are disabled.
Differential input buffers are in
high-impedance state.
HPD_SINK input and
OUT_D level shifting outputs are HPD_SOURCE output are not
De-asserted (high level)
disabled. OUT_D level shifting
outputs are in a high-impedance
state.
affected by OE_N.
SCL_SOURCE, SCL_SINK,
SDA_SOURCE and SDA_SINK
Internal bias currents are turned signals and functions are not
off. affected by OE_N.
12/26
STHDLS101T
Functional description
Table 4.
OE_N function
OE_N
OUT_Dx
(TMDS outputs)
IN_Dx
Notes
Device disabled.
Low power state.
De-asserted
(high level)
High-Z
High-Z
Internal bias currents are
disabled.
Asserted or
unconnected
(low level)
Level shifting mode
enabled.
50 Ω termination
Enabled
13/26
Maximum ratings
STHDLS101T
5
Maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 5.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
VI
Supply voltage to ground potential
DC input voltage (TMDS and PCIe ports)
Control pins
-0.5 to +4.0
-0.5 to +4.0
-0.5 t+4.0
5 to +6
120
V
V
V
SDA_SINK, SCL_SINK, HPD_SINK pins
DC output current
V
IO
mA
W
°C
°C
PD
Power dissipation
1
TSTG Storage temperature
-65 to +150
300
TL
Lead temperature (10 sec)
Electrostatic discharge
VESD
Han body model
6
kV
voltage on IOs(1)
1. In accordance with the MIL standard 883 method 3015
Table 6.
Symbol
JA
Thermal data
Parameter
Junction-ambient thermal coefficient
QFN-48
48
Unit
°C/W
14/26
STHDLS101T
Maximum ratings
5.1
Recommended operating conditions
5.1.1
Power supply and temperature range
Table 7.
Power supply and temperature range
Symbol
VCC33
Parameter
3.3 V power supply
Comments
Min
Typ
Max
Unit
3.0
3.3
3.6
V
Total current from VCC
3.3 V power supply
ICC
Maximum power supply current
Operating temperature range
100
85
mA
oC
T
-40
5.1.2
Differential inputs (IN_D signals)
Table 8.
Symbol
Differential input characteristics for IN_D signals
Parameter
Comments
M
Typ Max Unit
Tbit is determined by the
display mode. Nominal bit
rate ranges from 250 Mbps
to 2.5 Gbps pr lane.
Nominal Tbit at
Tbit
Unit interval
360
ps
2.5 Gb= 400 ps. 360 ps =
4s – 10%
VRX-DIFFp-p=2*|VRX-D+ - VRX-
D-|. Applies to IN_D signals.
VRX-DIFFp-p Differential input peak to peak voltage
0.175
0.8
1.2
V
The level shifter may add a
maximum of 0.02UI jitter
TRX-EYE
Minimum eye width at IN_D input pair
Tbit
VCM-AC-pp=|VRX-D+ +
VRX-D-|/2 – VRX-CM-DC.
VRX-CM-DC=DC(avg) of
|VRX-D+ + VRX-D-|/2
VCM-AC-pp AC peak common mode input voltage
100
mV
VCM-AC-pp includes all
frequencies above 30 kHz.
Applies to IN_D+ as well as
IN_D- pins (50 Ω 20%
tolerance)
ZRX-DC
DC single-ended input impedance
40
50
60
2
Ω
Intended to limit power-up
stress on chipset’s PCIE
output buffers
VRX-Bias
RX input termination voltage
0
V
Single-ended input resistance for
IN_Dx when inputs are in high-Z state a high impedance state
Differential inputs must be in
ZRX-HIGH-Z
100
KΩ
15/26
Maximum ratings
STHDLS101T
5.2
TMDS outputs (OUT_D signals)
The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The
HDMI 1.3 specification is assumed to be the correct reference in instances where this
document conflicts with the HDMI 1.3 specification.
Table 9.
Symbol
Differential output characteristics for TMDS OUT_D signals
Parameter
Comments
Min
Typ
Max
Unit
AVCC is the DC termination
voltage in the HDMI or DVI
sink. AVCC is nominally 3.3 V
Single-ended high
level output voltage
AVCC+10 m
V
VH
VL
AVCC-10 mV
AVCC
V
Single-ended low level The open-drain output pulls
AVCC
-
AVCC
-
AVCC-
400 mV
V
V
output voltage
down form AVCC
600 mV
500 mV
Swing down from TMDS
termination voltage
(3.3 V 10%)
Single-ended output
swing voltage
VSWING
400 mV
500 mV
600 mV
Measured with TMDS outputs
pulled up to AVCC max (3.6 V)
through 50 Ω resistors
Single-ended current
in high-Z state
IOFF
10
µA
ps
ps
Maximum rise/fall time at
2.7 Gbps = 148ps. 125ps =
148 – 15%
TR
Rise time
Fall time
125 ps
125 ps
0.4 Tbit
0.4 Tbit
Maximum rise/fall tim
2.7 Gbps = 148 ps.
TF
125ps = 148 – 15%
This differential skew budget
is in addition to the skew
presented between D+ and D-
paired input pins.
TSKEW- Intra-pair differential
skew
10
250
7.4
ps
ps
ps
INTRA
This lane to lane skew budget
TSKEW- Inter-pair lae to lane is in addition to the skew
output skew
between differential input
pairs.
INTER
Jitter budget for TMDS
Jitter added to TMDS signals as they pass through
TJIT
signals
the level shifter.
7.4 ps = 0.02 Tbit at 2.7 Gbps
16/26
STHDLS101T
Maximum ratings
5.3
HPD input and output characteristics
Table 10. HPD_SINK input and HPS_SOURCE output
Symbol
VIH-HPD_SINK HPD_SINK input high level
VIL-HPD_SINK HPD_SINK input low level
IIN-HPD_SINK
Parameter
Comment
Min
Typ
Max
Unit
Low speed input changes
state on cable plug/unplug
2
0
5.0
5.3
0.8
V
V
Measured with HPD_SINK
HPD_SINK input leakage current at VIH-HPD max and VIL-
HPD min
50
µA
VCC = 3.3 V 10%
VOH-
HPD_SOURCE output high level
when FUNCTION3 = L
Based on external pull-up
resistor;
output is open drain.
HPD_SOURCE
(INV)
VOL-
HPD_SOURCE output low level
when FUNCTION3 = H
VCC = 3.3 V 10%
2.5
0
VCC
0.2
V
V
V
HPD_SOURCE
VOH-
VCC = 3.3 V 10%
IOL = 1 mA
HPD_SOURCE output high level
when FUNCTION3 = L
HPD_SOURCE
(INV)
VOL-
HPD_SOURCE output low level
when FUNCTION3 = H
VCC = 3.3 V 10%
0
0.2
HPD_SOURCE
Tifrom HPD_SINK
changing state to
HPD_SOURCE changing
state. Includes
HPD_SOURCE rise/fall
time
HPD_SINK to HPD_SOURCE
propagation delay
THPD
200
ns
ns
CL=10 pF
Time required to transition
from VOH-HPD_SOURCE to
VOL-HPD_SOURCE or from
VOL-HPD_SOURCE to VOH-
TRF-HPD
HPD_SOURCE rise/fall time
1
20
HPD_SOURCE
CL=10 pF
17/26
Maximum ratings
STHDLS101T
5.4
DDC input and output chatacteristics
Table 11. SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics
Symb
Parameter
Comment
Min Typ Max Unit
ol
Voltage on the DDC pins on
connector end
VI
Input voltage on SDA_SINK, SCL_SINK pins
0
5.5
V
VCC = 3.3 V
VI =0.1VDD to 0.9 VDD to
isolated DDC inputs
Input leakage current on SDA_SINK, SCL_SINK
pins
ILKG
-10
10
µA
VDD = external pull-up
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
VCC = 0.0 V
VI = 0.1 VDD to 0.9 VDD to
DDC sink inputs
VDD = external pull-up
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
Power-down leakage current on SDA_SINK,
SCL_SINK pins
IOFF
-10
10
µA
SDA_SORCE,
SC_SOURCE = 0.0 V
VI(pp)=1 V, 100 KHz
VCC=3.3 V, T=25C
Input/output capacitance
(switch off)
CI/O
CI/O
5
pF
pF
Ω
VI(pp)=1 V, 100KHz
Input/output capacitance
(switch on)
10
40
VCC = 3.3 V, T= 25 °C
IO=3 mA, VO = 0.4 V
VCC = 3.3 V
RON Switch resistance
27
Time from DDC_SINK
changing state to
DDC_SOURCE changing
state while the pass gate is
enabled.
TPD DDC_SINK to DDC_SOURCE propagation delay
8
8
15
15
ns
ns
CL=10 pF
RPU=1.5 K (min), 2.0 K
(max)
CL = 10 pF
Switch time from DDC_EN to the valid state on
TSX
RPU = 1.5 K (min), 2.0 K
(max)
DDC_SOURCE
18/26
STHDLS101T
Maximum ratings
5.5
OE_ input characteristics
Table 12. OE_N input characteristics
Symbol
Parameter
Comment
Min
Typ
Max
Unit
VIH-OE_N Input high level
VIL-OE_N Input low level
2
0
VCC33
0.8
V
V
Measured with OE_N at
VIH-OE_N max and VIL-
OE_N mix
IIN-OE_N Input leakage current
200
µA
5.6
HPD input resistor
Table 13. HDP input resistor
Symbol
Parameter
Comment
Min
Typ
Max Unit
Guarantees HPD_SINK is
LOW when no dislay is
plugged in
RHPD
HPD_SINK input pull-down resistor
130 K 160 K 190 K
Ω
5.7
ESD performance
Table 14. ESD performance
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
ESD
MIL STD 883 method 015 (all pins) Human Body Model (HBM)
-6
+6
kV
19/26
Application information
STHDLS101T
6
Application information
6.1
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is
recommended to always apply VCC before applying any signals to the input/output
or control pins.
6.2
6.3
Supply bypassing
Bypass each of the V pins with 0.1 µF and 1nF capacitors in parallel as close to the
CC
device as possible, with the smaller-valued capacitor as close to the V pin of the device
as possible.
CC
Differential traces
The high-speed inputs and TMDS outputs are the most critical parts for the device. There
are several considerations to minimize discontinuities on hese transmission lines between
the connectors and the device.
(a) Maintain 100 Ω differential transmission line iedance into and out of the device.
(b) Keep an uninterrupted ground plane bew the high-speed I/Os.
(c) Keep the ground-path vias to the device as close as possible to allow the shortest return
current path.
(d) Layout of the TMDS differential outputs should be with the shortest stubs from the
connectors.
Output trace chaacteristics affect the performance of the STHDLS101T. Use controlled
impedance tres to match trace impedance to both the transmission medium impedance
and terination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.
20/26
STHDLS101T
Package mechanical data
7
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
21/26
Package mechanical data
Figure 6. QFN-48 (7 x 7 mm) package outline
STHDLS101T
22/26
STHDLS101T
Package mechanical data
Table 15. QFN-48 (7 x 7 mm) package mechanical data
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
A3
b
0.80
0.90
0.02
0.65
0.25
0.23
7.00
4.70
7.00
4.70
0.50
0.40
1.00
0.05
1.00
0.80
0.85
0.01
0.65
0.20
0.23
7.00
1.00
0.05
0.18
6.85
2.25
6.85
2.25
0.45
0.30
0.30
7.15
5.25
7.15
5.25
0.55
0.50
0.08
0.18
6.90
0.30
7.10
D
D2
E
SEE EXPOSED PAD VARIATIONS
6.90 7.00 7.10
SEE EXPOSED PAD VARIATIONS
E2
e
0.45
0.30
0
0.40
0.55
0.50
0.08
L
ddd
Figure 7.
QFN-48 tape and reel information
23/26
Package mechanical data
STHDLS101T
Figure 8.
Reel information
0084694_J
Table 16. Remechanical data (dimensions in mm)
A
C
N
T
330.2
13 0.25
100
16.4
24/26
STHDLS101T
Revision history
8
Revision history
Table 17. Document revision history
Date
Revision
Changes
30-Jun-2008
1
Initial release.
Document status promoted from preliminary data to datasheet.
24-Sep-2008
01-Dec-2008
2
3
Modified: features section, Table 2: Pin description on page 8 and
Section 4: Functional description.
Updated: Features section andChapter 5: Maximum ratings
Added: Figure 3: Cable adapter on page 5 , Figure 4: DP to
HDMI/DVI cable adapter on page 6, Figure 8: Reel information on
page 24 and Table 16: Reel mechanical data (dimensions in mm) on
page 24
25/26
STHDLS101T
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26/26
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