STHDMI002ABTR [STMICROELECTRONICS]
Wide bandwidth, 2 to 1 HDMI switch with single enable; 宽的带宽，以2比1的HDMI开关单启用
| 型号： | STHDMI002ABTR |
| 厂家： | 
ST |
| 描述： | Wide bandwidth, 2 to 1 HDMI switch with single enable |
| 文件： | 总26页 (文件大小：575K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STHDMI002A
Wide bandwidth, 2 to 1 HDMI switch with single enable
Features
■ Compatible with HDMI v1.2, DVI v1.0 digital
interfaces
■ 165MHz speed operation supports all video
formats up to 1080p and SXGA (1280 x 1024
at 75Hz)
TQFP48
■ Data rate per channel for UXGA: 1.65Gbps
■ Low R : 5.5 Ω(typ)
ON
Description
■ V operating range: 3.135V to 3.465V
CC
The STHDMI002A is a differential Single Pole
Double Throw (SPDT) 2 to 1, low Ron,
bi-directional HDMI switch designed for advanced
TV applications supporting HDMI/DVI which
demand high definition superior image quality.
The differential signal from the 2 ports of HDMI is
multiplexed through the switch to form a single
output HDMI channel going to the HDMI receiver
while the unselected output goes to the high-Z
state.
■ Low current consumption: 20µA
■ ESD human body model HBM Voltage:
–
2KV for all I/Os
■ Channel ON capacitance: 6pF (typ)
■ Switching speed: 9ns
■ Near-zero propagation delay: 250ps
■ Low crosstalk: -32dB at 825MHz
■ Bit-to-bit skew: 200ps
It is designed for very low cross-talk, low bit-to-bit
skew, high channel-to-channel noise isolation and
low I/O capacitance. The switch offers very little or
practically no attenuation of the high-speed
signals at the outputs, thus preserving the signal
integrity to pass stringent requirements.
■ Very low ground bounce in flow through mode
■ Data and control inputs provide an undershoot
clamp diode
■ Wide bandwidth minimizes skew and jitter
■ Hot insertion capable
The STHDMI002A also includes the DDC as well
as the HPD line switching. The pin layout is
optimized for easy PCB routing to the HDMI
connector and HDMI receivers.
■ Isolated Digital Display Control (DDC) bus for
unused ports
■ 5V tolerance to all DDC and HPD_SINK inputs
■ Supports bi-directional operation
The maximum DVI/HDMI data rate of 1.65Gbps
provides the resolution required by the advanced
HDTV and PC graphics.
■ Available in the TQFP48 package
■ –40°C to 85°C operating temperature range
Applications
Advantages
■ Advanced TVs
■ Front projectors
■ LCD TVs
STHDMI002A provides the ability to switch a
single source output to various display devices or
switch video display devices between multiple
sources. It reduces the overall BOM costs by
eliminating the need for more costly multi input-
output controllers.
■ PDPs
■ LCD monitors
■ Notebook PCs
■ STB and DVD players
October 2006
Rev 1
1/26
www.st.com
26
Contents
STHDMI002A
Contents
1
2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
4
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1
6.2
6.3
6.4
6.5
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/26
STHDMI002A
Contents
9.2
9.3
Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10
11
12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
Functional diagram
STHDMI002A
1
Functional diagram
Figure 1. Functional diagram
4/26
STHDMI002A
Functional description
2
Functional description
The STHDMI002A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standards like TMDS. The device multiplexes
differential outputs from a video source to one of the two corresponding outputs to a common
display. The low on-resistance and low I/O capacitance of STHDMI002A result in a very small
propagation delay. The device integrates SPDT-type switches for 3 differential data TMDS
channels and 1 differential clock channel. Additionally it integrates the switches for DDC and
HPD lines switching.
The I²C interface of the selected input port is linked to the I²C interface of the output port, and
the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused
ports, the I²C interfaces are isolated, and the HPD pins are also isolated.
2.1
2.2
HPD pins
The input of the Y_HPD is 5V tolerant, allowing direct connection to 5V signals. The switch is
able to pass both 0V and 5V signal levels. The HPD switch resistance depends on the input
voltage level. At low (near to 0V) input voltage levels, the resistance is 20Ωtypically and at high
(near to 5V) input voltage levels, the resistance is 150Ω typically.
DDC channels
The DDC channels are designed with a bi-directional NMOS gate, providing 5V signal
tolerance. The 5V tolerance allows direct connection to a standard I²C bus, thus eliminating the
need for a level shifter. When the input is a 5V, the NMOS switch is turned off and the pull up
resistor on either side of the switch determines the high voltage potential.
5/26
Application diagram
STHDMI002A
3
Application diagram
Figure 2. Application diagram
6/26
STHDMI002A
Pin configuration
4
Pin configuration
Figure 3. Pin connections
TQFP48 (pitch = 0.5mm)
7/26
Pin configuration
STHDMI002A
Table 1.
Pin description
Pin Name
Pin number
Type
Function
Supply voltage (3.3V 5%)
1
VCC
ACLK-
ACLK+
GND
A0-
Power
Input
Input
Power
Input
Input
Power
Input
Input
Power
Input
Input
Power
Output
Power
I/O
2
TMDS Clock- for port A
TMDS Clock+ for port A
Ground
3
4
5
TMDS Data 0- for port A
TMDS Data 0+ for port A
Ground
6
A0+
7
GND
A1-
8
TMDS Data 1- for port A
TMDS Data 1+ for port A
Ground
9
A1+
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND
A2-
TMDS Data 2- for port A
TMDS Data 2+ for port A
Supply voltage (3.3V 5%)
Hot Plug Detect (HPD) output for port B
Ground
A2+
VCC
B_HPD
GND
B_DDC_SDA
B_DDC_SCL
VCC
DDC SDA input for port B
DDC SCL input for port B
Supply voltage (3.3V 5%)
TMDS Clock- for port B
TMDS Clock+ for port B
Ground
I/O
Power
Input
Input
Power
Input
Input
Power
Input
Input
Power
Input
Input
Input
Output
Output
Power
Output
BCLK-
BCLK+
GND
B0-
TMDS Data 0- for port B
TMDS Data 0+ for port B
Ground
B0+
GND
B1-
TMDS Data 1- for port B
TMDS Data 1+ for port B
Ground
B1+
GND
B2-
TMDS Data 2- for port B
TMDS Data 2+ for port B
B2+
SEL
Select control input to select port A or port B
TMDS Data2+ output
TMDS Data2- output
Y2+
Y2-
GND
Y1+
Ground
TMDS Data1+ output
8/26
STHDMI002A
Pin configuration
Table 1.
Pin description
Pin name
Pin number
Type
Function
35
36
37
38
39
40
41
42
43
Y1-
GND
Output
Power
Output
Output
Power
Output
Output
I/O
TMDS Data1- output
Ground
Y0+
TMDS Data0+ output
TMDS Data0- output
Ground
Y0-
GND
YCLK+
YCLK-
TMDS Clock+ output
TMDS Clock- output
DDC SCL output
DDC SDA output
Y_DDC_SCL
Y_DDC_SDA
I/O
Sink side hot plug detector input
High : 5V power signal asserted from source to sink
and EDID is ready
44
Y_HPD
Input
Low : No 5V power signal is asserted from source to
sink or EDID is not ready
45
46
47
48
A_HPD
VCC
Output
Power
I/O
Hot Plug Detect (HPD) output for port A
Supply voltage (3.3V 5%)
DDC SDA input for port A
A_DDC_SDA
A_DDC_SCL
I/O
DDC SCL input for port A
4.1
Function table
Table 2.
SEL
Function table
Signal status
DDC Status
HPD Status
Y= TMDS Data, Clock for port A
Port B is in ‘Z’ state
Y = DDC for port A
DDC for port B is ‘Z’
Y= HPD for port A
L
HPD for port B is ‘Z’
Y=TMDS Data, Clock for port B
Port A is in ‘Z’ state
Y = DDC for port B
DDC for port A is ‘Z’
Y= HPD for port B
H
HPD for port A is ‘Z’
9/26
Maximum rating
STHDMI002A
5
Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may cause
permanent damage to the device. these are stress ratings only and operation of the device at
these or any other conditions above those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics sure program and
other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
Supply voltage to Ground
DC Input Voltage (TMDS A,B ports)
SEL
-0.5 to +4.0
1.7 to +4.0
-0.5 to +4.0
V
V
V
VI
A_DDC_SDA, A_DDC_SCL, B_DDC_SDA, B_DDC_SCL,
Y_DDC_SDA, Y_DDC_SCL, Y_HPD, A_HPD, B_HPD
-0.5 to +6.0
V
VIC
IO
DC control input voltage
DC output current
-0.5 to +4.0
120
V
mA
°C
TSTG
TL
Storage temperature
Lead temperature (10 sec)
Human body model
-65 to +150
300
°C
kV
kV
-2 to +2
-2 to +2
Electrostatic discharge voltage on IOs(1)1
Contact discharge
VESD
1. In accordance with the MIL STD 883 method 3015
Table 4.
Symbol
Thermal data
Description
Thermal Resistance Junction-ambient
Value
Unit
RthJA
TBA
°C/W
10/26
STHDMI002A
DC electrical characteristics
6
DC electrical characteristics
T = -40 to +85 °C, V = 3.3V 5%
A
CC
DC electrical characteristics
Parameter
Table 5.
Symbol
Test conditions
Min Typ Max Unit
VIH
VIL
VIK
IIH
HIGH level input voltage (SEL pin)
LOW level input voltage (SEL pin)
Clamp Diode voltage (All IOs)
High level guaranteed
Low level guaranteed
VCC = 3.465V, IIN = -18mA
VCC = 3.465V, VIN = VCC
VCC = 3.465V, VIN = GND
VCC = 0V;
2.0
V
V
-0.5
0.8
-0.8 -1.2
V
Input high current (SEL pin, A, B data ports)
Input low current (SEL pin, A, B data ports)
5
5
µA
µA
IIL
Outputs (Y-port) = 0V;
Inputs (A-port) = 3.465V;
Inputs (B-port) = 3.465V
IOFF
Power down leakage current
Switch ON resistance (1)
5
µA
VCC = 3.135 V,
VIN = 1.5 to VCC
IIN = -40mA
RON
RFLAT
∆RON
5.5
0.8
1.0
7.5
Ω
Ω
Ω
VCC = 3.135 V,
VIN = 1.5 to VCC
IIN = -40mA
ON resistance flatness (1) (2)
VCC = 3.135 V,
VIN = 1.5 to VCC
IIN = -40mA
ON resistance match between channels
1.3
(1) (3)
∆RON = RONMAX - RONMIN
DDC I/O Pins
VCC = 3.465V
VI (max) = 5.3V on
isolated DDC ports
Y= 0.0V
II(leak)
Input leakage current
0.1
+2
5
µA
µA
VCC = 0V;
Outputs (Y-port) = 0V;
Inputs (A-port) = 5.3V;
Inputs (B-port) = 5.3V
IOFF
Power down leakage current
VI=0V, VCC=3.3V, T= 25°C
F = 1 MHz
Switch off capacitance
Switch on capacitance
5
9
pF
pF
CI/O
11/26
DC electrical characteristics
STHDMI002A
Table 5.
Symbol
DC electrical characteristics
Parameter
Test conditions
VCC = 3.3V
IO=3mA; VO=0.0V
CC = 3.3V
IO=3mA; VO=0.4V
CC = 3.3V
IO=3mA; VO=0.8V
CC = 3.3V
Min Typ Max Unit
32
36
42
62
Ω
Ω
Ω
Ω
V
RON
Switch resistance
V
V
IO=3mA; VO=1.5V
Status pins (Y_HPD)
VCC = 3.465V
VI (max) = 5.3V on
isolated HPD port
Y= 0.0V
II(leak)
Input leakage current
0.1
+2
5
µA
µA
VCC = 0V;
(Y-port) = 0V;
(A-port) = 5.3V;
(B-port) = 5.3V
IOFF
Power down leakage current
Status pins (A_HPD, B_HPD)
VI=0V, VCC=3.3V, T= 25°C
F = 1 MHz
Switch off capacitance
CI/O
5
9
pF
pF
Switch on capacitance
VCC = 3.3V
24
Ω
Ω
IO=3mA; VO=0.0V
RON
Switch resistance
VCC = 3.3V
150
IO=3mA; VO=5.0V
1. Measured by voltage drop between channels at the indicated current through the switch. On-resistance is determined by
the lower of the two voltages.
2. Flatness is defined as the difference between the RONMAX and the RONMIN of the on resistance over the specified range.
3. ∆RON measured at the same VCC, temperature and voltage level.
12/26
STHDMI002A
DC electrical characteristics
6.1
Capacitance
T = 25°C, f = 1MHz
A
Table 6.
Symbol
Capacitance
Parameter
Test conditions
Min
Typ
2
Max
3
Unit
pF
CIN
COFF
CON
V
IN = 0V
IN = 0V
Input capacitance
V
Port x0 to Port x1, Switch off (Note 4)
4
6
pF
Capacitance switch on (x to x0 or x to x1) (1)
VIN = 0V
6
12
pF
1. x = Port Y; x0 = Port A; x1 = Port B
6.2
Power supply characteristics
T = -40 to +85 °C
A
Table 7.
Symbol
Power supply characteristics
Parameter
Test conditions
Min
Typ
Max
Unit
V
CC = 3.465 V,
ICC
Quiescent power supply current
50
500
µA
VIN = VCC or GND
6.3
Dynamic electrical characteristics
T = -40 to +85 °C, V = 3.3V 5%
A
CC
Dynamic electrical characteristics
Parameter
Table 8.
Symbol
Test conditions
Min
Typ
Max
Unit
XTALK
RL = 100Ω, f = 370MHz
RL = 100Ω, f = 825MHz
RL = 100Ω, f = 370MHz
RL = 100Ω, f = 825MHz
Non-adjacent channel Cross-talk
-32
-31
dB
dB
OIRR
Off Isolation
-36
dB
-30
dB
BW
DR
-3dB bandwidth
850
1.65
MHz
Gbps
Data rate per channel
13/26
DC electrical characteristics
STHDMI002A
6.4
Dynamic switching characteristics
T = -40 to +85 °C, V = 3.3V 5%
A
CC
Dynamic switching characteristics
Parameter
Table 9.
Symbol
Test conditions
Min Typ Max Unit
VCC = 3.135V to 3.465V
VCC = 3.135V to 3.465V
VCC = 3.135V to 3.465V
tPD
Propagation delay
0.30
6.5
ns
ns
ns
tPZH, PZL
t
Line Enable Time, SEL to x to x0 or x to x1
PHZ, tPLZ
Line Disable Time, SEL to x to x0 or x to x1
0.5
0.5
9
t
6.5
8.5
Output skew between center port to any
other port
VCC = 3.135V to 3.465V
VCC = 3.135V to 3.465V
tSK(O)
0.1
0.1
0.2
0.2
ns
ns
Skew between opposite transition of the
same output (tPHL - tPLH)
tSK(P)
DDC I/O pins
Propagation delay from A_DDC_SDA/
B_DDC_SDA to Y_DDC_SDA or
A_DDC_SCL/B_DDC_SCL to
Y_DDC_SCL or
tPD(DDC)
CL = 10pF
2.5
ns
Y_DDC_SDA to A_DDC_SDA/
B_DDC_SDA
V
CC = 3.135V to 3.465V
CC = 3.135V to 3.465V
t
PZH, tPZL
Line Enable Time, SEL to x to x0 or x to x1
Line Disable Time, SEL to x to x0 or x to x1
6.5
6.5
9
ns
ns
V
tPHZ, PLZ
t
8.5
Status pins (Y_HPD, A_HPD, B_HPD)
Propagation delay (from Y_HPD to the
tPD(HPD)
CL = 10pF
2.5
ns
active port of HPD)
VCC = 3.135V to 3.465V
VCC = 3.135V to 3.465V
tPZH, PZL
t
Line Enable Time, SEL to x to x0 or x to x1
PHZ, tPLZ
Line Disable Time, SEL to x to x0 or x to x1
6.5
6.5
9
ns
ns
t
8.5
Note:
x = Port Y; x0 = Port A; x1 = Port B
6.5
ESD performance
Table 10. ESD performance
Symbol
Parameter
MIL STD 883 method 3015 (all pins)
Test conditions
Min
Typ
Max Unit
ESD
Human Body Model (HBM)
2
kV
14/26
STHDMI002A
Test circuit for electrical characteristics
7
Test circuit for electrical characteristics
Figure 4. Timing measurement test circuit
Note: 1 CL = Load capacitance: includes jig and probe capacitance.
2 RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Figure 5. Bandwidth measurement test circuit
Note:
C includes probe and jig capacitance
L
Frequency response is measured at the output of the ON channel. For example, when
VSEL = 0 and Y0+ is the input, the output is measured at A0+. All unused analog I/O ports are
left open.
HP8753ES set up:
Average = 4
RBW = 3kHz
VBIAS = 0.35V
ST = 2s
P1 = 0dBm
15/26
Test circuit for electrical characteristics
STHDMI002A
Figure 6. Crosstalk measurement test circuit
Note: 1 CL includes probe and jig capacitance
2 A 50Ω termination resistor is needed to match the loading network analyzer
Crosstalk is measured at the output of the non-adjacent ON channel. For example, when
VSEL = 0, and Y0- is the input, the output is measured at Y1-. All unused analog input ports (Y)
are connected to GND and output ports (A,B) are left open.
HP8753ES set up:
Average = 4
RBW = 3kHz
VBIAS = 0.35V
ST = 2s
P1 = 0dBm
16/26
STHDMI002A
Test circuit for electrical characteristics
Figure 7. Off-isolation measurement test circuit
Note: 1 CL includes probe and jig capacitance
2 A 50Ω termination resistor is needed to match the loading network analyzer
Off-isolation is measured at the output of the OFF channel. For example, when VSEL=0, and
Y0- is the input, the output is measured at B0-. All unused analog input ports (Y) are connected
to GND and output ports (A,B) are left open.
HP8753ES set up:
Average = 4
RBW = 3kHz
VBIAS = 0.35V
ST = 2s
P1 = 0dBm
17/26
Timing waveforms
STHDMI002A
8
Timing waveforms
Figure 8. Propagation delay times
Figure 9. Enable and disable times
18/26
STHDMI002A
Timing waveforms
Figure 10. Output skew
Figure 11. Pulse skew
19/26
Application information
STHDMI002A
9
Application information
9.1
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended
to always apply VCC before applying any signals to the input/output or control pins.
9.2
9.3
Supply bypassing
Bypass each of the V pins with 0.1µF and 1nF capacitors in parallel as close to the device as
CC
possible, with the smaller-valued capacitor as close to the V pin of the device as possible.
CC
Differential traces
The high-speed TMDS inputs are the most critical parts for the device. There are several
considerations to minimize discontinuities on these transmission lines between the connectors
and the device.
a) Maintain 100-Ω differential transmission line impedance into and out of the
STHDMI002A.
b) Keep an uninterrupted ground plane below the high-speed I/Os.
c) Keep the ground-path vias to the device as close as possible to allow the shortest
return current path.
d) Layout of the TMDS differential inputs should be with the shortest stubs from the
connectors.
Output trace characteristics affect the performance of the STHDMI002A. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance and
termination resistor. Run the differential traces close together to minimize the effects of the
noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities in the
differential trace layout. Avoid 90 degree turns and minimize the number of vias to further
prevent impedance discontinuities.
20/26
STHDMI002A
Package mechanical data
10 Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK packages.
These packages have a Lead-free second level interconnect . The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
21/26
Package mechanical data
STHDMI002A
Figure 12. TQFP48 package dimensions
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STHDMI002A
Package mechanical data
Figure 13. TQFP48 Tape and reel dimensions
Tape & Reel TQFP48 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
22.4
9.7
0.882
0.382
0.382
0.091
0.161
0.476
Ao
Bo
Ko
Po
P
9.5
9.5
0.374
0.374
0.083
0.153
0.468
9.7
2.1
2.3
3.9
4.1
11.9
12.1
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Order codes
STHDMI002A
11 Order codes
Table 11. Order codes
Part number
Temperature range
–65°C to +150°C
Package
Packing
STHDMI002ABTR
TQFP48
Tape and reel
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STHDMI002A
Revision history
12 Revision history
Table 12. Revision history
Date
Revision
Change
10-Oct-2006
1
First release
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STHDMI002A
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