RHF1401KSO1 [STMICROELECTRONICS]
Rad-hard 14-bit 20Msps 85mW A/D converter; 抗辐射的14位20Msps的85mW的A / D转换器
| 型号： | RHF1401KSO1 |
| 厂家： | 
ST |
| 描述： | Rad-hard 14-bit 20Msps 85mW A/D converter |
| 文件： | 总29页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RHF1401
Rad-hard 14-bit 20Msps 85mW A/D converter
Features
SO-48 package
■ Ssingle +2.5V supply operation
■ Low power: 85mW @ 20Msps
■ High linearity: +/- 0.3 bit DNL
■ SFDR = 90dB typ. SINAD = 73dB typ.
@ F = 20Msps, F = 5MHz
s
in
■ 2.5V/3.3V compatible digital I/O
■ Switchable on/off built-in reference voltage
■ Hermetic package
Pin connections (top view)
1
48
■ Rad-hard: 300kRad(Si) TID
■ Failure immune (SEFI) and latchup immune
2
(SEL) up to 120 MeV-cm /mg at 2.7V and
125°C
■ Qml-V qualification on-going, smd 5962-06260
Applications
24
25
■ Digital communication satellites
■ Space data acquisition systems
■ Aerospace instrumentation
Specifically designed for optimizing power
consumption, the RHF1401 only dissipates
85mW at 20Msps, while maintaining a high level
of performance. It integrates a proprietary track-
and-hold structure to ensure an effective
resolution bandwidth of 70MHz.
■ Nuclear and high-energy physics
Description
The RHF1401 is a 14-bit, 20MHz maximum
sampling frequency analog-to-digital converter
using pure (ELDRS-free) CMOS 0.25µm
technology combining high performance, radiation
robustness and very low power consumption.
A voltage reference is integrated in the circuit to
simplify the design and minimize external
components. A tri-state capability is available on
the outputs, to allow common bus sharing.
A data-ready signal which is raised when the data
is valid on the output can be used for
synchronization purposes.
The RHF1401 is based on a pipeline structure
and digital error correction to provide excellent
static linearity. Its very low internal noise permits
to achieve more than 11.8 ENOB with a 2.2V
5MHz input.
pp
The RHF1401 has an operating temperature
range of -55°C to +125°C and is available in a
small 48-pin hermetic SO-48 package.
October 2007
Rev 2
1/29
www.st.com
29
Contents
RHF1401
Contents
1
2
3
4
5
6
7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 8
Electrical characteristics (unchanged after 300kRad) . . . . . . . . . . . . . . 9
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
Analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1.1
7.1.2
Setting the analog input range and references . . . . . . . . . . . . . . . . . . . 15
Driving the analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2
7.3
7.4
7.5
7.6
Clock signal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power consumption optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low sampling rate recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Digital inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PCB layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1
8.2
Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10
11
2/29
RHF1401
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
RHF1401 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
S0-48 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Linearity vs. F , internal references, F = 20 MHz, I = 40 mA. . . . . . . . . . . . . . . . . . . . 12
in
s
cca
Linearity vs. F , external references (REFP = 1 V), F = 20 MHz, I = 28 mA . . . . . . . . 12
in
s
cca
Distortion vs. F , internal refs, F = 20 MHz, I = 40 mA . . . . . . . . . . . . . . . . . . . . . . . . . 12
in
s
cca
Distortion vs. F , external ref, (REFP = 1 V) F = 20 MHz; I = 28 mA . . . . . . . . . . . . . 12
in
s
cca
nd
nd
rd
2
2
& 3 harmonics vs. F , internal refs, F = 20 MHz; I = 40 mA. . . . . . . . . . . . . . . . . 13
& 3 harmonics vs. F , external ref REFP=1 V, F =20MHz; I =28mA. . . . . . . . . . . 13
in s cca
rd
in
s
cca
Figure 10. Single-tone 16K FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Single-tone 16K FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. SFDR vs. input amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. Static parameter: differential non linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. Static parameter: integral non linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. Linearity vs. REFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
(1)
Figure 16. Distortion vs. REFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. External reference setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 18. Linearity vs. F
Figure 19. Distortion vs. F
s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
s
Figure 20. ADC input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 21. Differential input configuration with transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. AC-coupled differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 23. Analog current consumption vs. F according to value of R polarization resistances:
s
pol
internal references (for F < 10MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
in
Figure 24. Impact of clock frequency on RHF1401 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25. CLK signal derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. SO-48 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/29
Block diagram
RHF1401
1
Block diagram
Figure 1.
RHF1401 block diagram
VREFP
REFMODE
VIN
INCM
VINB
Reference
circuit
stage
1
stage
2
stage
n
IPOL
VREFM
DFSB
OEB
Sequencer-phase shifting
Digital data correction
VCCBE +2.5/3.3V
CLK
Timing
GNDBE
DR
DO
TO
Buffers
AVCC +2.5V
AGND
D13
OR
DGND AVDD +2.5V
2
Pinout
Figure 2.
S0-48 pin connections (top view)
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
4/29
RHF1401
Table 1.
Pinout
Pin descriptions
Description
Pin
Name
Observations
Pin
Name
Description
Observations
2.5 V/3.3 V CMOS
input
1
GNDBI
Digital buffer ground
0 V
25
REFMODE Ref. mode control input
2.5 V/3.3 V CMOS
input
2
3
GNDBE
VCCBE
Digital buffer ground
0 V
26
27
OEB
Output enable input
Digital buffer power
supply
2.5 V/3.3 V CMOS
input
2.5 V/3.3 V
DFSB
Data format select input
4
5
NC
NC
Non connected
Non connected
28
29
AVCC
AVCC
Analog power supply
Analog power supply
2.5 V
2.5 V
CMOS output
(2.5 V/3.3 V)
6
OR
D13(MSB)
D12
D11
D10
D9
Out of range output
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
AGND
IPOL
Analog ground
0 V
Most significant bit
output
CMOS output
(2.5 V/3.3 V)
7
Analog bias current input
Top voltage reference
CMOS output
(2.5 V/3.3 V)
8
Digital output MSB
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output LSB
VREFP
VREFM
AGND
VIN
1 V
CMOS output
(2.5 V/3.3 V)
9
Bottom voltage reference 0 V
CMOS output
(2.5 V/3.3 V)
10
11
12
13
14
15
16
17
18
19
20
21
Analog ground
0 V
1 V
0 V
1 V
0 V
CMOS output
(2.5 V/3.3 V)
Analog input
pp
pp
CMOS output
(2.5 V/3.3 V)
D8
AGND
VINB
Analog ground
CMOS output
(2.5 V/3.3 V)
D7
Inverted analog input
Analog ground
CMOS output
(2.5 V/3.3 V)
D6
AGND
INCM
AGND
AVCC
AVCC
DVCC
DVCC
DGND
CMOS output
(2.5 V/3.3 V)
D5
Input common mode
Analog ground
0.5 V
0 V
CMOS output
(2.5 V/3.3 V)
D4
CMOS output
(2.5V /3.3 V)
D3
Analog power supply
Analog power supply
Digital power supply
Digital power supply
Digital ground
2.5 V
2.5 V
2.5 V
2.5 V
0 V
CMOS output
(2.5 V/3.3 V)
D2
CMOS output
(2.5 V/3.3 V)
D1
CMOS output
(2.5 V/3.3 V)
D0(LSB)
DR
CMOS output
(2.5 V/3.3 V)
(1)
Data ready output
Digital buffer power
supply
2.5 V compatible
CMOS input
22
23
24
VCCBE
GNDBE
VCCBI
2.5 V/3.3 V
0 V
46
47
48
CLK
Clock input
Digital buffer ground
DGND
DGND
Digital ground
Digital ground
0 V
0 V
Digital buffer power
supply
2.5 V
1. See load considerations in Section 3: Timing.
5/29
Timing
RHF1401
3
Timing
Table 2.
Symbol
Timing characteristics
Parameter
Test conditions
Min
Typ
Max
Unit
Fs
Sampling frequency(1)
Sampling clock cycle(1)
Clock duty cycle
1.5
50
20
MHz
ns
Tck
DC
TC1
TC2
667
F = 20 Msps
50
25
25
%
s
Clock pulse width (high)
Clock pulse width (low)
ns
ns
Data output delay (fall of
clock to data valid) (2)
Tod
Tpd
Tdr
10 pF load capacitance
5
7.5
8.5
0.5
13
ns
Data pipeline delay
8.5
8.5 cycles
cycles
Data ready rising edge
delay after data change
Falling edge of OEB to
digital output valid data
Ton
Toff
1
1
ns
ns
Rising edge of OEB to
digital output tri-state
T
Data rising time
Data falling time
10 pF load capacitance
10 pF load capacitance
6
3
ns
ns
rD
TfD
1. See clock recommendations in Section 7.2: Clock signal requirements on page 19
2. See Figure 3 and discussion below.
6/29
RHF1401
Timing
Figure 3.
Timing diagram
N+5
N+6
N+4
N+7
N-1
N+3
N+8
N
N+2
N+9
N+1
CLK
OEB
Tpd + Tod
Tdr
Ton
Toff
Tod
DATA
OUT
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-1
N
DR
HZ state
The input signal is sampled on the rising edge of the clock while digital outputs are
synchronized on the falling edge of the clock.
Load considerations
The size of the internal output buffers limits the maximum load on the data output signals
and Data Ready to 10pF equivalent load. In particular, the shape and amplitude of the Data
Ready signal, toggling at the clock frequency can be weakened by a higher equivalent load.
In applications that impose higher load conditions, it is recommended to use the falling edge
of the master clock instead of the Data Ready signal. This is possible because the output
transitions are internally synchronized with the falling edge of the clock. For implementation
information, refer to Section 7.2: Clock signal requirements on page 19.
An alternative is to re-buffer the DR signal externally to avoid any risk of modifying the clock
signal.
7/29
Absolute maximum ratings and operating conditions
RHF1401
4
Absolute maximum ratings and operating conditions
Table 3.
Symbol
Absolute maximum ratings
Parameter
Values
Unit
AVCC
DVCC
VCCBI
VCCBE
IDout
Analog supply voltage(1)
Digital supply voltage(1)
0 to 3.3
0 to 3.3
0 to 3.3
0 to 3.6
-100 to 100
-65 to +150
22
V
V
Digital buffer supply voltage(1)
Digital buffer supply voltage(1)
Digital output current
V
V
mA
°C
°C/W
Tstg
Storage temperature
Rthjc
Junction - case thermal resistance
Electrostatic discharge
– HBM: human body model (2)
ESD
kV
2
1. All voltage values, except differential voltage, are with respect to the network ground terminal. The
magnitude of input and output voltages must never exceed -0.3 V or VCC+0.3 V.
2. Human body model: 100pF discharged through a 1.5kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
Table 4.
Symbol
Operating conditions
Parameter
Test conditions
Min
Typ
Max Unit
AVCC
DVCC
VCCBI
VCCBE
VREFP
Analog supply voltage
2.3
2.3
2.3
2.3
0.5
2.5
2.5
2.5
2.5
1
2.7
2.7
2.7
3.4
1.4
V
V
V
V
V
Digital supply voltage
Digital internal buffer supply
Digital output buffer supply
Forced top voltage reference
Bottom internal reference
voltage
VREFM
0
0
0.5
V
8/29
RHF1401
Electrical characteristics (unchanged after 300kRad)
Electrical characteristics (unchanged after 300kRad)
Test conditions are the following (unless otherwise specified):
5
●
●
●
●
●
●
AV = DV = V
= 2.5 V
CCB
CC
CC
F = 20 Msps
s
F = 2 MHz
in
V @ -1 dBSF
in
V
= 0 V
REFM
T
= 25° C
amb
Table 5.
Symbol
Analog inputs
Parameter
Test conditions
Min
Typ
Max
Unit
VIN-VINB Full scale reference voltage VREFP= 1 V
2
8
Vpp
pF
Cin
Zin
Input capacitance
Input impedance
F = 20 Msps
3.3
kOhms
s
Effective resolution
bandwidth(1)
ERB
70
MHz
1. See Section 8: Definitions of specified parameters on page 24 for more information.
Table 6.
Symbol
Internal references
Parameter
Test conditions
Min
Typ
Max
Unit
REFMODE=’0’
internal reference on
30
Ohm
Output resistance of
internal ref
Rout
REFMODE=’1’
internal reference off
7.5
kOhm
Top internal reference
voltage
VREFP
REFMODE=’0’
0.84
0
V
V
V
VREFM Bottom internal ref. voltage REFMODE=’0’
Input common mode
VINCM
REFMODE=’0’
0.44
voltage
Table 7.
Symbol
External references
Parameter
Test conditions
Min
Typ
Max
Unit
Forced top reference
voltage
VREFP
REFMODE=’1’
0.8
0
1.4
0.2
1
V
V
V
VREFM Forced bottom ref. voltage REFMODE=’1’
Forced common mode
VINCM
REFMODE=’1’
0.4
voltage
9/29
Electrical characteristics (unchanged after 300kRad)
RHF1401
Unit
See Figure 14
Table 8.
Symbol
Static accuracy
Parameter
Test conditions
Min
Typ
Max
DNL
INL
Differential non linearity(1)
Integral non linearity(2)
Fs=1.5 Msps
Fs=1.5 Msps
+/-0.3
+/-2
LSB
LSB
Monotonicity and no
missing codes
Guaranteed
1. SeeFigure 13 and Section 8: Definitions of specified parameters on page 24 for more information.
2. See Figure 14 and Section 8: Definitions of specified parameters on page 24 for more information.
Table 9.
Symbol
Digital inputs and outputs
Parameter Test conditions
Min
Typ
Max
Unit
Clock input
VIL
VIH
Logic "0" voltage
Logic "1" voltage
DVCC = 2.5 V
DVCC = 2.5 V
0
0
0.8
2.5
V
V
2.0
Digital inputs
0.25 x
VCCBE
VIL
VIH
Logic "0" voltage
Logic "1" voltage
VCCBE = 2.5 V
VCCBE = 2.5 V
0
V
V
0.75 x
VCCBE
VCCBE
Digital outputs
VOL
VOH
Logic "0" voltage
IOL = -1 mA
IOH = 1 mA
0
0.2
V
V
VCCBE
-0.2
Logic "1" voltage
High impedance leakage
current
IOZ
CL
OEB set to VIH
-15
15
15
µA
pF
Output load capacitance
10/29
RHF1401
Electrical characteristics (unchanged after 300kRad)
Table 10. Dynamic characteristics
Symbol
Parameter(1)
Test conditions
Min
Typ
Max
Unit
Fin = 10 MHz,
internal reference
-91
Spurious free dynamic
range
SFDR
dBFS
Fin = 10 MHz,
VREFP =1 V
-89
70
Fin = 10 MHz,
internal reference
SNR
THD
Signal to noise ratio
dB
dBc
dB
Fin= 10 MHz,
VREFP = 1 V
71.5
-86
-85
70
Fin= 10 MHz,
internal reference
Total harmonic distortion
Fin= 10 MHz,
VREFP = 1 V
Fin= 10 MHz,
internal reference
Signal to noise and
distortion ratio
SINAD
Fin= 10 MHz,
VREFP = 1 V
71
Fin= 10 MHz,
internal reference
11.5
11.7
ENOB Effective number of bits
bits
Fin= 10 MHz,
VREFP = 1 V
1. See Section 8: Definitions of specified parameters on page 24 for more information.
Higher values of SNR, SINAD and ENOB can be obtained by increasing the analog input full
scale range. This is illustrated in Figure 11 on page 13, Figure 18, and Figure 19 on page 17
with V
= 1.25V, and also in Figure 15 and Figure 16 on page 16 with V
up to 1.4V.
REFP
REFP
11/29
Typical performance characteristics
RHF1401
6
Typical performance characteristics
Because of its intrinsic high-speed low-power capabilities, most of the characterization
measurements for the RHF1401 were done in the analog frequency range from 1MHz to
100MHz.
An evaluation board designed to operate in this range, and including a transformer to
generate on-board differential signals to input to the RHF1401 was used in characterization
testing. This configuration is illustrated in Figure 21 on page 18.
For best performance, the RHF1401 also requires a high enough sampling frequency or, in
other terms, that the clock period is not too long, to avoid current leakage which would
impact conversion accuracy. The recommended lowest sampling frequency is 1.5Msps.
Note that under 1.2Msps, the RHF1401 performance is degraded. For more information on
sampling frequency, see Section 7.2: Clock signal requirements, and Section 7.3: Power
consumption optimization.
Figure 4.
Linearity vs. F , internal references,
Figure 5.
Linearity vs. F , external references
in
in
F = 20 MHz, I = 40 mA
(REFP = 1 V), F = 20 MHz, I = 28 mA
s
cca
s cca
80
12
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11
80
77
74
71
68
65
12
77
74
71
68
11.8
ENO
ENOB
11.6
11.4
11.2
11
SINA
SNR
SNR
SINAD
25
5
15
Fin (Mhz)
25
65
0
5
10
15
Fin (Mhz)
20
30
Figure 6.
Distortion vs. F , internal refs,
Figure 7.
Distortion vs. F , external ref,
in
in
F = 20 MHz, I
= 40 mA
(REFP = 1 V) F = 20 MHz; I = 28 mA
s
cca
s cca
-70
-75
-70
-75
-80
-85
-90
-95
-80
THD
THD
SFDR
-85
-90
SFDR
15
-95
-100
5
-100
10
20
25
30
0
5
10
15
Fin (Mhz)
20
25
30
Fin (Mhz)
12/29
RHF1401
Figure 8.
Typical performance characteristics
nd
rd
nd
rd
2
& 3 harmonics vs. F , internal Figure 9.
2
& 3 harmonics vs. F , external
in
in
refs, F = 20 MHz; I
= 40 mA
ref REFP=1 V, F =20MHz; I =28mA
s
cca
s cca
-60
-65
-60
-65
-70
-70
-75
-75
-80
-80
H3
10
-85
-85
H2
-90
-90
H2
-95
-95
-100
-105
-110
H3
-100
-105
-110
5
15
Fin (Mhz)
20
25
30
0
5
10
15
20
25
30
Fin (Mhz)
Figure 10. Single-tone 16K FFT
0
-2 0
-4 0
-6 0
-8 0
-1 0 0
-1 2 0
-1 4 0
-1 6 0
-1 8 0
0
1 0
5
F ( M h z )
1. At Fs = 20 Msps, internal references, Fin = 5 MHz, Icca = 40 mA, Vin@-1 dBFS,
SFDR = -89.3 dBc, THD = -84.5 dBc, SNR = 70.5 dB, SINAD = 70.3 dB, ENOB = 11.5 bits
Figure 11. Single-tone 16K FFT
2 0
0
-2 0
-4 0
-6 0
-8 0
-1 0 0
-1 2 0
-1 4 0
-1 6 0
0
5
1 0
F ( M h z )
1. At Fs=20 Msps, external references, Fin= 5 MHz, Icca = 40 mA, Vin@-1 dBFS, VREFP= 1.25V, SFDR = -87.5 dBc, THD = -
85.4 dBc, SNR = 73.3 dB, SINAD = 73 dB, ENOB = 11.84 bits
13/29
Typical performance characteristics
RHF1401
Figure 12. SFDR vs. input amplitude
-20
-30
-40
-50
-60
SFDR(dBc)
-70
-80
-90
SFDR(dBFS)
-20
-100
-110
-30
-25
-15
-10
-5
0
SFSR(dB)
1. (Full scale = 2 x 0.86 V), Fs = 20 Msps, Fin = 5 MHz, Icca = 40 mA
Figure 13. Static parameter: differential non linearity
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
4
4
0
3276.6
6553.2
9829.8
1.31 10
1.64 10
1. Fs = 1.5 Msps acquisition over 128 DC linear ramping input signals
Figure 14. Static parameter: integral non linearity
3
2.4
1.8
1.2
0.6
0
0.6
1.2
1.8
2.4
3
4
4
0
3276.6
6553.2
9829.8
1.31 10
1.64 10
1. Fs = 1.5 Msps acquisition over 128 DC linear ramping input signals
14/29
RHF1401
Application information
7
Application information
The RHF1401 is a high speed analog-to-digital converter based on a pipeline architecture
and the ST 0.25µm CMOS process in order to achieve the best performance in terms of
linearity, power consumption and radiation hardness.
The pipeline structure consists of 14 internal conversion stages in which the analog signal is
fed and sequentially converted into digital data.
Each of the first 13 stages consists of an analog to digital converter, a digital to analog
converter, a sample and hold and an amplifier with a gain of 2. A 1.5-bit conversion
resolution is done at each stage. The last stage is a 2-bit flash ADC. Each resulting LSB-
MSB couple is then time-shifted to recover from the delay caused by conversion. Digital data
correction completes the processing by recovering from the redundancy of the (LSB-MSB)
couple for each stage. The corrected data is output through the digital buffers.
Signal input is sampled on the rising edge of the clock while digital outputs are synchronized
on the falling edge of the clock.
The advantages of this converter reside in the combination of a SEFI-free pipeline
architecture and advanced low-voltage CMOS technology. The highest dynamic
performance is achieved while consumption remains at the lowest level.
7.1
Analog input configuration
7.1.1
Setting the analog input range and references
To optimize the high resolution and speed of the RHF1401, we strongly advise you to drive
the analog input differentially. The half full-scale of RHF1401 is adjusted through the voltage
values of V
and V
:
REFP
REFM
V
IN – VINB = Full Scale = 2(VREFP – VREFM
)
The differential analog input signal always has a common mode voltage of:
V
IN + VINB
VCM = ---------------------------
2
To select the references according to the constraints of your particular application, a control
pin, REFMODE, allows you to switch from internal to external references.
Internal references, common mode:
When REFMODE is set to V level, the RHF1401 operates with its own reference voltage
IL
generated by its internal bandgap. If the VREFM pin is connected externally to the analog
ground while VREFP is set to its internal voltage (0.86 V), the full scale of the ADC is
2 x 0.86 = 1.72V.
In this case, VREFP, VREFM and INCM are low impedance outputs. The INCM pin (voltage
generator 0.46 V) may be used to supply the common mode, CM, of the analog input signal.
15/29
Application information
RHF1401
External references, common mode:
In applications that require a different full scale magnitude, it is possible to force the VREFP
and VREFM pins from an external voltage reference device. In this configuration, the
RHF1401 has better performance, as illustrated in Figure 15 and Figure 16.
Setting REFMODE to V level will put the internal references in standby mode, turning
IH
VREFP, VREFM and INCM into high impedance inputs that have to be forced by external
references.
(1)
(1)
Figure 15. Linearity vs. REFP
Figure 16. Distortion vs. REFP
80
12.4
12.2
12
-70
-75
-80
77
ENOB
74
71
68
65
SINAD
11.8
11.6
11.4
11.2
11
THD
-85
-90
SNR
SFDR
-95
-100
0.8
0.9
1
1.1
REFP (V)
1.2
1.3
1.4
0.8
0.9
1
1.1
REFP (V)
1.2
1.3
1.4
1. Fin = 5 MHz; Fs = 20 Mhz; Icca = 26 mA; VINCM=0.45 V
Using the RHF1401 with an external voltage reference device yields optimum performance
when configured as shown in Figure 17.
Figure 17. External reference setting
1kΩ
“1”
330pF 10nF 4.7µF
REFMODE
VCCA VREFP
VIN
RHF1401
external
reference
VINB
VREFM
Note:
In multi-channel applications, the high impedance input of the references allows you to drive
several ADCs with only one voltage reference device.
In the case of a 1.25V external reference, the full scale is increased to 2.5 V differential.
pp
The improved dynamic performance is shown in Figure 18 and Figure 19.
16/29
RHF1401
Application information
(1)
(1)
Figure 18. Linearity vs. F
Figure 19. Distortion vs. F
s
s
-70
-75
80
77
74
71
68
65
12.1
12
ENOB
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
-80
SNR
-85
SINAD
THD
-90
SFDR
-95
-100
3
5
7
9
11 13 15 17 19 21
Fs (Mhz)
3
5
7
9
11 13 15 17 19 21
Fs (Mhz)
1. At Fin = 5 MHz, using external REFP = 1.25 V, Icca optimized, VINCM = 0.65 V
The magnitude of the analog input common mode, CM should stay close to V
levels will introduce more distortion.
/2. Higher
REFP
7.1.2
Driving the analog inputs
The RHF1401 is designed to be differentially driven for better noise immunity.
Measurements done with single-ended signals show reduced levels of performance.
The switch-capacitor input structure of RHF1401 has a high input impedance (3.3 kΩ at
F = 20MHz) but it is not constant in time (see the equivalent input circuit in Figure 20)
S
because, at the end of each conversion, the charge update of the sampling capacitor draws
or injects a small transient current on the input signal.
One method of masking this transient current is a low-pass RC filter as shown in Figure 21
and Figure 22. A capacitor with a higher value than the sampling capacitor of 2.4 pF,
mounted in parallel with the two analog input signals, will absorb the transient glitches.
Figure 20. ADC input equivalent circuit
AVcc
Switch at Fs
VIN
VIN
Cs=2.4pF
AGND
17/29
Application information
RHF1401
Single-ended signal with transformer
Using an RF transformer is an efficient method of achieving high performance.
Figure 21 shows the schematic view. The input signal is fed to the primary of the
transformer, while the secondary drives both ADC inputs.
Figure 21. Differential input configuration with transformer
ADT1-1
Analog source
1:1
VIN
RHF1401
50Ω
100pF
VINB
INCM
330pF 10nF
4.7µF
The internal common mode voltage of the ADC (INCM) is connected to the center-tap of the
secondary of the transformer in order to bias the input signal around this common voltage,
internally set to 0.46 V. The INCM is decoupled to maintain a low noise level on this node.
Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You
might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on
the analog signal source.
AC coupled differential input:
Figure 22 represents the biasing of a differential input signal in AC-coupled differential input
configuration. Both inputs V and V
are centered around the common mode voltage CM,
IN
INB
that can be forced through INCM or supplied externally (in this case, INCM may be left
internal).
Figure 22. AC-coupled differential input
VIN
10nF
50Ω
100kΩ
33pF
RHF1401
INCM
common
mode
100kΩ
VINB
10nF
50Ω
18/29
RHF1401
Application information
7.2
Clock signal requirements
The signal applied to the CLK pin is critical to obtain full performance from the RHF1401. It
is recommended to use a 0V to 2.5V square signal with fast transition times, and to place
proper termination resistors as close as possible to the device.
It is the rising edge of the clock signal that determines the sampling instant. The jitter
associated with this instant must be as low as possible to avoid SNR degradation on fast
moving input signals. To achieve less than 0.5 LSB error, the total jitter T must satisfy the
j
following condition for a full scale input signal:
1
--------------------------------------
Tj <
π ⋅ Fin ⋅ 2n + 1
For example, the total jitter with 14-bit resolution for a 10 MHz full scale input should be no
more than 1 picosecond (rms).
In most cases, it is the clock signal jitter that is the major contributor to the total jitter.
Therefore, you must pay particular attention to the clock signal in the case of acquisition of
fast signals with a low frequency clock. For further considerations on low sampling
conditions, refer to Section 7.4 on page 20.
The clock signal must be active when you power up the device. Clock gating (stopping the
clock) is not recommended due to possible undertermined states inside the circuit when the
clock is off.
7.3
Power consumption optimization
The internal architecture of the RHF1401 makes it possible for you to optimize the analog
power consumption depending on the sampling frequency by adjusting the R resistor.
pol
This resistor is placed between the IPOL pin and the analog ground.
Input signal below 10MHz
Depending of the application sampling speed, the R value should be set between 120 kΩ
pol
(low sampling speed, low current) and 40 kΩ (high sampling speed, high current). With a low
sampling speed, you should use a high value for R (for example 100 kΩ) in order to
pol
minimize the power consumption, often critical in space applications. This method is
efficient with an input signal in the range from DC up to 10MHz.
With a sampling frequency of 20 MHz, an R value of 41 kΩ provides optimized power
pol
consumption.
Figure 23 shows the optimized power consumption of the circuit versus the sampling
frequency in two different configurations:
●
REFMODE=0 internal references with I
in the range 30-40 mA
in the range 20-30 mA
AVCC
●
REFMODE=1 external references with I
AVCC
19/29
Application information
RHF1401
Figure 23. Analog current consumption vs. F according to value of R polarization
s
pol
resistances: internal references (for F < 10MHz)
in
45
140
120
100
80
Rpol
40
35
30
25
20
REFMODE=0
60
40
REFMODE= 1
20
0
5
7
9
11
13
Fs (Mhz)
15
17
19
21
Input signal above 10MHz
However, with a higher frequency input signal (for example, in the 10-70MHz range), a high
value does not supply enough current to the internal amplifiers, thus resulting in
R
pol
degraded SNR and THD performance. With an input signal in this range, the recommended
value for R is in the 30-50 kΩ range.
pol
7.4
Low sampling rate recommendations
The RHF1401 offers a wide range of sampling rates from 1.5Msps to 20Msps with the
minimum power consumption. However, under the minimum, the performance of the device
deteriorates. Figure 24 shows the degradation in performance at sampling frequencies
under 1.2Msps. The recommended minimum sampling frequency is 1.5Msps.
20/29
RHF1401
Application information
Figure 24. Impact of clock frequency on RHF1401 performance
80
70
60
50
40
30
20
10
0
Fs = 1.0 Msps
Fs = 1.2 Msps
Fs = 1.5 Msps
1
5
15
25
Fin
In the case of under-sampling, that is when the sampling rate is much lower than the input
signal frequency (for example a 2Msps sampling rate with a 41.3MHz input signal), there are
two critical parameters to consider:
●
The value of the R resistor
pol
●
The clock jitter
7.5
Digital inputs/outputs
Data format select (DFSB)
When set to low level (V ), the digital input DFSB provides a two’s complement digital
IL
output MSB. This can be of interest when performing further signal processing.
When set to high level (V ), DFSB provides a standard binary output coding.
IH
Output enable (OEB)
When set to low level (V ), all digital outputs remain active and are in low impedance state.
IL
When set to high level (V ), all digital output buffers are in high impedance state. It results
IH
in lower consumption while the converter goes on sampling.
When OEB is set to low level again, the data is then delivered on the output with a very short
T
delay.
on
Out of range (OR)
This function is implemented on the output stage in order to set up an “Out of range” flag
whenever the digital data is over the full scale range.
Typically, there is a detection of all the data at ’0’ or all the data at ’1’. This ends up with an
output signal OR which is in low level state (V ) when the data is within the range, or in
OL
high level state (V ) when the data is out of the range.
OH
21/29
Application information
RHF1401
Data ready (DR)
The data ready output signal is an image of the clock being synchronized on the output data
(D0 to D13). This is a very helpful signal that simplifies the synchronization of the
measurement equipment or the controlling DSP.
As all other digital outputs, DR goes into high impedance state when OEB reaches high
level as described in Figure 3: Timing diagram on page 7.
Caution:
Because the driving force of data outputs and the DR signal is relatively low, it is
recommended to limit the equivalent load on these signals to 10-15pF maximum. This is to
avoid a weak signal when the RHF1401 is clocked at full speed (20Msps). The DR signal is
potentially the most affected because it has the highest frequency (20MHz maximum).
If the equivalent load on the data outputs is slightly higher than 15pF, you can avoid
resorting to external re-buffering of the data bus and DR signal by connecting the data bus
to the acquisition device directly without using the DR. In this case, you can obtain a good
validation signal from a derivation of the clock because the clock falling edge is used by the
RHF1401 internally to generate data output transitions. A series resistor of approximately
100-200 Ohms should be placed at the derivation to avoid the effect of current spikes on the
critical CLK node. This configuration is illustrated in Figure 25.
Figure 25. CLK signal derivation
D0-D13
DR
CLK
50Ω
ASIC or FPGA
above 15pF
100-200Ω
22/29
RHF1401
Application information
7.6
PCB layout precautions
To use the ADC circuits most efficiently at high frequencies, some precautions have to be
taken for power supplies:
●
First of all, the implementation of 4 separate proper supplies and ground planes
(analog, digital, internal and external buffer ones) on the PCB is recommended for high
speed circuit applications to provide low-inductance and low-resistance common
return.
●
●
●
The separation of the analog signal from the digital part and from the buffers power
supply is essential to prevent noise from coupling onto the input signal.
Power supply bypass capacitors must be placed as close as possible to the IC pins in
order to improve high frequency bypassing and reduce harmonic distortion.
Proper termination of all inputs and outputs is needed; with output termination
resistors, the amplifier load is resistive only and the stability of the amplifier is improved.
All leads must be wide and as short as possible especially for the analog input in order
to decrease parasitic capacitance and inductance.
●
●
To keep the capacitive loading as low as possible at digital outputs, short lead lengths
of routing are essential to minimize currents when the output changes. To minimize this
output capacitance, use buffers or latches close to the output pins. It is also helpful to
use 47 Ω to 56 Ω series resistors at the ADC output pins, located as close to the ADC
output pins as possible.
Choose component sizes as small as possible (SMD).
23/29
Definitions of specified parameters
RHF1401
8
Definitions of specified parameters
8.1
Static parameters
Static measurements are performed using the histograms method on a 2 MHz input signal,
sampled at 50 Msps, which is high enough to fully characterize the test frequency response.
The input level is +1 dBFS to saturate the signal.
Differential non linearity (DNL)
The average deviation of any output code width from the ideal code width of 1LSB.
Integral non linearity (INL)
An ideal converter exhibits a transfer function which is a straight line from the starting code
to the ending code. The INL is the deviation from this ideal line for each transition.
8.2
Dynamic parameters
Dynamic measurements are performed by spectral analysis, applied to an input sinewave of
various frequencies and sampled at 50 Msps.
Spurious free dynamic range (SFDR)
The ratio between the power of the worst spurious signal (not always an harmonic) and the
amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in
dBc.
Total harmonic distortion (THD)
The ratio of the rms sum of the first five harmonic distortion components to the rms value of
the fundamental line. It is expressed in dB.
Signal to noise ratio (SNR)
The ratio of the rms value of the fundamental component to the rms sum of all other spectral
components in the Nyquist band (F / 2) excluding DC, fundamental and the first five
s
harmonics. SNR is reported in dB.
Signal to noise and distortion ratio (SINAD)
A similar ratio to the SNR but including the harmonic distortion components in the noise
figure (not the DC signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the
formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but has an A amplitude, the SINAD
0
expression becomes:
SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A /FS)
0
The ENOB is expressed in bits.
24/29
RHF1401
Definitions of specified parameters
Analog input bandwidth
The maximum analog input frequency at which the spectral response of a full power signal
is reduced by 3 dB. Higher values can be achieved with smaller input levels.
Pipeline delay
Delay between the initial sample of the analog input and the availability of the corresponding
digital data output, on the output bus. Also called data latency. It is expressed as a number
of clock cycles.
25/29
Package information
RHF1401
9
Package information
Figure 26. SO-48 package mechanical drawing
Table 11. SO-48 package mechanical data
Dimensions
Ref.
Millimeters
Typ.
Inches
Typ.
Min.
Max.
Min.
Max.
A
b
2.18
0.20
0.12
15.57
9.52
2.47
0.254
0.15
2.72
0.30
0.18
15.92
9.78
0.086
0.008
0.005
0.613
0.375
0.097
0.010
0.006
0.620
0.380
0.429
0.250
0.065
0.025
0.008
0.495
0.057
0.031
0.017
0.107
0.012
0.007
0.627
0.385
c
D
15.75
9.65
E
E1
E2
E3
e
10.90
6.35
6.22
1.52
6.48
1.78
0.245
0.060
0.255
0.070
1.65
0.635
0.20
f
L
12.28
1.30
0.66
0.25
12.58
1.45
12.88
1.60
0.92
0.61
0.483
0.051
0.026
0.010
0.507
0.063
0.036
0.024
P
Q
S1
0.79
0.43
26/29
RHF1401
Ordering information
10
Ordering information
Table 12. Order codes
Part number
Temperature range
Package
Marking
RHF1401KSO1
RHF1401KSO2
RHF1401KSO-01V
RHF1401KSO1
RHF1401KSO2
F0626001VXC
-55 °C to 125 °C
SO-48
27/29
Revision history
RHF1401
11
Revision history
Table 13. Document revision history
Date
Revision
Changes
First public release.
Failure immune and latchup immune value increased to
2
120 MeV-cm /mg.
Updated package mechanical information.
29-Jun-2007
1
Removed reference to non rad-hard components from External
references, common mode: on page 16.
Updated Figure 1: RHF1401 block diagram.
Added explanation on Figure 3: Timing diagram.
Added introduction to Section 6: Typical performance characteristics.
Updated Section 7.2: Clock signal requirements and Section 7.3:
Power consumption optimization.
29-Oct-2007
2
Added Section 7.4: Low sampling rate recommendations.
Updated information on Data Ready signal in Section 7.5: Digital
inputs/outputs.
Added Figure 24: Impact of clock frequency on RHF1401
performance and Figure 25: CLK signal derivation.
28/29
RHF1401
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29/29
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