M48T18PC [STMICROELECTRONICS]
64 Kbit 8Kb x 8 TIMEKEEPER SRAM; 64 Kbit的是8K ×8 TIMEKEEPER SRAM
| 型号： | M48T18PC |
| 厂家： | 
ST |
| 描述： | 64 Kbit 8Kb x 8 TIMEKEEPER SRAM |
| 文件： | 总27页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T08
M48T08Y, M48T18
®
5V, 64 Kbit (8 Kb x8) TIMEKEEPER SRAM
FEATURES SUMMARY
■
INTEGRATED ULTRA LOW POWER SRAM,
Figure 1. 28-pin PCDIP, CAPHAT™ Package
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, AND BATTERY
■
■
BYTEWIDE™ RAM-LIKE CLOCK ACCESS
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, and SECONDS
■
■
■
TYPICAL CLOCK ACCURACY OF ±1
MINUTE A MONTH, AT 25°C
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
WRITE PROTECT VOLTAGES
28
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
(V
–
= Power-fail Deselect Voltage):
PFD
M48T08: V = 4.75 to 5.5V
CC
4.5V ≤ V
≤ 4.75V
PFD
–
M48T18/T08Y: V = 4.5 to 5.5V
CC
Figure 2. 28-pin SOIC Package
4.2V ≤ V
≤ 4.5V
PFD
■
■
■
■
SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
SELF-CONTAINED BATTERY AND
CRYSTAL IN THE CAPHAT™ DIP
PACKAGE
SNAPHAT (SH)
Battery/Crystal
PACKAGING INCLUDES A 28-LEAD SOIC
®
AND SNAPHAT TOP (to be ordered
separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
28
1
SOH28 (MH)
■
PIN AND FUNCTION COMPATIBLE WITH
DS1643 and JEDEC STANDARD 8K x8
SRAMs
April 2004
1/27
M48T08, M48T08Y, M48T18
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 28-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-fail Interrupt Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/27
M48T08, M48T08Y, M48T18
Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Power Down/Up Trip Points DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . . 21
Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . . 21
Figure 16.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline. 22
Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data . . . . . 22
Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 23
Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 23
Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 24
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
M48T08, M48T08Y, M48T18
SUMMARY DESCRIPTION
The M48T08/18/08Y TIMEKEEPER RAM is an
8K x 8 non-volatile static RAM and real time clock
which is pin and functional compatible with the
DS1643. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory and real time clock so-
lution.
The M48T08/18/08Y is a non-volatile pin and func-
tion equivalent to any JEDEC standard 8K x 8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
®
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing con-
®
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4T28-BR12SH” or “M4T32-BR12SH”
(see Table 17., page 25).
The 28-pin, 600mil DIP CAPHAT™ houses the
M48T08/18/08Y silicon with a quartz crystal and a
long- life lithium button cell in a single package.
Figure 3. Logic Diagram
Table 1. Signal Names
A0-A12
Address Inputs
V
CC
DQ0-DQ7
Data Inputs / Outputs
Power Fail Interrupt (Open Drain)
Chip Enable 1
13
8
INT
E1
E2
G
A0-A12
DQ0-DQ7
INT
Chip Enable 2
W
E1
E2
G
M48T08
M48T08Y
M48T18
Output Enable
W
WRITE Enable
V
Supply Voltage
CC
V
Ground
SS
V
SS
AI01020
4/27
M48T08, M48T08Y, M48T18
Figure 4. DIP Connections
Figure 5. SOIC Connections
INT
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
INT
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
2
26 E2
25 A8
24 A9
23 A11
3
E2
A6
A6
4
A8
A5
A5
5
A9
A4
A4
6
A11
G
A3
22
G
A3
7
M48T08
M48T18
M48T08Y
A2
21 A10
20 E1
A2
8
A10
E1
A1
A1
9
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
14
V
SS
SS
AI01182
AI01021B
Figure 6. Block Diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A12
POWER
DQ0-DQ7
8184 x 8
SRAM ARRAY
LITHIUM
CELL
E1
E2
W
VOLTAGE SENSE
AND
V
PFD
SWITCHING
CIRCUITRY
G
V
INT
V
CC
SS
AI01333
5/27
M48T08, M48T08Y, M48T18
OPERATION MODES
As Figure 6., page 5 shows, the static memory ar-
ray and the quartz-controlled clock oscillator of the
M48T08/18/08Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year - valid until
2100), 30, and 31 day months are made automat-
ically. Byte 1FF8h is the clock control register. This
byte controls user access to the clock information
and also stores the clock calibration setting.
cells. The M48T08/18/08Y includes a clock control
circuit which updates the clock bytes with current
information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T08/18/08Y also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
condition. When V is out of tolerance, the circuit
CC
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V . As V falls
CC
CC
below the Battery Back-up Switchover Voltage
(V ), the control circuitry connects the battery
SO
which maintains data and clock operation until val-
id power returns.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
Table 2. Operating Modes
V
Mode
Deselect
Deselect
WRITE
READ
E1
E2
G
X
X
X
W
X
DQ0-DQ7
High Z
Power
Standby
Standby
Active
CC
V
IH
X
V
IL
X
X
High Z
4.75 to 5.5V
or
4.5 to 5.5V
V
IL
V
IH
V
D
IL
IH
IH
IN
V
IL
V
IH
V
V
V
D
Active
IL
OUT
V
IL
V
IH
V
IH
READ
High Z
High Z
High Z
Active
(1)
Deselect
Deselect
X
X
X
X
X
X
CMOS Standby
V
SO
to V
(min)
PFD
(1)
X
X
Battery Back-up Mode
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL SO
1. See Table 11., page 20 for details.
6/27
M48T08, M48T08Y, M48T18
READ Mode
The M48T08/18/08Y is in the READ Mode when-
ever W (WRITE Enable) is high, E1 (Chip Enable
1) is low, and E2 (Chip Enable 2) is high. The de-
vice architecture allows ripple-through access of
data from eight of 65,536 locations in the static
storage array. Thus, the unique address specified
by the 13 address inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within address
available after the latter of the Chip Enable Access
times (t
or t
) or Output Enable Access
E1LQV
E2HQV
time (t
).
GLQV
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are ac-
tivated before t
an indeterminate state until t
, the data lines will be driven to
AVQV
. If the address
AVQV
inputs are changed while E1, E2 and G remain ac-
tive, output data will remain valid for Output Data
access time (t
) after the last address input
AVQV
Hold time (t
) but will go indeterminate until the
AXQX
signal is stable, providing that the E1, E2, and G
access times are also satisfied. If the E1, E2 and
G access times are not met, valid data will be
next address access.
Figure 7. READ Mode AC Waveforms
tAVAV
VALID
A0-A12
tAVQV
tAXQX
tE1LQV
tE1HQZ
E1
tE1LQX
tE2HQV
tE2LQZ
E2
tE2HQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00962
Note: WRITE Enable (W) = High.
7/27
M48T08, M48T08Y, M48T18
Table 3. READ Mode AC Characteristics
M48T08/M48T18/T08Y
–100/–10 (T08Y) –150/–15 (T08Y)
(1)
Symbol
Unit
Parameter
Min
Max
Min
Max
t
READ Cycle Time
100
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
100
100
100
50
150
150
150
75
AVQV
t
Chip Enable 1 Low to Output Valid
Chip Enable 2 High to Output Valid
Output Enable Low to Output Valid
Chip Enable 1 Low to Output Transition
Chip Enable 2 High to Output Transition
Output Enable Low to Output Transition
Chip Enable 1 High to Output Hi-Z
Chip Enable 2 Low to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
E1LQV
t
E2HQV
t
GLQV
t
10
10
5
10
10
5
E1LQX
t
E2HQX
t
GLQX
t
50
50
40
75
75
60
E1HQZ
t
E2LQZ
t
GHQZ
t
5
5
AXQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
8/27
M48T08, M48T08Y, M48T18
WRITE Mode
The M48T08/18/08Y is in the WRITE Mode when-
ever W, E1, and E2 are active. The start of a
WRITE is referenced from the latter occurring fall-
ing edge of W or E1, or the rising edge of E2. A
WRITE is terminated by the earlier rising edge of
W or E1, or the falling edge of E2. The addresses
must be held valid throughout the cycle. E1 or W
Enable prior to the initiation of another READ or
WRITE Cycle. Data-in must be valid t
the end of WRITE and remain valid for t
prior to
DVWH
af-
WHDX
terward. G should be kept high during WRITE Cy-
cles to avoid bus contention; however, if the output
bus has been activated by a low on E1 and G and
a high on E2, a low on W will disable the outputs
must return high or E2 low for a minimum of t
t
after W falls.
E1HAX
WLQZ
or t
from Chip Enable or t
from WRITE
E2LAX
WHAX
Figure 8. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
A0-A12
VALID
tAVWH
tAVE1L
tAVE2H
tWHAX
E1
E2
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DATA INPUT
tDVWH
DQ0-DQ7
AI00963
9/27
M48T08, M48T08Y, M48T18
Figure 9. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A12
VALID
tAVE1H
tE1LE1H
tAVE1L
tE1HAX
tE2LAX
E1
tAVE2L
tE2HE2L
tAVE2H
E2
tAVWL
W
tE1HDX
tE2LDX
DQ0-DQ7
DATA INPUT
tDVE1H
tDVE2L
AI00964B
10/27
M48T08, M48T08Y, M48T18
Table 4. WRITE Mode AC Characteristics
M48T08/M48T18/T08Y
–100/–10 (T08Y) –150/–15 (T08Y)
(1)
Symbol
Unit
Parameter
Min
100
0
Max
Min
150
0
Max
t
WRITE Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to WRITE Enable Low
Address Valid to Chip Enable 1 Low
Address Valid to Chip Enable 2 High
WRITE Enable Pulse Width
AVWL
t
0
0
AVE1L
t
0
0
AVE2H
t
80
80
80
10
10
10
50
50
50
5
100
130
130
10
10
10
70
70
70
5
WLWH
t
Chip Enable 1 Low to Chip Enable 1 High
Chip Enable 2 High to Chip Enable 2 Low
WRITE Enable High to Address Transition
Chip Enable 1 High to Address Transition
Chip Enable 2 Low to Address Transition
Input Valid to WRITE Enable High
Input Valid to Chip Enable 1 High
E1LE1H
t
E2HE2L
t
WHAX
t
E1HAX
t
E2LAX
t
DVWH
t
DVE1H
t
Input Valid to Chip Enable 2 Low
DVE2L
t
WRITE Enable High to Input Transition
Chip Enable 1 High to Input Transition
Chip Enable 2 Low to Input Transition
WRITE Enable Low to Output Hi-Z
Address Valid to WRITE Enable High
Address Valid to Chip Enable 1 High
Address Valid to Chip Enable 2 Low
WRITE Enable High to Output Transition
WHDX
t
5
5
E1HDX
t
5
5
E2LDX
t
50
70
WLQZ
t
80
80
80
10
130
130
130
10
AVWH
t
AVE1H
t
AVE2L
t
WHQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
11/27
M48T08, M48T08Y, M48T18
Data Retention Mode
With valid V applied, the M48T08/18/08Y oper-
Note: Requires use of M4T32-BR12SH
SNAPHAT top when using the SOH28 package.
CC
®
ates as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
As system power returns and V
rises above
CC
V
, the battery is disconnected and the power
SO
self when V
falls within the V
(max), V
PFD PFD
CC
supply is switched to external V
.
CC
(min) window. All outputs become high imped-
ance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
Write protection continues until V reaches V
CC
PFD
(min) plus t (min). E1 should be kept high or E2
rec
low as V
rises past V
(min) to prevent inad-
CC
PFD
vertent WRITE cycles prior to system stabilization.
Normal RAM operation can resume t after V
rec
CC
tent. At voltages below V
(min), the user can be
PFD
exceeds V
(max).
PFD
assured the memory will be in a write protected
For more information on Battery Storage Life refer
to the Application Note AN1012.
Power-fail Interrupt Pin
state, provided the V fall time is not less than t .
CC
F
The M48T08/18/08Y may respond to transient
noise spikes on V that reach into the deselect
CC
window during the time the device is sampling
The M48T08/18/08Y continuously monitors V
.
CC
V
. Therefore, decoupling of the power supply
When V
falls to the power-fail detect trip point,
CC
CC
lines is recommended.
an interrupt is immediately generated. An internal
clock provides a delay of between 10µs and 40µs
before automatically deselecting the M48T08/18/
08Y. The INT pin is an open drain output and re-
quires an external pull up resistor, even if the inter-
rupt output function is not being used.
When V drops below V , the control circuit
CC
SO
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T08/18/
08Y for an accumulated period of at least 10 years
when V is less than V
.
CC
SO
12/27
M48T08, M48T08Y, M48T18
CLOCK OPERATIONS
Reading the Clock
Setting the Clock
®
Updates to the TIMEKEEPER registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIME-
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, the seventh bit in the control register.
As long as a '1' remains in that position, updating
is halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
The eighth bit of the control register is the WRITE
Bit. Setting the WRITE Bit to a '1,' like the READ
Bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (on Ta-
ble 5). Resetting the WRITE Bit to a '0' then trans-
fers the values of all time registers (1FF9h-1FFFh)
to the actual TIMEKEEPER counters and allows
normal operation to resume. The FT Bit and the
bits marked as '0' in Table 5 must be written to '0'
to allow for normal TIMEKEEPER and RAM oper-
ation.
®
See the Application Note AN923, “TIMEKEEPER
Rolling Into the 21 Century” for information on
st
Century Rollover.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
Table 5. Register Map
Data
Function/Range
BCD Format
Address
D7
D6
D5
D4
10 M
0
D3
D2
D1
D0
1FFFh
1FFEh
1FFDh
1FFCh
1FFBh
1FFAh
1FF9h
1FF8h
10 Years
Year
Month
Date
Year
Month
Date
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
10 Date
0
FT
0
0
0
Day
Hours
Day
0
10 Hours
Hours
Minutes
Seconds
Control
0
10 Minutes
10 Seconds
S
Minutes
ST
W
Seconds
R
Calibration
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Set to '0' for normal clock operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
13/27
M48T08, M48T08Y, M48T18
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit (ST) is the MSB of the seconds register. Setting
it to a '1' stops the oscillator. The M48T08/18/08Y
(in the PCDIP28 package) is shipped from STMi-
croelectronics with the STOP Bit set to a '1.' When
reset to a '0,' the M48T08/18/08Y oscillator starts
within one second.
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration Byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Note: To guarantee oscillator start-up after initial
power-up, first write the STOP Bit (ST) to '1,' then
reset to '0.'
Calibrating the Clock
Two methods are available for ascertaining how
much calibration a given M48T08/18/08Y may re-
quire. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable
enclosure. All the designer has to do is provide a
simple utility that accesses the Calibration Byte.
The M48T08/18/08Y is driven by a quartz-con-
trolled oscillator with a nominal frequency of
32,768 Hz. A typical M48T08/18/08Y is accurate
within 1 minute per month at 25°C without calibra-
tion. The devices are tested not to exceed ± 35
ppm (parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T08/18/08Y improves to
better than +1/–2 ppm at 25°C.
The second approach is better suited to a manu-
facturing environment, and involves the use of
standard test equipment. When the Frequency
Test (FT) Bit, the seventh-most significant bit in
the Day Register, is set to a '1,' and the oscillator
is running at 32,768 Hz, the LSB (DQ0) of the Sec-
onds Register will toggle at 512 Hz. Any deviation
from 512 Hz indicates the degree and direction of
oscillator frequency shift at the test temperature.
For example, a reading of 512.01024 Hz would in-
dicate a +20 ppm oscillator frequency error, requir-
ing a –10 (WR001010) to be loaded into the
Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency. The device must be selected and ad-
dresses must be stable at Address 1FF9h when
reading the 512 Hz on DQ0.
The LSB of the Seconds Register is monitored by
holding the M48T08/18/08Y in an extended READ
of the Seconds Register, but without having the
READ Bit set. The FT Bit MUST be reset to '0' for
normal clock operations to resume.
The oscillation rate of any crystal changes with
temperature. Figure 10., page 15 shows the fre-
quency error that can be expected at various tem-
peratures. Most clock chips compensate for
crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T08/18/
08Y design, however, employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure
11., page 15. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration Byte
found in the Control Register. Adding counts
speeds the clock up, subtracting counts slows the
clock down.
The Calibration Byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value between 0 and 31 in binary
form. The sixth bit is the Sign Bit; '1' indicates pos-
itive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The
first 62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
For more information on calibration, see the Appli-
®
cation Note AN934, “TIMEKEEPER Calibration.”
14/27
M48T08, M48T08Y, M48T18
Figure 10. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
-60
-80
T0 = 25 °C
-100
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
Figure 11. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
15/27
M48T08, M48T08Y, M48T18
V
Noise And Negative Going Transients
Figure 12. Supply Voltage Protection
CC
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
12) is recommended in order to provide the need-
ed filtering.
V
CC
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
CC
V
SS
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
AI02169
nect a schottky diode from V
to V
(cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
16/27
M48T08, M48T08Y, M48T18
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 6. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
T
A
Ambient Operating Temperature
T
Storage Temperature (V Off, Oscillator Off)
–40 to 85
°C
STG
CC
(1,2,3)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
260
–0.3 to 7
–0.3 to 7
20
°C
V
T
SLD
V
IO
V
V
CC
I
Output Current
mA
W
O
P
D
Power Dissipation
1
Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
than 30 seconds).
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
17/27
M48T08, M48T08Y, M48T18
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 7. Operating and AC Measurement Conditions
Parameter
M48T08
M48T18/T08Y
4.5 to 5.5
0 to 70
100
Unit
V
Supply Voltage (V
)
4.75 to 5.5
0 to 70
100
CC
Ambient Operating Temperature (T )
°C
pF
ns
V
A
Load Capacitance (C )
L
Input Rise and Fall Times
≤ 5
≤ 5
Input Pulse Voltages
0 to 3
1.5
0 to 3
Input and Output Timing Ref. Voltages
1.5
V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 13. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF
L
C
includes JIG capacitance
L
AI01019
Table 8. Capacitance
Symbol
(1,2)
Min
Max
Unit
pF
Parameter
C
Input Capacitance
Input / Output Capacitance
10
10
IN
(3)
pF
C
IO
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
18/27
M48T08, M48T08Y, M48T18
Table 9. DC Characteristics
M48T08/M48T18/T08Y
Unit
(1)
Symbol
Parameter
Test Condition
Min
Max
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current
±1
µA
µA
LI
IN
CC
(2)
0V ≤ V
≤ V
CC
±1
80
3
I
OUT
LO
I
Outputs open
mA
mA
CC
(3)
E1 = V E2 = V
IL
Supply Current (Standby) TTL
I
I
IH,
CC1
E1 = V – 0.2V,
CC
(3)
Supply Current (Standby) CMOS
Input Low Voltage
3
mA
V
CC2
E2 = V + 0.2V
SS
(4)
–0.3
2.2
0.8
V
IL
V
V
CC
+ 0.3
Input High Voltage
Output Low Voltage
V
V
V
V
IH
I
I
= 2.1mA
= 0.5mA
= –1mA
0.4
0.4
OL
V
OL
(5)
OL
Output Low Voltage (INT)
V
I
Output High Voltage
2.4
OH
OH
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
2. Outputs deselected.
3. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.'
4. Negative spikes of –1V allowed for up to 10ns once per Cycle.
5. The INT pin is Open Drain.
19/27
M48T08, M48T08Y, M48T18
Figure 14. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tPD
tFB
tPFX
tRB
tPFH
INT
trec
RECOGNIZED
NOTE
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00566
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as V rises past V
(min).
PFD
CC
Some systems may perform inadvertent WRITE cycles after V rises above V
(min) but before normal system operations begin.
CC
PFD
Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
Table 10. Power Down/Up AC Characteristics
(1)
Symbol
Min
0
Max
Unit
µs
Parameter
t
PD
E1 or W at V or E2 at V before Power Down
IH
IL
(2)
V
(max) to V
(min) V Fall Time
300
µs
t
PFD
PFD
PFD
PFD
CC
F
(3)
V
V
V
(min) to V
V
Fall Time
10
0
µs
µs
µs
ms
µs
µs
t
SS CC
FB
t
(min) to V
(max) V Rise Time
PFD CC
R
t
t
to V
(min) V Rise Time
PFD CC
1
RB
SS
E1 or W at V or E2 at V before Power Up
1
rec
IH
IL
t
INT Low to Auto Deselect
V (max) to INT High
PFD
10
40
PFX
t
120
PFH
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than t may result in deselection/write protection not occurring until 200µs after V pass-
PFD F CC
PFD
es V
(min).
PFD
3. V
(min) to V fall time of less than t may cause corruption of RAM data.
SS FB
PFD
Table 11. Power Down/Up Trip Points DC Characteristics
(1,2)
Symbol
Min
4.5
4.2
Typ
4.6
4.3
3.0
Max
4.75
4.5
Unit
V
Parameter
M48T08
V
PFD
Power-fail Deselect Voltage
M48T18/T08Y
V
V
Battery Back-up Switchover Voltage
Expected Data Retention Time
V
SO
(3)
t
YEARS
DR
10
Note: 1. All voltages referenced to V
.
SS
2. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
®
3. At 55°C, V = 0V; t = 8.5 years (typ) at 70°C. Requires use of M4T32-BR12SH SNAPHAT top when using the SOH28 package.
CC
DR
20/27
M48T08, M48T08Y, M48T18
PACKAGE MECHANICAL INFORMATION
Figure 15. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Note: Drawing is not to scale.
Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
36.32
16.00
3.81
Typ
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
21/27
M48T08, M48T08Y, M48T18
Figure 16. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
22/27
M48T08, M48T08Y, M48T18
Figure 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
23/27
M48T08, M48T08Y, M48T18
Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
24/27
M48T08, M48T08Y, M48T18
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
M48T
18
–100
PC
1
E
Device Type
M48T
Supply Voltage and Write Protect Voltage
(1)
08 = V = 4.75 to 5.5V; V
= 4.5 to 4.75V
PFD
CC
18/08Y = V = 4.5 to 5.5V; V
= 4.2 to 4.5V
PFD
CC
Speed
–100 = 100ns
–150 = 150ns
–10 = 100ns (M48T08Y)
Package
(1)
PC = PCDIP28
(2)
MH = SOH28
Temperature Range
1 = 0 to 70°C
Shipping Method
For SOH28:
blank = Tubes (Not for New Design - Use E)
®
E = Lead-free Package (ECO PACK ), Tubes
®
F = Lead-free Package (ECO PACK ), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For PCDIP28:
blank = Tubes
Note: 1. The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.
®
2. The SOIC package (SOH28) requires the SNAPHAT battery/crystal package which is ordered separately under the part number
“M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see Table 17). The M48T08Y part is offered in the
SOH28 (SNAPHAT) package only.
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-
tery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 17. SNAPHAT Battery Table
Part Number
M4T28-BR12SH
M4T32-BR12SH
Description
Lithium Battery (48mAh) SNAPHAT
Lithium Battery (120mAh) SNAPHAT
Package
SH
SH
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M48T08, M48T08Y, M48T18
REVISION HISTORY
Table 18. Document Revision History
Date
Rev. #
Revision Details
December 1999
1.0
First Issue
From Preliminary Data to Data Sheet; Battery Low Flag paragraph changed; 100ns
speed class identifier changed (Tables 3, 4)
07-Feb-00
11-Jul-00
16-Jul-01
2.0
2.1
3.0
t
FB
changed (Table 10); Watchdog Timer paragraph changed
Reformatted; SNAPHAT battery table added (Table 17); added temp./voltage info. to
tables (Tables 8, 9, 3, 4, 10, 11)
01-Aug-01
21-Dec-01
06-Mar-02
20-May-02
29-Aug-02
28-Mar-03
10-Dec-03
30-Mar-04
3.1
3.2
3.3
3.4
3.5
4.0
5.0
6.0
Reference to App. Note corrected in “Calibrating the Clock” section
Changes to text in document to reflect addition of M48T08Y option
Fix Ordering Information table and add to footnote (Table 16)
Modify reflow time and temperature footnotes (Table 6)
t
specification temperature updated (Table 11)
DR
v2.2 template applied; updated test conditions (Table 10)
Reformatted
Reformatted; Lead-free (Pb-free) information package update (Table 6, 16)
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M48T08, M48T08Y, M48T18
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
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27/27
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