M48T201V-70MH1_技术文档

M48T201Y

M48T201V

®

5.0 or 3.3V TIMEKEEPER Supervisor

FEATURES SUMMARY

■

CONVERTS LOW POWER SRAM INTO

Figure 1. Package

NVRAMs

■

YEAR 2000 COMPLIANT

BATTERY LOW FLAG

INTEGRATED REAL TIME CLOCK, POWER-

FAIL CONTROL CIRCUIT, BATTERY AND

CRYSTAL

SNAPHAT (SH)

Crystal/Battery

■

WATCHDOG TIMER

CHOICE OF WRITE PROTECT VOLTAGES

(V

–

= Power-fail Deselect Voltage):

PFD

M48T201Y: V = 4.5 to 5.5V

CC

4.1V ≤ V

≤ 4.5V

PFD

–

M48T201V: V = 3.0 to 3.6V

CC

44

2.7V ≤ V

≤ 3.0V

PFD

■

MICROPROCESSOR POWER-ON RESET

(Valid even during battery back-up mode.)

PROGRAMMABLE ALARM OUTPUT

ACTIVE IN THE BATTERY BACKED-UP

MODE

1

SOH44 (MH)

44-pin SOIC

■

PACKAGING INCLUDES A 44-LEAD SOIC

AND SNAPHAT TOP (to be ordered

separately)

®

SOIC PACKAGE PROVIDES DIRECT

®

CONNECTION FOR A SNAPHAT TOP

WHICH CONTAINS THE BATTERY AND

CRYSTAL

September 2004

1/33

M48T201Y, M48T201V

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. G

Timing When Switching Between RTC and External SRAM. . . . . . . . . . . . . . . . . . 8

CON

Figure 6. READ Cycle Timing: RTC and External RAM Control Signals . . . . . . . . . . . . . . . . . . . . . 9

Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals . . . . . . . . . . . . . . . . . . . . . 11

Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. Alarm Interrupt Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10.RSTIN1 and RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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M48T201Y, M48T201V

Table 9. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

V

CC

Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 10. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 11. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14. Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 16.SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline . . . . . . . . . . . . . . 28

Table 15. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data . . . . . . 28

Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 29

Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 29

Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 30

Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 30

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 18. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 19. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3/33

M48T201Y, M48T201V

DESCRIPTION

The M48T201Y/V are self-contained devices that

include a real time clock (RTC), programmable

alarms, a watchdog timer, and a square wave out-

put which provides control of up to 512K x 8 of ex-

ternal low-power static RAM. Access to all RTC

functions and the external RAM is the same as

conventional bytewide SRAM. The 16 TIME-

mounted on top of the SOIC package after the

completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow

prevents potential battery damage due to the high

temperatures required for device surface-mount-

ing. The SNAPHAT housing is keyed to prevent

reverse insertion. The SOIC and battery packages

are shipped separately in plastic anti-static tubes

or in Tape & Reel form. For the 44-lead SOIC, the

battery/crystal package (e.g., SNAPHAT) part

number is “M4Txx-BR12SH” (see Table

19., page 31).

®

KEEPER registers offer year, month, date, day,

hour, minute, second, calibration, alarm, century,

watchdog, and square wave output data. External-

ly attached static RAMs are controlled by the

M48T201Y/V via the G

and E

signals.

CON

The 44-pin, 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

nection to a separate SNAPHAT housing con-

taining the battery and crystal. The unique design

allows the SNAPHAT battery package to be

Caution: Do not place the SNAPHAT battery/crys-

tal top in conductive foam as this will drain the lith-

ium button-cell battery.

®

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A18

DQ0-DQ7

RSTIN1

RSTIN2

RST

Address Inputs

Data Inputs / Outputs

Reset 1 Input

V

CC

Reset 2 Input

19

8

Reset Output (Open Drain)

Watchdog Input

A0-A18

DQ0-DQ7

WDI

W

IRQ/FT

RST

E

Chip Enable Input

Output Enable Input

WRITE Enable Input

RAM Chip Enable Output

RAM Enable Output

G

M48T201Y

M48T201V

W

E

G

CON

E

CON

G

E

CON

G

CON

RSTIN1

RSTIN2

SQW

Interrupt / Frequency Test Output

(Open Drain)

IRQ/FT

SQW

V

OUT

Square Wave Output

Supply Voltage Output

Supply Voltage

V

OUT

SS

AI02240

V

CC

V

SS

Ground

NC

Not Connected Internally

4/33

M48T201Y, M48T201V

Figure 3. SOIC Connections

RSTIN1

RSTIN2

RST

NC

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

V

CC

2

OUT

3

SQW

IRQ/FT

A17

A15

A13

A8

4

A18

A16

A14

A12

A7

5

6

7

8

9

A9

A6

10

11

12

13

14

15

16

17

18

19

20

21

22

A11

G

A5

M48T201Y

M48T201V

A4

W

A3

NC

A2

A10

E

A1

A0

E

CON

WDI

DQ7

DQ6

DQ5

DQ4

DQ3

NC

G

CON

DQ0

DQ1

DQ2

V

SS

AI02241

5/33

M48T201Y, M48T201V

Figure 4. Hardware Hookup

A0-A18

A0-Axx

32,768 Hz

CRYSTAL

V

CC

OUT

(1)

0.1µF

E2

LITHIUM

CELL

M48T201Y/V

5V

V

E

CC

CMOS

SRAM

0.1µF

W

ECON

E

G

W

G

WDI

GCON

RST

RSTIN1

RSTIN2

IRQ/FT

SQW

V

SS

V

SS

DQ0-DQ7

AI00604

Note: 1. If the second chip enable pin (E2) is unused, it should be tied to V

.

OUT

6/33

M48T201Y, M48T201V

OPERATION

Automatic backup and write protection for an ex-

ternal SRAM is provided through V

date, hours, minutes, and seconds of the clock

registers. Byte 7FFF1h contains century informa-

tion. Byte 7FFF0h contains additional flag informa-

tion pertaining to the watchdog timer, the alarm

condition, the battery status and square wave out-

put operation. 4 bits are included within this regis-

ter (RS0-RS3) that are used to program the

Square Wave Output Frequency (see Table

7., page 18). The M48T201Y/V also has its own

Power-Fail Detect circuit. This control circuitry

constantly monitors the supply voltage for an out

, E

, and

OUT

CON

G

pins. (Users are urged to insure that voltage

CON

specifications, for both the SUPERVISOR chip

and external SRAM chosen, are similar.) The

SNAPHAT containing the lithium energy source

®

is used to retain the RTC and RAM data in the ab-

sence of V

power through the V

pin. The

CC

OUT

chip enable output to RAM (E

enable output to RAM (G

ing power transients to prevent data corruption.

The date is automatically adjusted for months with

less than 31 days and corrects for leap years (valid

until 2100). The internal watchdog timer provides

programmable alarm windows.

) and the output

) are controlled dur-

CON

of tolerance condition. When V

is out of toler-

CC

®

ance, the circuit write protects the TIMEKEEPER

register data and external SRAM, providing data

security in the midst of unpredictable system oper-

ation. As V

falls below the Battery Back-up

CC

The nine clock bytes (7FFFFh-7FFF9h and

7FFF1h) are not the actual clock counters, they

are memory locations consisting of BiPORT™

READ/WRITE memory cells within the static RAM

array. Clock circuitry updates the clock bytes with

current information once per second. The informa-

tion can be accessed by the user in the same man-

ner as any other location in the static memory

array. Byte 7FFF8h is the clock control register.

This byte controls user access to the clock infor-

mation and also stores the clock calibration set-

ting.

Byte 7FFF7h contains the watchdog timer setting.

The watchdog timer can generate either a reset or

an interrupt, depending on the state of the Watch-

dog Steering Bit (WDS). Bytes 7FFF6h-7FFF2h

include bits that, when programmed, provide for

clock alarm functionality. Alarms are activated

when the register content matches the month,

Switchover Voltage (V ), the control circuitry au-

SO

tomatically switches to the battery, maintaining

data and clock operation until valid power is re-

stored.

Address Decoding

The M48T201Y/V accommodates 19 address

lines (A0-A18) which allow direct connection of up

to 512K bytes of static RAM. Regardless of SRAM

density used, timekeeping, watchdog, alarm, cen-

tury, flag, and control registers are located in the

upper RAM locations. All TIMEKEEPER registers

reside in the upper RAM locations without conflict

by inhibiting the G

(output enable RAM) signal

CON

during clock access. The RAM's physical locations

are transparent to the user and the memory map

looks continuous from the first clock address to the

upper most attached RAM addresses.

Table 2. Operating Modes

V

Mode

Deselect

WRITE

READ

E

G

X

W

DQ7-DQ0

Power

Standby

Active

CC

V

IH

X

High-Z

4.5V to 5.5V

or

3.0V to 3.6V

V

IL

V

IL

V

IL

V

D

IL

IH

IN

V

D

Active

IL

OUT

V

IH

READ

High-Z

Active

(1)

Deselect

X

CMOS Standby

V

SO

to V

(min)

PFD

(1)

Deselect

X

Battery Back-Up

≤ V

SO

Note: X = V or V ; V = Battery Back-up Switchover Voltage

IH

IL

SO

1. See Table 14., page 27 for details.

7/33

M48T201Y, M48T201V

READ Mode

The M48T201Y/V executes a READ Cycle when-

ever W (WRITE Enable) is high and E (Chip En-

able) is low. The unique address specified by the

address inputs (A0-A18) defines which one of the

must be measured from the latter occurring signal

(E or G) and the limiting parameter is either t

ELQV

for E or t

for G rather than the address access

GLQV

time. When one of the on-chip TIMEKEEPER reg-

®

on-chip TIMEKEEPER registers or external

isters is selected for READ, the G signal will

CON

SRAM locations is to be accessed. When the ad-

dress presented to the M48T201Y/V is in the

range of 7FFFFh-7FFF0h, one of the on-board

TIMEKEEPER registers is accessed and valid

data will be available to the eight data output driv-

remain inactive throughout the READ Cycle.

When the address value presented to the

M48T201Y/V is outside the range of TIMEKEEP-

ER registers, an external SRAM location will be

selected. In this case the G signal will be passed

ers within t

after the address input signal is

AVQV

to the G

pin, with the specified delay times of

CON

stable, providing that the E and G access times

are also satisfied. If they are not, then data access

t

or t

.

AOEL

OERL

Figure 5. G

Timing When Switching Between RTC and External SRAM

CON

7FFF0h - 7FFFFh

00000h - 7FFEFh

7FFF0h - 7FFFFh

00000h - 7FFEFh

ADDRESS

RTC

External SRAM

RTC

External SRAM

G

CON

tAOEL

tAOEH

tOERL

tRO

E

AI02333

8/33

M48T201Y, M48T201V

Figure 6. READ Cycle Timing: RTC and External RAM Control Signals

READ

tAVAV

READ

tAVAV

WRITE

tAVAV

ADDRESS

tELQV

tAVQV

tAVWL

tWHAX

E

tELQX

tGLQV

G

tRO

G

CON

E

CON

tEPD

tWLWH

W

tGLQX

tAXQX

tGHQZ

DATA OUT

VALID

DATA OUT

VALID

DATA IN

VALID

DQ0-DQ7

AI02334

9/33

M48T201Y, M48T201V

Table 3. READ Mode AC Characteristics

M48T201Y

–70

M48T201V

–85

(1)

Symbol

Unit

Parameter

Min

Max

Min

Max

t

READ Cycle Time

70

85

ns

AVAV

t

Address Valid to Output Valid

70

25

85

35

AVQV

t

Chip Enable Low to Output Valid

Output Enable Low to Output Valid

Chip Enable Low to Output Transition

ELQV

t

GLQV

(2)

5

0

5

0

t

ELQX

GLQX

EHQZ

(2)

Output Enable Low to Output Transition

Chip Enable High to Output Hi-Z

ns

t

20

25

Output Enable High to Output Hi-Z

Address Transition to Output Transition

t

GHQZ

t

5

ns

AXQX

t

External SRAM Address to G

Low

CON

20

10

15

10

30

15

20

15

AOEL

AOEH

t

SUPERVISOR SRAM Address to G

High

CON

t

E to E

Low or High

CON

EPD

t

G Low to G

Low

OERL

CON

t

G High to G

High

CON

RO

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. C = 5pF.

L

10/33

M48T201Y, M48T201V

WRITE Mode

The M48T201Y/V is in the WRITE Mode whenever

W (WRITE Enable) and E (Chip Enable) are low

state after the address inputs are stable. The start

of a WRITE is referenced from the latter occurring

falling edge of W or E. A WRITE is terminated by

the earlier rising edge of W or E. The addresses

must be held valid throughout the cycle. E or W

tention; although, if the output bus has been acti-

vated by a low on E and G a low on W will disable

the outputs t

after W falls.

WLQZ

When the address value presented to the

M48T201Y/V during the WRITE is in the range of

7FFFFh-7FFF0h, one of the on-board TIME-

®

KEEPER registers will be selected and data will

must return high for a minimum of t

from Chip

EHAX

be written into the device. When the address value

presented to M48T201Y/V is outside the range of

TIMEKEEPER registers, an external SRAM loca-

tion is selected.

Enable or t

from WRITE Enable prior to the

WHAX

initiation of another READ or WRITE Cycle. Data-

in must be valid t prior to the end of WRITE

DVWH

and remain valid for t

afterward. G should be

WHDX

kept high during WRITE Cycles to avoid bus con-

Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals

WRITE

tAVAV

WRITE

tAVAV

READ

tAVAV

ADDRESS

tAVEH

tELEH

tAVWH

tEHAX tWHAX

tAVEL

tAVQV

E

tEPD

E

CON

tEPD

tGLQV

G

tRO

tEHDX

G

CON

tAVWL

tWLWH

tWHQX

tWLQZ

W

tEHQZ

tDVEH tDVWH

tWHDX

DATA OUT

VALID

DATA IN

VALID

DATA IN

VALID

DATA OUT

VALID

DQ0-DQ7

AI02336

11/33

M48T201Y, M48T201V

Table 4. WRITE Mode AC Characteristics

M48T201Y

–70

M48T201V

–85

(1)

Symbol

Unit

Parameter

Min

Max

Min

Max

t

WRITE Cycle Time

70

0

85

0

ns

AVAV

t

Address Valid to WRITE Enable Low

Address Valid to Chip Enable Low

WRITE Enable Pulse Width

AVWL

t

0

AVEL

t

45

50

0

55

60

0

WLWH

t

Chip Enable Low to Chip Enable High

WRITE Enable High to Address Transition

Chip Enable High to Address Transition

Input Valid to WRITE Enable High

Input Valid to Chip Enable High

ELEH

t

WHAX

t

0

EHAX

t

25

0

30

0

DVWH

t

DVEH

t

WRITE Enable High to Input Transition

Chip Enable High to Input Transition

WHDX

t

0

EHDX

(2,3)

WRITE Enable Low to Output High-Z

Address Valid to WRITE Enable High

Address Valid to Chip Enable High

WRITE Enable High to Output Transition

20

25

ns

t

WLQZ

t

55

5

65

5

AVWH

t

AVEH

(2,3)

t

WHQX

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. C = 5pF

L

3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

12/33

M48T201Y, M48T201V

Data Retention Mode

With valid V applied, the M48T201Y/V can be

accessed as described above with READ or

WRITE cycles. Should the supply voltage decay,

the M48T201Y/V will automatically deselect, write

protecting itself (and any external SRAM) when

100µA of current to the attached memory with less

than 0.3V drop under this condition. On power up,

CC

when V returns to a nominal value, write protec-

CC

tion continues for 200ms (max) by inhibiting E

.

CON

The RST signal also remains active during this

time (see Figure 15., page 27).

V

falls between V

(max) and V

(min).

CC

PFD

This is accomplished by internally inhibiting ac-

cess to the clock registers via the E signal. At this

time, the Reset pin (RST) is driven active and will

Note: Most low power SRAMs on the market to-

day can be used with the M48T201Y/V TIME-

®

KEEPER SUPERVISOR. There are, however

remain active until V

returns to nominal levels.

CC

some criteria which should be used in making the

final choice of an SRAM to use.

The SRAM must be designed in a way where the

chip enable input disables all other inputs to the

SRAM. This allows inputs to the M48T201Y/V and

External RAM access is inhibited in a similar man-

ner by forcing E to a high level. This level is

CON

within 0.2V of the V

. E

will remain at this

BAT

CON

level as long as V

remains at an out-of-toler-

CC

ance condition. When V falls below the level of

CC

SRAMs to be “Don't care” once V

falls below

CC

), power input is switched from

BAT

V

(min). The SRAM should also guarantee

®

PFD

data retention down to V

= 2.0V. The chip en-

CC

clock registers are maintained from the attached

battery supply. External RAM is also powered by

able access time must be sufficient to meet the

system needs with the chip enable (and output en-

able) output propagation delays included.

the SNAPHAT battery. All outputs except G

,

CON

E

, RST, IRQ/FT and V , become high im-

OUT

CON

pedance. The V

pin is capable of supplying

OUT

13/33

M48T201Y, M48T201V

CLOCK OPERATION

®

TIMEKEEPER Registers

Setting the Clock

The M48T201Y/V offers 16 internal registers

which contain TIMEKEEPER , Alarm, Watchdog,

Bit D7 of the Control Register (7FFF8h) is the

WRITE Bit. Setting the WRITE Bit to a '1,' like the

READ Bit, halts updates to the TIMEKEEPER reg-

isters. The user can then load them with the cor-

rect day, date, and time data in 24-hour BCD

format (see Table 5., page 15).

Resetting the WRITE Bit to a '0' then transfers the

values of all time registers (7FFFFh-7FFF9h,

7FFF1h) to the actual TIMEKEEPER counters and

allows normal operation to resume. After the

WRITE Bit is reset, the next clock update will occur

approximately one second later.

®

Flag, and Control data (see Table 5., page 15).

These registers are memory locations which con-

tain external (user accessible) and internal copies

of the data (usually referred to as BiPORT™

TIMEKEEPER cells). The external copies are in-

dependent of internal functions except that they

are updated periodically by the simultaneous

transfer of the incremented internal copy. TIME-

KEEPER and Alarm Registers store data in BCD.

Control, Watchdog and Flags (Bits D0 to D3) Reg-

isters store data in Binary Format.

Note: Upon power-up following a power failure,

both the WRITE Bit and the READ Bit will be reset

to '0.'

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted before clock data is read to prevent reading

data in transition. The BiPORT TIMEKEEPER

cells in the RAM array are only data registers and

not the actual clock counters, so updating the reg-

isters can be halted without disturbing the clock it-

self.

Updating is halted when a '1' is written to the

READ Bit, D6 in the Control Register (7FFF8h). As

long as a '1' remains in that position, updating is

halted. After a halt is issued, the registers reflect

the count; that is, the day, date, and time that were

current at the moment the halt command was is-

sued.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP

Bit is located at Bit D7 within the Seconds Register

(7FFF9h). Setting it to a '1' stops the oscillator.

When reset to a '0,' the M48T201Y/V oscillator

starts within one second.

Note: It is not necessary to set the WRITE Bit

when setting or resetting the FREQUENCY TEST

Bit (FT) or the STOP Bit (ST).

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating occurs approximately 1 sec-

ond after the READ Bit is reset to a '0.'

14/33

M48T201Y, M48T201V

®

Table 5. TIMEKEEPER Register Map

Data

Function/Range

BCD Format

Address

D7

D6

D5

D4

D3

D2

D1

D0

7FFFFh

7FFFEh

7FFFDh

7FFFCh

7FFFBh

7FFFAh

7FFF9h

7FFF8h

7FFF7h

7FFF6h

7FFF5h

7FFF4h

7FFF3h

7FFF2h

7FFF1h

7FFF0h

10 Years

Year

Month

00-99

01-12

01-31

01-07

00-23

00-59

0

10 M

0

Month

10 Date

Date: Day of Month

Day

Date

0

FT

0

Day

0

10 Hours

Hours (24 Hour Format)

Minutes

Hours

0

10 Minutes

10 Seconds

S

Minutes

Seconds

Control

Watchdog

Al. Month

Al. Date

Al. Hours

Al. Minutes

Al. Seconds

Century

Flags

ST

W

Seconds

R

Calibration

WDS BMB4 BMB3 BMB2 BMB1 BMB0

RB1

RB0

AFE

SQWE ABE Al.10M

Alarm Month

Alarm Date

01-12

01-31

00-23

00-59

00-99

RPT4 RPT5

Al. 10 Date

RPT3

RPT2

RPT1

0

Al. 10 Hours

Alarm Hours

Alarm Minutes

Alarm Seconds

100 Years

Alarm 10 Minutes

Alarm 10 Seconds

1000 Years

WDF

AF

0

BL

RS3

RS2

RS1

RS0

Keys: S = Sign Bit

SQWE = Square Wave Enable Bit

BMB0-BMB4 = Watchdog Multiplier Bits

RB0-RB1 = Watchdog Resolution Bits

AFE = Alarm Flag Enable Flag

FT = Frequency Test Bit

R = READ Bit

W = WRITE Bit

ST = Stop Bit

ABE = Alarm in Battery Back-Up Mode Enable Bit

RPT1-RPT5 = Alarm Repeat Mode Bits

WDF = Watchdog Flag

0 = Must be set to '0'

WDS = Watchdog Steering Bit

AF = Alarm Flag

RS0-RS3 = SQW Frequency

BL = Battery Low Flag

15/33

M48T201Y, M48T201V

Setting the Alarm Clock

Registers 7FFF6h-7FFF2h contain the alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, day of month,

hour, minute, or second or repeat every month,

day of month, hour, minute, or second.

It can also be programmed to go off while the

M48T201Y/V is in the battery back-up to serve as

a system wake-up call.

Bits RPT5-RPT1 put the alarm in the repeat mode

of operation. Table 6 shows the possible configu-

rations. Codes not listed in the table default to the

once per second mode to quickly alert the user of

an incorrect alarm setting.

Note: User must transition address (or toggle chip

enable) to see Flag Bit change.

When the clock information matches the alarm

clock settings based on the match criteria defined

by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE

(Alarm Flag Enable) is also set, the alarm condi-

tion activates the IRQ/FT pin. To disable alarm,

write ’0’ to the Alarm-Date register and RPT1-5.

The IRQ/FT output is cleared by a READ to the

Flags Register as shown in Figure 8. A subse-

quent READ of the Flags Register is necessary to

see that the value of the Alarm Flag has been re-

set to '0.'

The IRQ/FT pin can also be activated in the bat-

tery back-up mode. The IRQ/FT will go low if an

alarm occurs and both ABE (Alarm in Battery

Back-up Mode Enable) and AFE are set. The ABE

and AFE Bits are reset during power-up, therefore

an alarm generated during power-up will only set

AF. The user can read the Flag Register at system

boot-up to determine if an alarm was generated

while the M48T201Y/V was in the deselect mode

during power-up. Figure 9., page 17 illustrates the

back-up mode alarm timing.

Figure 8. Alarm Interrupt Reset Waveforms

A0-A18

ADDRESS 7FFF0h

15ns Min

ACTIVE FLAG BIT

IRQ/FT

HIGH-Z

AI02331

Table 6. Alarm Repeat Modes

RPT5

RPT4

RPT3

RPT2

RPT1

Alarm Setting

Once per Second

Once per Minute

Once per Hour

Once per Day

1

0

1

0

1

0

1

0

1

0

Once per Month

Once per Year

16/33

M48T201Y, M48T201V

Figure 9. Back-up Mode Alarm Waveforms

tREC

V

CC

PFD

(max)

(min)

V

SO

AFE bit/ABE bit

AF bit in Flags Register

IRQ/FT

HIGH-Z

AI03520

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The user programs the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address

7FFF7h. Bits BMB4-BMB0 store a binary multiplier

and the two lower order bits RB1-RB0 select the

resolution, where 00 = 1/16 second, 01 = 1/4 sec-

ond, 10 = 1 second, and 11 = 4 seconds. The

amount of time-out is then determined to be the

multiplication of the five-bit multiplier value with the

resolution. (For example: writing 00001110 in the

Watchdog Register = 3*1 or 3 seconds).

The watchdog timer can be reset by two methods:

1. a transition (high-to-low or low-to-high) can be

applied to the Watchdog Input pin (WDI) or

2. the microprocessor can perform a WRITE of

the Watchdog Register.

The time-out period then starts over. The WDI pin

should be tied to V if not used. The watchdog

SS

will be reset on each transition (edge) seen by the

WDI pin.

In order to perform a software reset of the watch-

dog timer, the original time-out period can be writ-

ten into the Watchdog Register, effectively

restarting the count-down cycle.

Note: Accuracy of timer is within ± the selected

resolution.

Should the watchdog timer time-out, and the WDS

Bit is programmed to output an interrupt, a value of

00h needs to be written to the Watchdog Register

in order to clear the IRQ/FT pin. This will also dis-

able the watchdog function until it is again pro-

grammed correctly. A READ of the Flags Register

will reset the Watchdog Flag (Bit D7; Register

7FFF0h).

The watchdog function is automatically disabled

upon power-down and the Watchdog Register is

cleared. If the watchdog function is set to output to

the IRQ/FT pin and the frequency test function is

activated, the watchdog or alarm function prevails

and the frequency test function is denied.

If the processor does not reset the timer within the

specified period, the M48T201Y/V sets the WDF

(Watchdog Flag) and generates a watchdog inter-

rupt or a microprocessor reset. WDF is reset by

reading the Flag Register (Address 7FFF0h).

The most significant bit of the Watchdog Register

is the Watchdog Steering Bit (WDS). When set to

a '0', the watchdog will activate the IRQ/FT pin

when timed-out. When WDS is set to a '1,' the

watchdog will output a negative pulse on the RST

pin for t

. The Watchdog register and the AFE,

REC

SQWE, ABE, and FT Bits will reset to a '0' at the

end of a Watchdog time-out when the WDS Bit is

set to a '1.'

Note: The user must transition the address (or

toggle chip enable) to see the Flag Bit change.

17/33

M48T201Y, M48T201V

Square Wave Output

The M48T201Y/V offers the user a programmable

square wave function which is output on the SQW

pin. RS3-RS0 Bits located in 7FFF0h establish the

square wave output frequency. These frequencies

are listed in Table 7. Once the selection of the

SQW frequency has been completed, the SQW

pin can be turned on and off under software con-

trol with the Square Wave Enable Bit (SQWE) lo-

cated in Register 7FFF6h.

Table 7. Square Wave Output Frequency

Square Wave Bits

Square Wave

RS3

0

RS2

0

RS1

0

RS0

0

Frequency

Hi-Z

32.768

8.192

4.096

2.048

1.024

512

256

128

64

Units

-

0

1

kHz

Hz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Hz

1

0

Hz

1

0

1

Hz

1

0

1

0

32

Hz

1

0

1

16

Hz

1

0

8

Hz

1

0

1

4

Hz

1

0

2

Hz

1

Hz

18/33

M48T201Y, M48T201V

Power-on Reset

Reset Inputs (RSTIN1 & RSTIN2)

The M48T201Y/V continuously monitors V

.

The M48T201Y/V provides two independent in-

puts which can generate an output reset. The du-

ration and function of these resets is identical to a

reset generated by a power cycle. Figure 10 and

Table 8 illustrate the AC reset characteristics of

CC

When V

falls to the power fail detect trip point,

CC

the RST pulls low (open drain) and remains low on

power-up for t after V passes V (max).

REC

CC

PFD

The RST pin is an open drain output and an appro-

priate pull-up resistor to V

control rise time.

should be chosen to

this function. Pulses shorter than t and t will

not generate a reset condition. RSTIN1 and

CC

R1 R2

RSTIN2 are each internally pulled up to V

CC

through a 100KΩ resistor.

Figure 10. RSTIN1 and RSTIN2 Timing Waveforms

RSTIN1

RSTIN2

RST

tR2

Hi-Z

tR1

tR1HRZ

tR2HRZ

AI01679

Table 8. Reset AC Characteristics

Symbol

(1)

Min

50

Max

Unit

ns

Parameter

t

RSTIN1 Low to RST Low

200

100

200

R1

R2

RSTIN2 Low to RST Low

RSTIN1 High to RST Hi-Z

RSTIN2 High to RST Hi-Z

20

ms

(2)

40

t

R1HRZ

R2HRZ

40

200

ms

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. C = 5pF (see Figure 14., page 25).

L

19/33

M48T201Y, M48T201V

Calibrating the Clock

The M48T201Y/V is driven by a quartz controlled

oscillator with a nominal frequency of 32,768Hz.

The devices are factory calibrated at 25°C and

tested for accuracy. Clock accuracy will not ex-

ceed ±35 ppm (parts per million) oscillator fre-

quency error at 25°C, which equates to about

±1.53 minutes per month. When the Calibration

circuit is properly employed, accuracy improves to

better than +1/–2 ppm at 25°C.

which corresponds to a total range of +5.5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T201Y/V may re-

quire. The first involves setting the clock, letting it

run for a month and comparing it to a known accu-

rate reference and recording deviation over a fixed

period of time. Calibration values, including the

number of seconds lost or gained in a given peri-

The oscillation rate of crystals changes with tem-

perature (see Figure 11., page 21). The

M48T201Y/V design employs periodic counter

correction. The calibration circuit adds or subtracts

counts from the oscillator divider circuit at the di-

vide by 256 stage, as shown in Figure

12., page 21.

The number of times pulses which are blanked

(subtracted, negative calibration) or split (added,

positive calibration) depends upon the value load-

ed into the five Calibration bits found in the Control

Register. Adding counts speeds the clock up, sub-

tracting counts slows the clock down.

The Calibration bits occupy the five lower order

bits (D4-D0) in the Control Register 7FFF8h.

These bits can be set to represent any value be-

tween 0 and 31 in binary form. Bit D5 is a Sign Bit;

'1' indicates positive calibration, '0' indicates nega-

tive calibration (see Figure 12., page 21). Calibra-

tion occurs within a 64 minute cycle. The first 62

minutes in the cycle may, once per minute, have

one second either shortened by 128 or lengthened

by 256 oscillator cycles. If a binary '1' is loaded into

the register, only the first 2 minutes in the 64

minute cycle will be modified; if a binary 6 is load-

ed, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step in the calibration register. Assuming that

the oscillator is running at exactly 32,768Hz, each

of the 31 increments in the Calibration byte would

represent +10.7 or –5.35 seconds per month

od, can be found in the STMicroelectronics Appli-

®

cation

Note

AN934,

“TIMEKEEPER

CALIBRATION.” This allows the designer to give

the end user the ability to calibrate the clock as the

environment requires, even if the final product is

packaged in a non-user serviceable enclosure.

The designer could provide a simple utility that ac-

cesses the Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT pin. The pin will toggle at 512Hz, when the

Stop Bit (ST, D7 of 7FFF9h) is '0,' the Frequency

Test Bit (FT, D6 of 7FFFCh) is '1,' the Alarm Flag

Enable Bit (AFE, D7 of 7FFF6h) is '0,' and the

Watchdog Steering Bit (WDS, D7 of 7FFF7h) is '1'

or the Watchdog Register (7FFF7h=0) is reset.

Note: A 4-second settling time must be allowed

before reading the 512Hz output.

Any deviation from 512Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example,

a

reading of

512.010124Hz would indicate a +20 ppm oscillator

frequency error, requiring a –10 (WR001010) to be

loaded into the Calibration Byte for correction.

Note that setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency.

The IRQ/FT pin is an open drain output which re-

quires a pull-up resistor to V

for proper opera-

CC

tion. A 500-10kΩ resistor is recommended in order

to control the rise time. The FT Bit is cleared on

power-down.

20/33

M48T201Y, M48T201V

Figure 11. Crystal Accuracy Across Temperature

Frequency (ppm)

20

0

–20

–40

–60

–80

2

∆F

F

ppm

C²

= -0.038

(T - T₀) ± 10%

–100

–120

–140

–160

T₀= 25 °C

–40

–30

–20

–10

0

10

20

30

40

50

60

70

80

Temperature °C

AI00999

Figure 12. Calibration Waveform

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

AI00594B

21/33

M48T201Y, M48T201V

Battery Low Warning

The M48T201Y/V automatically performs battery

voltage monitoring upon power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) Bit, Bit D4 of Flags

Register 7FFF0h, will be asserted if the battery

voltage is found to be less than approximately

2.5V. The BL Bit will remain asserted until comple-

tion of battery replacement and subsequent bat-

tery low monitoring tests, either during the next

power-up sequence or the next scheduled 24-hour

interval.

If a battery low is generated during a power-up se-

quence, this indicates that the battery is below ap-

proximately 2.5V and may not be able to maintain

data integrity in the SRAM. Data should be consid-

ered suspect and verified as correct. A fresh bat-

tery should be installed.

subsequent periods of battery back-up mode, the

battery should be replaced. The SNAPHAT top

®

may be replaced while V

vice.

is applied to the de-

CC

Note: This will cause the clock to lose time during

the interval the battery/crystal is removed.

The M48T201Y/V only monitors the battery when

a nominal V is applied to the device. Thus appli-

CC

cations which require extensive durations in the

battery back-up mode should be powered-up peri-

odically (at least once every few months) in order

for this technique to be beneficial. Additionally, if a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

Initial Power-on Defaults

Upon application of power to the device, the fol-

lowing register bits are set to a '0' state: WDS;

BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W; R;

FT (see Table 9).

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is near end of life. However, data is not com-

promised due to the fact that a nominal V

is

CC

supplied. In order to insure data integrity during

Table 9. Default Values

WATCHDOG

Condition

W

R

FT

AFE

ABE

SQWE

(1)

Register

Initial Power-up

0

(2)

(Battery Attach for SNAPHAT)

(3)

0

1

0

1

0

1

0

RESET

(4)

Power-down

Note: 1. WDS, BMB0-BMB4, RB0, RB1.

2. State of other control bits undefined.

3. State of other control bits remains unchanged.

4. Assuming these bits set to '1' prior to power-down.

22/33

M48T201Y, M48T201V

V

Noise And Negative Going Transients

Figure 13. Supply Voltage Protection

CC

I

transients, including those produced by output

CC

switching, can produce voltage fluctuations, re-

sulting in spikes on the V bus. These transients

CC

can be reduced if capacitors are used to store en-

ergy which stabilizes the V

bus. The energy

CC

stored in the bypass capacitors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic by-

pass capacitor value of 0.1µF (as shown in Figure

13) is recommended in order to provide the need-

ed filtering.

V

CC

V

CC

0.1µF

DEVICE

In addition to transients that are caused by normal

SRAM operation, power cycling can generate neg-

ative voltage spikes on V

that drive it to values

CC

SS

below V by as much as one volt. These negative

SS

spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, STMicroelectronics recom-

AI00605

mends connecting a schottky diode from V

to

CC

V

(cathode connected to V , anode to V ).

SS

CC SS

Schottky diode 1N5817 is recommended for

through hole and MBRS120T3 is recommended

for surface mount.

23/33

M48T201Y, M48T201V

MAXIMUM RATING

Stressing the device above the rating listed in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice

reliability.

Refer

also

to

the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Table 10. Absolute Maximum Ratings

Symbol

Parameter

Ambient Operating Temperature

Value

0 to 70

Unit

°C

T

A

®

–40 to 85

–55 to 125

260

°C

SNAPHAT

SOIC

T

Storage Temperature

STG

°C

(1)

Lead Solder Temperature for 10 seconds

Input or Output Voltage

°C

T

SLD

–0.3 to V

+ 0.3

V

IO

CC

M48T201Y

M48T201V

–0.3 to 7.0

–0.3 to 4.6

V

Supply Voltage

CC

(2)

Output Current

20

1

mA

W

I

O

P

D

Power Dissipation

Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120

seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

24/33

M48T201Y, M48T201V

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 11. DC and AC Measurement Conditions

Parameter

M48T201Y

4.5 to 5.5

0 to 70

100

M48T201V

3.0 to 3.6

0 to 70

50

Unit

V

Supply Voltage

CC

Ambient Operating Temperature

°C

pF

ns

V

Load Capacitance (C )

L

Input Rise and Fall Times

≤ 5

Input Pulse Voltages

0 to 3

1.5

0 to 3

1.5

Input and Output Timing Ref. Voltages

V

Note: Output High Z is defined as the point where data is no longer driven.

Figure 14. AC Testing Load Circuit

645Ω

DEVICE

UNDER

TEST

C

= 100pF

1.75V

L

C

includes JIG capacitance

L

AI04764

Notes:Excluding open-drain output pin; 50pF for M48T201V.

Table 12. Capacitance

(1,2)

Symbol

Min

Max

10

Unit

Parameter

Input Capacitance

C

pF

IN

(3)

Input/Output Capacitance

10

C

OUT

Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.

2. At 25°C; f = 1MHz.

3. Outputs deselected.

25/33

M48T201Y, M48T201V

Table 13. DC Characteristics

M48T201Y

–70

M48T201V

–85

(1)

Sym

Parameter

Unit

Test Condition

Min

Typ

Max

Min

Typ

Max

(2)

0V ≤ V ≤ V

Input Leakage Current

Output Leakage Current

Supply Current

±1

µA

I

IN

CC

LI

(3)

0V ≤ V

≤ V

CC

±1

15

±1

10

I

OUT

LO

I

Outputs open

8

4

mA

CC

Supply Current (Standby)

TTL

I

E = V

5

3

mA

CC1

CC2

IH

Supply Current (Standby)

CMOS

E = V –0.2

3

2

mA

nA

V

CC

Battery Current OSC ON

575

800

100

0.8

575

800

100

0.8

I

V

CC

= 0V

BAT

Battery Current OSC

OFF

V

Input Low Voltage

Input High Voltage

–0.3

2.2

–0.3

2.0

IL

V

+

V

+

CC

0.3

CC

0.3

V

IH

I

= 2.1mA

= 10mA

Output Low Voltage

0.4

V

OL

V

OL

I

V

OL

(4)

(open drain)

I

= –1.0mA

= –1.0µA

Output High Voltage

2.4

2.0

2.4

2.0

V

OH

(5)

V

Battery Back-up

Current (Active)

I

OUT2

3.6

70

V

OH

OHB

(6)

V

> V –0.3

CC

100

mA

I

OUT

OUT1

Current (Battery

OUT

I

V

> V

–0.3

100

4.5

100

3.0

µA

V

OUT2

BAT

Back-up)

Power-fail Deselect

Voltage

V

4.1

4.35

2.7

2.9

PFD

V

–

Battery Back-up

Switchover Voltage

PFD

V

3.0

V

SO

100mV

V

BAT

Battery Voltage

3.0

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. RSTIN1 and RSTIN2 internally pulled-up to V through 100KΩ resistor. WDI internally pulled-down to V through 100KΩ resistor.

CC

SS

3. Outputs deselected.

4. For IRQ/FT & RST pins (Open Drain).

5. Conditioned outputs (E

will reduce battery life.

- G

) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents

CON

6. External SRAM must match TIMEKEEPER SUPERVISOR chip V specification.

CC

26/33

M48T201Y, M48T201V

Figure 15. Power Down/Up Mode AC Waveforms

V

CC

V

(max)

(min)

PFD

SO

tF

tR

tFB

tRB

tREC

INPUTS

VALID

DON'T CARE

VALID

HIGH-Z

OUTPUTS

VALID

RST

AI03519

Table 14. Power Down/Up Mode AC Characteristics

(1)

Symbol

Min

Max

Unit

Parameter

(2)

V

(max) to V

(min) to V

(min) V Fall Time

300

µs

t

PFD

CC

F

M48T201Y

M48T201V

10

150

10

40

5

µs

ms

µs

(3)

V

Fall Time

t

PFD

SS CC

FB

t

V

(min) to V

(max) V Rise Time

PFD CC

R

PFD

t

(max) to RST High

(min) V Rise Time

200

REC

PFD

t

to V

RB

SS

PFD

CC

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. V

(max) to V

(min) fall time of less than t may result in deselection/write protection not occurring until 200µs after V pass-

PFD F CC

PFD

es V

(min).

PFD

3. V

(min) to V fall time of less than t may cause corruption of RAM data.

SS FB

PFD

27/33

M48T201Y, M48T201V

PACKAGE MECHANICAL INFORMATION

Figure 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline

A2

A

C

eB

B

e

CP

D

N

E

H

A1

α

L

1

SOH-A

Note: Drawing is not to scale.

Table 15. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data

mm

Min

inches

Min

Symb

Typ

Max

3.05

0.36

2.69

0.46

0.32

18.49

8.89

–

Typ

Max

0.120

0.014

0.106

0.018

0.012

0.728

0.350

–

A

A1

A2

B

0.05

2.34

0.36

0.15

17.71

8.23

–

0.002

0.092

0.014

0.006

0.697

0.324

–

C

D

E

e

0.81

0.032

eB

H

3.20

11.51

0.41

0°

3.61

12.70

1.27

8°

0.126

0.453

0.016

0°

0.142

0.500

0.050

8°

L

α

N

44

CP

0.10

0.004

28/33

M48T201Y, M48T201V

Figure 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline

A2

A1

A

A3

L

eA

D

B

eB

E

SHTK-A

Note: Drawing is not to scale.

Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data

mm

Min

inches

Min

Symb

Typ

Max

9.78

7.24

6.99

0.38

0.56

21.84

14.99

15.95

3.61

2.29

Typ

Max

A

A1

A2

A3

B

0.385

0.285

0.275

0.015

0.022

0.860

0.590

0.628

0.142

0.090

6.73

6.48

0.265

0.255

0.46

21.21

14.22

15.55

3.20

0.018

0.835

0.560

0.612

0.126

0.080

D

E

eA

eB

L

2.03

29/33

M48T201Y, M48T201V

Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

A2

A1

A

A3

L

eA

D

B

eB

E

SHTK-A

Note: Drawing is not to scale.

Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data

mm

Min

inches

Min

Symb

Typ

Max

10.54

8.51

Typ

Max

A

A1

A2

A3

B

0.415

.0335

0.315

0.015

0.022

0.860

.0710

0.628

0.142

0.090

8.00

7.24

0.315

0.285

8.00

0.38

0.46

21.21

17.27

15.55

3.20

0.56

0.018

0.835

0.680

0.612

0.126

0.080

D

21.84

18.03

15.95

3.61

E

eA

eB

L

2.03

2.29

30/33

M48T201Y, M48T201V

PART NUMBERING

Table 18. Ordering Information Example

Example:

M48T

201Y

–70

MH

1

TR

Device Type

M48T

Supply and Write Protect Voltage

201Y = V = 4.5 to 5.5V; V

= 4.1V to 4.5V

= 2.7V to 3.0V

CC

PFD

201V = V = 3.0 to 3.6V; V

CC

PFD

Speed

–70 = 70ns (for M48T201Y)

–85 = 85ns (for M48T201V)

Package

(1)

MH = SOH44

Temperature Range

1 = 0 to 70°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

®

Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT ) which is ordered separately under the part number

“M4Txx-BR12SH” in plastic tube or “M4Txx-BR12SHTR” in Tape & Reel form.

Note: 1. Caution: Do not place the SNAPHAT battery package “M4Txx-BR12SH” in conductive foam as it will drain the lithium button-cell

battery.

For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

®

Table 19. SNAPHAT Battery Table

Part Number

M4T28-BR12SH

M4T32-BR12SH

Description

Lithium Battery (48mAh) SNAPHAT

Lithium Battery (120mAh) SNAPHAT

Package

SH

31/33

M48T201Y, M48T201V

REVISION HISTORY

Table 20. Document Revision History

Date

Rev. #

1.0

Revision Details

November 1999

10-May-01

14-May-01

30-May-01

First Issue

2.0

Reformatted; added Industrial temperature (Table 10, 13, 3, 4, 14)

Corrected table footnote (Table 14)

2.1

2.2

Change “Controller” references to “SUPERVISOR”

Formatting changes from recent document review findings; E2 added to Hookup (Figure

4)

01-Aug-01

2.3

08-Aug-01

18-Dec-01

13-May-02

16-Jul-02

2.4

2.5

2.6

2.7

3.0

Improve text in “Setting the Alarm Clock” section

Added I

values for Industrial Temperature device (Table 13)

BAT

Modify reflow time and temperature footnote (Table 10)

Update DC Characteristics, footnotes (Table 13)

v2.2 template applied; update test condition (Table 13)

27-Mar-03

Reformatted, remove Industrial Temperature (Ambient Operating) references (Table 3, 4,

8, 10, 13, 14, 18)

24-Sep-04

4.0

M48T201, M48T201Y, M48T201V, 48T201, 48T201Y, 48T201V, T201, T201Y, T201V, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPER-

VISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIME-

KEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER,

TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,

NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,

NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, RTC, RTC, RTC, RTC, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Micro-

processor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microproces-

sor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,

Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,

Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,

Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,

Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Watchdog, Watch-

dog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,

Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,

Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI,

PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO,

PFO, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,

Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,

Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,

Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover,

Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Com-

parator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,

Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,

SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,

SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC,

SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,

5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V

32/33

M48T201Y, M48T201V

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

33/33


型号：	M48T201V-70MH1
厂家：	ST
描述：	3.3V-5V TIMEKEEPER CONTROLLER 3.3V - 5V TIMEKEEPER控制器控制器
文件：	总33页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M48T201V-70MH1 [STMICROELECTRONICS]

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