M48T201V-70MH1F [STMICROELECTRONICS]
5.0 or 3.3 V TIMEKEEPER? supervisor; 5.0或3.3 V TIMEKEEPER ？监
| 型号： | M48T201V-70MH1F |
| 厂家： | 
ST |
| 描述： | 5.0 or 3.3 V TIMEKEEPER? supervisor |
| 文件： | 总37页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T201Y
M48T201V
5.0 or 3.3 V TIMEKEEPER® supervisor
Features
■ Converts low power SRAM into NVRAMs
■ Year 2000 compliant
®
SNAPHAT (SH)
crystal/battery
■ Battery low flag
■ Integrated real time clock, power-fail control
circuit, battery and crystal
■ Watchdog timer
■ Choice of write protect voltages
(V
= power-fail deselect voltage):
PFD
– M48T201Y: V = 4.5 to 5.5 V
CC
4.1V ≤ V
≤ 4.5 V
PFD
– M48T201V: V = 3.0 to 3.6 V
CC
2.7 V ≤ V
≤ 3.0 V
PFD
■ Microprocessor power-on reset (valid even
44
during battery backup mode)
1
■ Programmable alarm output active in the
battery backed-up mode
■ Packaging includes a 44-lead SOIC and
®
SOH44 (MH)
44-pin SOIC
SNAPHAT top (to be ordered separately)
■ SOIC package provides direct connection for a
®
SNAPHAT top which contains the battery and
crystal
■ RoHS compliant
– Lead-free second level interconnect
March 2009
Rev 7
1/37
www.st.com
1
Contents
M48T201Y, M48T201V
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
Address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
TIMEKEEPER® registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.12 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 26
4
5
6
7
8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2/37
M48T201Y, M48T201V
Contents
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
List of tables
M48T201Y, M48T201V
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
®
TIMEKEEPER register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Square wave output frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power down/up mode AC characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
®
SOH44 – 44-lead plastic small outline, SNAPHAT , pack. mech. data . . . . . . . . . . . . . . . 31
®
SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. mech. data . . . . . . . 32
®
SH – 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. mech. data . . . . . . 33
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
®
SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4/37
M48T201Y, M48T201V
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
G
timing when switching between RTC and external SRAM . . . . . . . . . . . . . . . . . . . . 11
CON
Read cycle timing: RTC and external RAM control signals . . . . . . . . . . . . . . . . . . . . . . . . 12
Write cycle timing: RTC and external RAM control signals. . . . . . . . . . . . . . . . . . . . . . . . . 14
Alarm interrupt reset waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Backup mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RSTIN1 and RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
®
Figure 15. SOH44 – 44-lead plastic small outline, SNAPHAT , package outline . . . . . . . . . . . . . . . . 31
®
Figure 16. SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, package outline. . . . . . . . . 32
®
Figure 17. SH – 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. outline . . . . . . . . . . 33
Figure 18. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5/37
Description
M48T201Y, M48T201V
1
Description
The M48T201Y/V are self-contained devices that include a real time clock (RTC),
programmable alarms, a watchdog timer, and a square wave output which provides control
of up to 512 K x 8 of external low-power static RAM. Access to all RTC functions and the
®
external RAM is the same as conventional bytewide SRAM. The 16 TIMEKEEPER
registers offer year, month, date, day, hour, minute, second, calibration, alarm, century,
watchdog, and square wave output data. Externally attached static RAMs are controlled by
the M48T201Y/V via the G
and E
signals.
CON
CON
The 44-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
®
connection to a separate SNAPHAT housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the
high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic
anti-static tubes or in tape & reel form. For the 44-lead SOIC, the battery/crystal package
(e.g., SNAPHAT) part number is “M4Txx-BR12SH” (see Table 19 on page 34).
Caution:
Do not place the SNAPHAT battery/crystal top in conductive foam as this will drain the
lithium button-cell battery.
Figure 1.
Logic diagram
V
CC
19
8
A0-A18
DQ0-DQ7
WDI
W
IRQ/FT
RST
M48T201Y
M48T201V
E
G
CON
G
E
CON
RSTIN1
RSTIN2
SQW
V
OUT
V
SS
AI02240
6/37
M48T201Y, M48T201V
Table 1.
Description
Signal names
A0-A18
Address inputs
DQ0-DQ7
RSTIN1
RSTIN2
RST
Data inputs / outputs
Reset 1 input
Reset 2 Input
Reset output (open drain)
Watchdog input
WDI
E
Chip enable input
G
Output enable Input
WRITE enable input
RAM chip enable output
RAM enable output
Interrupt / frequency test output (open drain)
Square wave output
Supply voltage output
Supply voltage
W
ECON
GCON
IRQ/FT
SQW
VOUT
VCC
VSS
Ground
NC
Not connected internally
7/37
Description
M48T201Y, M48T201V
Figure 2.
SOIC connections
RSTIN1
RSTIN2
RST
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
V
CC
2
OUT
3
SQW
IRQ/FT
A17
A15
A13
A8
4
A18
A16
A14
A12
A7
5
6
7
8
9
A9
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
A11
G
A5
M48T201Y
M48T201V
A4
W
A3
NC
A2
A10
E
A1
A0
E
CON
WDI
DQ7
DQ6
DQ5
DQ4
DQ3
NC
G
CON
DQ0
DQ1
DQ2
V
SS
AI02241
8/37
M48T201Y, M48T201V
Figure 3. Hardware hookup
Description
A0-A18
A0-Axx
32,768 Hz
CRYSTAL
V
V
CC
OUT
(1)
0.1μF
E2
LITHIUM
CELL
M48T201Y/V
5V
V
E
CC
CMOS
SRAM
0.1μF
W
ECON
E
G
W
G
WDI
GCON
RST
RSTIN1
RSTIN2
IRQ/FT
SQW
V
SS
V
SS
DQ0-DQ7
DQ0-DQ7
AI00604
1. If the second chip enable pin (E2) is unused, it should be tied to VOUT
.
9/37
Operation
M48T201Y, M48T201V
2
Operation
Automatic backup and write protection for an external SRAM is provided through V
,
OUT
E
, and G
pins. (Users are urged to insure that voltage specifications, for both the
CON
CON
®
supervisor chip and external SRAM chosen, are similar.) The SNAPHAT containing the
lithium energy source is used to retain the RTC and RAM data in the absence of V power
CC
through the V
pin. The chip enable output to RAM (E
) and the output enable output
OUT
CON
to RAM (G
) are controlled during power transients to prevent data corruption. The date
CON
is automatically adjusted for months with less than 31 days and corrects for leap years (valid
until 2100). The internal watchdog timer provides programmable alarm windows.
The nine clock bytes (7FFFFh-7FFF9h and 7FFF1h) are not the actual clock counters, they
are memory locations consisting of BiPORT™ READ/WRITE memory cells within the static
RAM array. Clock circuitry updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array. Byte 7FFF8h is the clock control register. This byte controls user
access to the clock information and also stores the clock calibration setting.
Byte 7FFF7h contains the watchdog timer setting. The watchdog timer can generate either a
reset or an interrupt, depending on the state of the watchdog steering bit (WDS). Bytes
7FFF6h-7FFF2h include bits that, when programmed, provide for clock alarm functionality.
Alarms are activated when the register content matches the month, date, hours, minutes,
and seconds of the clock registers. Byte 7FFF1h contains century information. Byte 7FFF0h
contains additional flag information pertaining to the watchdog timer, the alarm condition,
the battery status and square wave output operation. 4 bits are included within this register
(RS0-RS3) that are used to program the square wave output frequency (see Table 7 on
page 21). The M48T201Y/V also has its own power-fail detect circuit. This control circuitry
constantly monitors the supply voltage for an out of tolerance condition. When V is out of
CC
®
tolerance, the circuit write protects the TIMEKEEPER register data and external SRAM,
providing data security in the midst of unpredictable system operation. As V falls below
CC
the battery backup switchover voltage (V ), the control circuitry automatically switches to
SO
the battery, maintaining data and clock operation until valid power is restored.
2.1
Address decoding
The M48T201Y/V accommodates 19 address lines (A0-A18) which allow direct connection
of up to 512 K bytes of static RAM. Regardless of SRAM density used, timekeeping,
watchdog, alarm, century, flag, and control registers are located in the upper RAM locations.
All TIMEKEEPER registers reside in the upper RAM locations without conflict by inhibiting
the G
(output enable RAM) signal during clock access. The RAM's physical locations
CON
are transparent to the user and the memory map looks continuous from the first clock
address to the upper most attached RAM addresses.
10/37
M48T201Y, M48T201V
Operation
Power
Table 2.
Mode
Operating modes
VCC
DQ7-
DQ0
E
G
W
Deselect
WRITE
READ
VIH
VIL
VIL
VIL
X
X
X
X
VIL
VIH
VIH
X
High-Z
DIN
Standby
Active
4.5 V to 5.5 V
or
VIL
VIH
X
DOUT
Active
3.0 V to 3.6 V
READ
High-Z
High-Z
High-Z
Active
Deselect
Deselect
VSO to VPFD (min)(1)
CMOS standby
Battery backup
(1)
≤ VSO
X
X
X
1. See Table 14 on page 30 for details.
Note:
X = V or V ; V = battery backup switchover voltage
IH IL SO
2.2
Read mode
The M48T201Y/V executes a READ cycle whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the address inputs (A0-A18) defines which
®
one of the on-chip TIMEKEEPER registers or external SRAM locations is to be accessed.
When the address presented to the M48T201Y/V is in the range of 7FFFFh-7FFF0h, one of
the on-board TIMEKEEPER registers is accessed and valid data will be available to the
eight data output drivers within t
after the address input signal is stable, providing that
AVQV
the E and G access times are also satisfied. If they are not, then data access must be
measured from the latter occurring signal (E or G) and the limiting parameter is either t
ELQV
for E or t
for G rather than the address access time. When one of the on-chip
GLQV
TIMEKEEPER registers is selected for READ, the G
throughout the READ cycle.
signal will remain inactive
CON
When the address value presented to the M48T201Y/V is outside the range of
TIMEKEEPER registers, an external SRAM location will be selected. In this case the G
signal will be passed to the G
pin, with the specified delay times of t
or t
.
CON
AOEL
OERL
Figure 4.
G
timing when switching between RTC and external SRAM
CON
7FFF0h - 7FFFFh
00000h - 7FFEFh
7FFF0h - 7FFFFh
00000h - 7FFEFh
ADDRESS
G
RTC
External SRAM
RTC
External SRAM
G
CON
tAOEL
tAOEH
tOERL
tRO
E
AI02333
11/37
Operation
Figure 5.
M48T201Y, M48T201V
Read cycle timing: RTC and external RAM control signals
READ
tAVAV
READ
tAVAV
WRITE
tAVAV
ADDRESS
tELQV
tAVQV
tAVWL
tWHAX
E
tELQX
tGLQV
G
tRO
G
CON
E
CON
tEPD
tWLWH
W
tGLQX
tAXQX
tGHQZ
DATA OUT
VALID
DATA OUT
VALID
DATA IN
VALID
DQ0-DQ7
AI02334
12/37
M48T201Y, M48T201V
Table 3.
Operation
Unit
Read mode AC characteristics
Parameter(1)
M48T201Y
–70
M48T201V
–85
Symbol
Min
Max
Min
Max
tAVAV
tAVQV
tELQV
READ cycle time
70
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to output valid
Chip enable low to output valid
70
70
25
85
85
35
tGLQV Output enable low to output valid
(2)
tELQX
tGLQX
tEHQZ
tGHQZ
Chip enable low to output transition
Output enable low to output transition
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
5
0
5
0
(2)
(2)
(2)
20
20
25
25
tAXQX Address transition to output transition
tAOEL External SRAM address to GCON low
tAOEH Supervisor SRAM address to GCON high
5
5
20
20
10
15
10
30
30
15
20
15
tEPD
tOERL
tRO
E to ECON low or high
G low to GCON low
G high to GCON high
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF.
2.3
Write mode
The M48T201Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)
are low state after the address inputs are stable. The start of a WRITE is referenced from
the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge
of W or E. The addresses must be held valid throughout the cycle. E or W must return high
for a minimum of t
from chip enable or t
from WRITE enable prior to the initiation
EHAX
WHAX
of another READ or WRITE cycle. Data-in must be valid t
prior to the end of WRITE
DVWH
and remain valid for t
afterward. G should be kept high during WRITE cycles to avoid
WHDX
bus contention; although, if the output bus has been activated by a low on E and G a low on
W will disable the outputs t after W falls.
WLQZ
When the address value presented to the M48T201Y/V during the WRITE is in the range of
®
7FFFFh-7FFF0h, one of the on-board TIMEKEEPER registers will be selected and data
will be written into the device. When the address value presented to M48T201Y/V is outside
the range of TIMEKEEPER registers, an external SRAM location is selected.
13/37
Operation
Figure 6.
M48T201Y, M48T201V
Write cycle timing: RTC and external RAM control signals
WRITE
tAVAV
WRITE
tAVAV
READ
tAVAV
ADDRESS
tAVEH
tELEH
tAVWH
tEHAX tWHAX
tAVEL
tAVQV
E
tEPD
E
CON
tEPD
tGLQV
G
tRO
tEHDX
G
CON
tAVWL
tWLWH
tWHQX
tWLQZ
W
tEHQZ
tDVEH tDVWH
tWHDX
DATA OUT
VALID
DATA IN
VALID
DATA IN
VALID
DATA OUT
VALID
DQ0-DQ7
AI02336
14/37
M48T201Y, M48T201V
Table 4.
Operation
Unit
Write mode AC characteristics
Parameter(1)
M48T201Y
–70
M48T201V
–85
Symbol
Min
Max
Min
Max
tAVAV
tAVWL
tAVEL
WRITE cycle time
70
0
85
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
0
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
45
50
0
55
60
0
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
0
0
25
25
0
30
30
0
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output High-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
0
0
(2)(3)
tWLQZ
20
25
tAVWH
55
55
5
65
65
5
tAVEH
(2)(3)
tWHQX
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.4
Data retention mode
With valid V applied, the M48T201Y/V can be accessed as described above with READ
CC
or WRITE cycles. Should the supply voltage decay, the M48T201Y/V will automatically
deselect, write protecting itself (and any external SRAM) when V falls between V
CC
PFD
(max) and V
(min). This is accomplished by internally inhibiting access to the clock
PFD
registers via the E signal. At this time, the reset pin (RST) is driven active and will remain
active until V returns to nominal levels. External RAM access is inhibited in a similar
CC
manner by forcing E
to a high level. This level is within 0.2 V of the V . E
will
CON
BAT CON
remain at this level as long as V remains at an out-of-tolerance condition. When V falls
CC
CC
below the level of the battery (V ), power input is switched from the V pin to the
BAT
CC
®
SNAPHAT battery and the clock registers are maintained from the attached battery supply.
External RAM is also powered by the SNAPHAT battery. All outputs except G , E
,
CON
CON
RST, IRQ/FT and V
, become high impedance. The V
pin is capable of supplying
OUT
OUT
100 µA of current to the attached memory with less than 0.3 V drop under this condition. On
power up, when V returns to a nominal value, write protection continues for 200 ms (max)
CC
by inhibiting E
. The RST signal also remains active during this time (see Figure 14 on
CON
page 30).
15/37
Operation
M48T201Y, M48T201V
Note:
Most low power SRAMs on the market today can be used with the M48T201Y/V
TIMEKEEPER SUPERVISOR. There are, however some criteria which should be used in
®
making the final choice of an SRAM to use.
The SRAM must be designed in a way where the chip enable input disables all other inputs
to the SRAM. This allows inputs to the M48T201Y/V and SRAMs to be “Don't care” once
V
V
falls below V
(min). The SRAM should also guarantee data retention down to
CC
PFD
= 2.0 V. The chip enable access time must be sufficient to meet the system needs with
CC
the chip enable (and output enable) output propagation delays included.
16/37
M48T201Y, M48T201V
Clock operation
3
Clock operation
3.1
TIMEKEEPER® registers
®
The M48T201Y/V offers 16 internal registers which contain TIMEKEEPER , alarm,
watchdog, flag, and control data (see Table 5 on page 18). These registers are memory
locations which contain external (user accessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The external copies are independent of
internal functions except that they are updated periodically by the simultaneous transfer of
the incremented internal copy. TIMEKEEPER and alarm registers store data in BCD.
control, watchdog and flags (bits D0 to D3) registers store data in binary format.
3.2
Reading the clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent
reading data in transition. The BiPORT TIMEKEEPER cells in the RAM array are only data
registers and not the actual clock counters, so updating the registers can be halted without
disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (7FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating occurs approximately 1 second after the READ bit is reset to a
'0.'
3.3
Setting the clock
Bit D7 of the control register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 18).
Resetting the WRITE bit to a '0' then transfers the values of all time registers (7FFFFh-
7FFF9h, 7FFF1h) to the actual TIMEKEEPER counters and allows normal operation to
resume. After the WRITE bit is reset, the next clock update will occur approximately one
second later.
Note:
Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset
to '0.'
3.4
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within the seconds register (7FFF9h). Setting it to
a '1' stops the oscillator. When reset to a '0,' the M48T201Y/V oscillator starts within one
second.
17/37
Clock operation
M48T201Y, M48T201V
Note:
It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
®
Table 5.
TIMEKEEPER register map
Data
Function/range
Address
BCD format
D7
D6
D5
D4
D3
D2
D1
D0
7FFFFh
7FFFEh
7FFFDh
7FFFCh
7FFFBh
7FFFAh
7FFF9h
7FFF8h
7FFF7h
7FFF6h
7FFF5h
7FFF4h
7FFF3h
7FFF2h
7FFF1h
7FFF0h
10 years
Year
Month
Year
Month
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
10 M
0
10 date
Date: Day of month
Day
Date
0
FT
0
0
0
Day
0
10 hours
Hours (24-hour format)
Minutes
Hours
0
10 minutes
10 seconds
S
Minutes
Seconds
Control
Watchdog
Al. month
Al. date
Al. hours
Al. minutes
Al. seconds
Century
Flags
ST
W
Seconds
R
Calibration
WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1
RB0
AFE
SQWE ABE Al.10M
Alarm month
Alarm date
01-12
01-31
00-23
00-59
00-59
00-99
RPT4 RPT5
Al. 10 date
RPT3
RPT2
RPT1
0
Al. 10 hours
Alarm hours
Alarm minutes
Alarm seconds
100 years
Alarm 10 minutes
Alarm 10 seconds
1000 years
WDF
AF
0
BL
RS3
RS2
RS1
RS0
Keys:
S = Sign bit
FT = Frequency test bit
R = READ bit
W = WRITE bit
ST = Stop bit
0 = Must be set to '0'
WDS = Watchdog steering bit
AF = Alarm flag
BL = Battery low flag
SQWE = Square wave enable bit
BMB0-BMB4 = Watchdog multiplier bits
RB0-RB1 = Watchdog resolution bits
AFE = Alarm flag enable flag
ABE = Alarm in battery backup mode enable bit
RPT1-RPT5 = Alarm repeat mode bits
WDF = Watchdog flag
RS0-RS3 = SQW frequency
18/37
M48T201Y, M48T201V
Clock operation
3.5
Setting the alarm clock
Registers 7FFF6h-7FFF2h contain the alarm settings. The alarm can be configured to go off
at a prescribed time on a specific month, day of month, hour, minute, or second or repeat
every month, day of month, hour, minute, or second.
It can also be programmed to go off while the M48T201Y/V is in the battery backup to serve
as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 6 shows the possible
configurations. Codes not listed in the table default to the once per second mode to quickly
alert the user of an incorrect alarm setting.
Note:
User must transition address (or toggle chip enable) to see flag bit change.
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the
alarm condition activates the IRQ/FT pin. To disable alarm, write ’0’ to the alarm-date
register and RPT1-5. The IRQ/FT output is cleared by a READ to the flags register as
shown in Figure 7. A subsequent READ of the flags register is necessary to see that the
value of the alarm flag has been reset to '0.'
The IRQ/FT pin can also be activated in the battery backup mode. The IRQ/FT will go low if
an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. The
ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up
will only set AF. The user can read the flag register at system boot-up to determine if an
alarm was generated while the M48T201Y/V was in the deselect mode during power-up.
Figure 8 on page 20 illustrates the backup mode alarm timing.
Figure 7.
Alarm interrupt reset waveforms
A0-A18
ADDRESS 7FFF0h
15ns Min
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI02331
Table 6.
RPT5
Alarm repeat modes
RPT4
RPT3
RPT2
RPT1
Alarm setting
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Once per second
Once per minute
Once per hour
Once per day
Once per month
Once per year
19/37
Clock operation
Figure 8. Backup mode alarm waveforms
M48T201Y, M48T201V
tREC
V
V
V
CC
PFD
PFD
(max)
(min)
V
SO
AFE bit/ABE bit
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI03520
3.6
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of timeout into the Watchdog
Register, address 7FFF7h. Bits BMB4-BMB0 store a binary multiplier and the two lower
order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1
second, and 11 = 4 seconds. The amount of timeout is then determined to be the
multiplication of the five-bit multiplier value with the resolution. (For example: writing
00001110 in the watchdog register = 3*1 or 3 seconds).
Note:
Accuracy of timer is within the selected resolution.
If the processor does not reset the timer within the specified period, the M48T201Y/V sets
the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.
WDF is reset by reading the flag register (address 7FFF0h).
The most significant bit of the watchdog register is the watchdog steering bit (WDS). When
set to a '0', the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a
'1,' the watchdog will output a negative pulse on the RST pin for t
. The watchdog register
REC
and the AFE, SQWE, ABE, and FT bits will reset to a '0' at the end of a watchdog timeout
when the WDS bit is set to a '1.'
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI)
or
2. the microprocessor can perform a WRITE of the watchdog register.
The timeout period then starts over. The WDI pin should be tied to V if not used. The
SS
watchdog will be reset on each transition (edge) seen by the WDI pin.
20/37
M48T201Y, M48T201V
Clock operation
In order to perform a software reset of the watchdog timer, the original timeout period can be
written into the watchdog register, effectively restarting the countdown cycle.
Should the watchdog timer time out, and the WDS bit is programmed to output an interrupt,
a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT pin.
This will also disable the watchdog function until it is again programmed correctly. A READ
of the flags register will reset the watchdog flag (bit D7; register 7FFF0h).
The watchdog function is automatically disabled upon power-down and the watchdog
register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied.
Note:
The user must transition the address (or toggle chip enable) to see the flag bit change.
3.7
Square wave output
The M48T201Y/V offers the user a programmable square wave function which is output on
the SQW pin. RS3-RS0 bits located in 7FFF0h establish the square wave output frequency.
These frequencies are listed in Table 7. Once the selection of the SQW frequency has been
completed, the SQW pin can be turned on and off under software control with the square
wave enable bit (SQWE) located in register 7FFF6h.
Table 7.
Square wave output frequency
Square wave bits
Square wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hi-Z
32.768
8.192
4.096
2.048
1.024
512
256
128
64
-
kHz
kHz
kHz
kHz
kHz
Hz
Hz
Hz
Hz
32
Hz
16
Hz
8
Hz
4
Hz
2
Hz
1
Hz
21/37
Clock operation
M48T201Y, M48T201V
3.8
Power-on reset
The M48T201Y/V continuously monitors V . When V falls to the power fail detect trip
CC
CC
point, the RST pulls low (open drain) and remains low on power-up for t
after V
REC
CC
passes V
(max). The RST pin is an open drain output and an appropriate pull-up resistor
PFD
to V should be chosen to control rise time.
CC
3.9
Reset inputs (RSTIN1 & RSTIN2)
The M48T201Y/V provides two independent inputs which can generate an output reset. The
duration and function of these resets is identical to a reset generated by a power cycle.
Figure 9 and Table 8 illustrate the AC reset characteristics of this function. Pulses shorter
than t and t will not generate a reset condition. RSTIN1 and RSTIN2 are each internally
R1
R2
pulled up to V through a 100 KΩ resistor.
CC
Figure 9.
RSTIN1 and RSTIN2 timing waveforms
RSTIN1
RSTIN2
RST
tR2
Hi-Z
Hi-Z
tR1
tR1HRZ
tR2HRZ
AI01679
Table 8.
Symbol
tR1
tR2
Reset AC characteristics
Parameter(1)
Min
Max
Unit
RSTIN1 low to RST low
RSTIN2 low to RST low
RSTIN1 high to RST Hi-Z
RSTIN2 high to RST Hi-Z
50
20
40
40
200
100
200
200
ns
ms
ms
ms
(2)
tR1HRZ
tR2HRZ
(2)
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF (see Figure 13 on page 28).
3.10
Calibrating the clock
The M48T201Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are factory calibrated at 25°C and tested for accuracy. Clock
accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25°C,
which equates to about 1.53 minutes per month. When the calibration circuit is properly
employed, accuracy improves to better than +1/–2 ppm at 25°C.
22/37
M48T201Y, M48T201V
Clock operation
The oscillation rate of crystals changes with temperature (see Figure 10 on page 24). The
M48T201Y/V design employs periodic counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in
Figure 11 on page 24.
The number of times pulses which are blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the value loaded into the five calibration bits
found in the control register. Adding counts speeds the clock up, subtracting counts slows
the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the control register 7FFF8h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration (see Figure 11 on
page 24). Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may,
once per minute, have one second either shortened by 128 or lengthened by 256 oscillator
cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle
will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is
running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T201Y/V may
require. The first involves setting the clock, letting it run for a month and comparing it to a
known accurate reference and recording deviation over a fixed period of time. Calibration
values, including the number of seconds lost or gained in a given period, can be found in the
®
STMicroelectronics application note AN934, “TIMEKEEPER calibration.” This allows the
designer to give the end user the ability to calibrate the clock as the environment requires,
even if the final product is packaged in a non-user serviceable enclosure. The designer
could provide a simple utility that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ/FT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 7FFF9h) is '0,'
the frequency test bit (FT, D6 of 7FFFCh) is '1,' the alarm flag enable bit (AFE, D7 of
7FFF6h) is '0,' and the watchdog steering bit (WDS, D7 of 7FFF7h) is '1' or the watchdog
register (7FFF7h=0) is reset.
Note:
A 4-second settling time must be allowed before reading the 512 Hz output.
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.
The IRQ/FT pin is an open drain output which requires a pull-up resistor to V for proper
CC
operation. A 500-10 kΩ resistor is recommended in order to control the rise time. The FT bit
is cleared on power-down.
23/37
Clock operation
M48T201Y, M48T201V
Figure 10. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
2
ΔF
F
ppm
C2
= -0.038
(T - T0) 10%
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 11. Calibration waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
3.11
Battery low warning
The M48T201Y/V automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 7FFF0h, will be asserted if the battery voltage is found to be less than
approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement
and subsequent battery low monitoring tests, either during the next power-up sequence or
the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 V and may not be able to maintain data integrity in the SRAM. Data
should be considered suspect and verified as correct. A fresh battery should be installed.
24/37
M48T201Y, M48T201V
Clock operation
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal V is supplied. In order to insure data integrity during subsequent periods of
CC
®
battery backup mode, the battery should be replaced. The SNAPHAT top may be replaced
while V is applied to the device.
CC
Note:
This will cause the clock to lose time during the interval the battery/crystal is removed.
The M48T201Y/V only monitors the battery when a nominal V is applied to the device.
CC
Thus applications which require extensive durations in the battery backup mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.12
Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state:
WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W; R; FT (see Table 9).
Table 9.
Default values
Condition
Watchdog
register(1)
W
R
FT
AFE
ABE SQWE
Initial power-up
0
0
0
0
0
0
0
(Battery attach for
SNAPHAT)(2)
RESET(3)
Power-down(4)
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1. WDS, BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to '1' prior to power-down.
25/37
Clock operation
M48T201Y, M48T201V
3.13
VCC noise and negative going transients
I
transients, including those produced by output switching, can produce voltage
CC
fluctuations, resulting in spikes on the V bus. These transients can be reduced if
CC
capacitors are used to store energy which stabilizes the V bus. The energy stored in the
CC
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 12) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V that drive it to values below V by as much as
CC
SS
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from V to V (cathode connected to V , anode to V ).
CC
SS
CC
SS
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Figure 12. Supply voltage protection
V
CC
V
CC
0.1μF
DEVICE
V
SS
AI00605
26/37
M48T201Y, M48T201V
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 10. Absolute maximum ratings
Symbol
Parameter
Value
Unit
TA
Ambient operating temperature
0 to 70
–40 to 85
–55 to 125
260
°C
°C
°C
°C
V
SNAPHAT®
SOH44
TSTG
Storage temperature
(1)(2)
TSLD
Lead solder temperature for 10 seconds
Input or output voltage
VIO
–0.3 to VCC + 0.3
–0.3 to 7.0
–0.3 to 4.6
20
M48T201Y
M48T201V
V
VCC
Supply voltage
V
(2)
IO
Output current
mA
W
PD
Power dissipation
1
1. For SOH44 package, standard (SnPb) lead finish: reflow at peak temperature of 225°C (the time above
220°C must not exceed 20 seconds).
2. For SOH44 package, lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (the time above
255°C must not exceed 30 seconds).
Caution:
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
27/37
DC and AC parameters
M48T201Y, M48T201V
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in
Table 11: DC and AC measurement conditions. Designers should check that the operating
conditions in their projects match the measurement conditions when using the quoted
parameters.
Table 11. DC and AC measurement conditions
Parameter
VCC supply voltage
M48T201Y
M48T201V
Unit
4.5 to 5.5
0 to 70
100
3.0 to 3.6
0 to 70
50
V
°C
pF
ns
V
Ambient operating temperature
Load capacitance (CL)
Input rise and fall times
≤ 5
≤ 5
Input pulse voltages
0 to 3
1.5
0 to 3
1.5
Input and output timing ref. voltages
V
Note:
Output High Z is defined as the point where data is no longer driven.
Figure 13. AC testing load circuit
645Ω
DEVICE
UNDER
TEST
C
= 100pF
1.75V
L
C
includes JIG capacitance
L
AI04764
Note:
Excluding open-drain output pin; 50 pF for M48T201V.
Table 12. Capacitance
Symbol
Parameter(1)(2)
Min
Max
Unit
CIN
Input capacitance
10
10
pF
pF
(3)
COUT
Input/output capacitance
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25°C; f = 1 MHz.
3. Outputs deselected.
28/37
M48T201Y, M48T201V
DC and AC parameters
M48T201V
Table 13. DC characteristics
M48T201Y
–70
Sym
Parameter
Test condition(1)
–85
Typ
Unit
Min Typ
Max
Min
Max
(2)
ILI
Input leakage current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
E = VIH
1
1
1
µA
µA
Output leakage
current
(3)
ILO
1
10
3
ICC
Supply current
8
15
5
4
mA
mA
Supply current
(standby) TTL
ICC1
Supply current
(standby) CMOS
ICC2
E = VCC –0.2
VCC = 0 V
3
2
mA
nA
nA
Battery current OSC
ON
575
800
575
800
100
IBAT
Battery current OSC
OFF
100
0.8
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
–0.3
2.2
–0.3
0.8
VCC + 0.3
0.4
V
V
V
VCC + 0.3 2.0
0.4
IOL = 2.1 mA
IOL = 10 mA
VOL
Output low voltage
(open drain)(4)
0.4
0.4
V
VOH
Output high voltage
VOH battery backup
IOH = –1.0 mA
IOUT2 = –1.0 µA
2.4
2.0
2.4
V
V
(5)
VOHB
3.6
2.0
3.6
70
(6)
IOUT1
IOUT2
VPFD
VOUT current (active) VOUT1 > VCC –0.3
100
mA
VOUT current (battery
VOUT2 > VBAT –0.3
backup)
100
4.5
100
3.0
µA
V
Power-fail deselect
voltage
4.1 4.35
2.7
2.9
Battery backup
switchover voltage
VPFD –
100 mV
VSO
3.0
3.0
V
V
VBAT
Battery voltage
3.0
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100 KΩ resistor. WDI internally pulled-down to VSS through
100 KΩ resistor.
3. Outputs deselected.
4. For IRQ/FT & RST pins (open drain).
5. Conditioned outputs (ECON - GCON) can only sustain CMOS leakage currents in the battery backup mode. Higher leakage
currents will reduce battery life.
6. External SRAM must match TIMEKEEPER® supervisor chip VCC specification.
29/37
DC and AC parameters
M48T201Y, M48T201V
Figure 14. Power down/up mode AC waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tREC
INPUTS
VALID
DON'T CARE
VALID
VALID
HIGH-Z
OUTPUTS
VALID
RST
AI03519
Table 14. Power down/up mode AC characteristic
Symbol
Parameter(1)
Min
Max
Unit
(2)
tF
VPFD (max) to VPFD (min) VCC fall time
300
10
150
10
40
5
µs
µs
µs
µs
ms
µs
M48T201Y
M48T201V
(3)
tFB
VPFD (min) to VSS VCC fall time
tR
VPFD (min) to VPFD (max) VCC rise time
VPFD (max) to RST high
tREC
tRB
200
VSS to VPFD (min) VCC rise time
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
30/37
M48T201Y, M48T201V
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
®
Figure 15. SOH44 – 44-lead plastic small outline, SNAPHAT , package outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
Table 15. SOH44 – 44-lead plastic small outline, SNAPHAT , pack. mech. data
®
mm
Min
inches
Min
Symb
Typ
Max
Typ
Max
A
A1
A2
B
3.05
0.36
2.69
0.46
0.32
18.49
8.89
–
0.120
0.014
0.106
0.018
0.012
0.728
0.350
–
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
0.81
0.032
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
a
N
44
44
CP
0.10
0.004
31/37
Package mechanical data
M48T201Y, M48T201V
®
Figure 16. SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, package
outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note:
Drawing is not to scale.
®
Table 16. SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, pack. mech.
data
mm
Min
inches
Min
Symb
Typ
Max
Typ
Max
A
A1
A2
A3
B
9.78
7.24
6.99
0.38
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.56
0.018
0.835
0.560
0.612
0.126
0.080
D
21.84
14.99
15.95
3.61
E
eA
eB
L
2.03
2.29
32/37
M48T201Y, M48T201V
Package mechanical data
®
Figure 17. SH – 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note:
Drawing is not to scale.
®
Table 17. SH – 4-pin SNAPHAT housing for 120 mAh battery & crystal, pack. mech.
data
mm
Min
inches
Min
Symb
Typ
Max
Typ
Max
A
A1
A2
A3
B
10.54
8.51
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
33/37
Part numbering
M48T201Y, M48T201V
7
Part numbering
Table 18. Ordering information scheme
Example:
M48T
201Y
–70
MH
1
F
Device type
M48T
Supply and write protect voltage
201Y = VCC = 4.5 to 5.5 V; VPFD = 4.1 V to 4.5 V
201V = VCC = 3.0 to 3.6 V; VPFD = 2.7 V to 3.0 V
Speed
–70 = 70 ns (for M48T201Y)
–85 = 85 ns (for M48T201V)
Package
MH(1) = SOH44
Temperature range
1 = 0 to 70°C
Shipping method for SOIC
blank = tubes (not for new design - use E)
E = ECOPACK® package, tubes
F = ECOPACK® package, tape and reel
TR = tape and reel (not for new design - use F)
1. The SOIC package (SOH44) requires the battery package (SNAPHAT®) which is ordered separately
under the part number “M4Txx-BR12SH” in plastic tube or “M4Txx-BR12SHTR” in tape & reel form.
Caution:
Do not place the SNAPHAT battery package “M4Txx-BR12SH” in conductive foam as it will
drain the lithium button-cell battery.
For a list of available options (e.g., speed, package) or for further information on any aspect
of this device, please contact the ST sales office nearest to you.
®
Table 19. SNAPHAT battery table
Part number
Description
Package
®
M4T28-BR12SH
M4T32-BR12SH
Lithium battery (48mAh) SNAPHAT
SH
SH
®
Lithium battery (120mAh) SNAPHAT
34/37
M48T201Y, M48T201V
Environmental information
8
Environmental information
Figure 18. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Please refer to the following web site address for additional information regarding
compliance statements and waste recycling.
Go to www.st.com/rtc, then select "Lithium Battery Recycling" from "Related Topics".
35/37
Revision history
M48T201Y, M48T201V
9
Revision history
Table 20. Document revision history
Date
Revision
Changes
Nov-1999
1
First issue
10-May-2001
14-May-2001
30-May-2001
2
Reformatted; added industrial temperature (Table 10, 13, 3, 4, 14)
Corrected table footnote (Table 14)
2.1
2.2
Change “controller” references to “supervisor”
Formatting changes from recent document review findings; E2
added to hookup (Figure 3)
01-Aug-2001
2.3
08-Aug-2001
18-Dec-2001
13-May-2002
16-Jul-2002
27-Mar-2003
2.4
2.5
2.6
2.7
3
Improve text in “Setting the alarm clock” section
Added IBAT values for industrial temperature device (Table 13)
Modify reflow time and temperature footnote (Table 10)
Update DC characteristics, footnotes (Table 13)
v2.2 template applied; update test condition (Table 13)
Reformatted, remove industrial temperature (ambient operating)
references (Table 3, 4, 8, 10, 13, 14, 18)
24-Sep-2004
4
Reformatted; added lead-free second level interconnect information
to cover page and Section 6: Package mechanical data; updated
Table 10.
12-Sep-2007
5
22-Apr-2008
23-Mar-2009
6
7
Updated shipping method in Table 18.
Updated Table 10, text in Section 6: Package mechanical data;
added Section 8: Environmental information.
36/37
M48T201Y, M48T201V
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