M41T11MH [STMICROELECTRONICS]
512 bit 64b x8 Serial Access TIMEKEEPER SRAM; 512位64B X8串行访问TIMEKEEPER SRAM
| 型号： | M41T11MH |
| 厂家： | 
ST |
| 描述： | 512 bit 64b x8 Serial Access TIMEKEEPER SRAM |
| 文件： | 总19页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M41T11
®
512 bit (64b x8) Serial Access TIMEKEEPER SRAM
■ 2.0V to 5.5V SUPPLY VOLTAGE
SNAPHAT (SH)
Battery & Crystal
■ COUNTERS for SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEARS and
CENTURY
■ YEAR 2000 COMPLIANT
■ SOFTWARE CLOCK CALIBRATION
8
■ AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
1
2
■ I C BUS COMPATIBLE
28
■ 56 BYTES of GENERAL PURPOSE RAM
1
SO8 (M)
150mil Width
■ ULTRA-LOW BATTERY SUPPLY CURRENT
SOH28 (MH)
of 1µA
■ LOW OPERATING CURRENT of 300µA
■ OPERATING TEMPERATURE of –40 to 85°C
■ AUTOMATIC LEAP YEAR COMPENSATION
Figure 1. Logic Diagram
■ SPECIAL SOFTWARE PROGRAMMABLE
OUTPUT
■ PACKAGING INCLUDES a 28-LEAD SOIC and
®
SNAPHAT TOP (to be Ordered Separately)
V
V
BAT
CC
Table 1. Signal Names
OSCO
SDA
OSCI
SCL
OSCI
Oscillator Input
M41T11
OCSO
Oscillator Output
FT/OUT
Frequency Test / Output Driver
(Open drain)
FT/OUT
SDA
SCL
Serial Data Address Input / Output
Serial Clock
V
SS
AI01000
V
Battery Supply Voltage
Supply Voltage
BAT
V
CC
V
SS
Ground
May 2000
1/19
M41T11
Figure 2A. SO8 Connections
Figure 2B. SOH28 Connections
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
28
27
V
CC
NC
2
M41T11
3
26
FT/OUT
NC
4
25
OSCI
1
2
3
4
8
V
CC
FT/OUT
5
24
NC
OSCO
7
6
6
23
NC
V
SCL
BAT
7
22
NC
V
5
SDA
SS
M41T11
8
21
NC
AI01001
9
20
SCL
NC
10
11
12
13
14
19
18
NC
17
NC
16
SDA
NC
V
15
SS
DESCRIPTION
AI03606
®
The M41T11 TIMEKEEPER RAM is a low power
512 bit static CMOS RAM organized as 64 words
by 8 bits. A built-in 32.768 kHz oscillator (external
crystal controlled) and the first 8 bytes of the RAM
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a
two-line bi-directional bus. The built-in address
register is incremented automatically after each
write or read data byte.
The M41T11 clock has a built-in power sense cir-
cuit which detects power failures and automatical-
ly switches to the battery supply during power
failures. The energy needed to sustain the RAM
and clock operations can be supplied from a small
lithium coin cell.
Typical data retention time is in excess of 5 years
with a 50mA/h 3V lithium cell. The M41T11 is sup-
plied in 8 lead Plastic Small Outline package or 28
lead SNAPHAT package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery/crys-
tal packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form.
For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is "M4Txx-
BR12SHx".
Caution: Do not place the SNAPHAT battery/crys-
tal package "M4Txx-BR12SHx" in conductive
foam since this will drain the lithium button-cell
battery.
2/19
M41T11
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
T
Ambient Operating Temperature
–40 to 85
–40 to 85
–55 to 125
°C
A
SNAPHAT
SOIC
T
Storage Temperature (V Off, Oscillator Off)
°C
STG
CC
(2)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
260
–0.3 to 7
–0.3 to 7
20
°C
V
T
SLD
V
IO
V
V
CC
I
Output Current
mA
W
O
P
D
Power Dissipation
0.25
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
OPERATION
The M41T11 clock continually monitors V for an
CC
out of tolerance condition. Should V
fall below
CC
The M41T11 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 64 bytes contained in the device
can then be accessed sequentially in the following
order:
V
, the device terminates an access in progress
SO
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from an out of tolerance system. When V
CC
falls below V , the device automatically switches
SO
1.
2.
3.
4.
5.
6.
7.
8.
Seconds Register
Minutes Register
Century/Hours Register
Day Register
Date Register
Month Register
Years Register
over to the battery and powers down into an ultra
low current mode of operation to conserve battery
life. Upon power-up, the device switches from bat-
tery to V
at V
and recognizes inputs.
CC
SO
Control Register
9 to 64. RAM
3/19
M41T11
Figure 3. Block Diagram
1 Hz
SECONDS
MINUTES
CENTURY/HOURS
DAY
OSCI
OSCILLATOR
32.768 kHz
DIVIDER
OSCO
FT/OUT
DATE
MONTH
VOLTAGE
SENSE
V
CC
YEAR
CONTROL
LOGIC
and
V
SS
CONTROL
SWITCH
CIRCUITRY
V
BAT
RAM
(56 x 8)
SCL
SDA
SERIAL
BUS
INTERFACE
ADDRESS
REGISTER
AI02566
Table 3. Register Map
Address
Data
Function/Range
BCD Format
D7
ST
X
D6
D5
D4
D3
D2
D1
D0
0
1
2
10 Seconds
10 Minutes
Seconds
Minutes
Hours
Seconds
Minutes
00-59
00-59
(1)
CB
10 Hours
Century/Hour 0-1/00-23
CEB
X
3
4
5
6
7
X
X
X
X
X
S
X
X
Day
Day
Date
01-07
01-31
01-12
00-99
X
10 Date
10 M.
Date
Month
Years
X
Month
Year
10 Years
OUT
FT
Calibration
Control
Note: 1. When CEB is set to ’1’, CB will toggle from ’0’ to ’1’ or from ’1’ to ’0’ every 100 years (dependent upon the initial value set).
When CEB is set to ’0’, CB will not toggle.
Keys: S = SIGN Bit;
FT = FREQUENCY TEST Bit;
X = Don’t care;
CEB = Century Enable Bit;
CB = Century Bit.
ST = STOP Bit;
OUT = Output level;
4/19
M41T11
Table 4. AC Measurement Conditions
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
Input Pulse Voltages
≤ 5ns
0.2V to 0.8V
CC
CC
Input and Output Timing Ref.
Voltages
0.3V to 0.7V
CC
CC
0.8V
CC
0.7V
CC
Note that Output Hi-Z is defined as the point where data is no longer
driven.
0.3V
CC
0.2V
CC
2-WIRE BUS CHARACTERISTICS
AI02568
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock sig-
nals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition, a device that gives out a message is
called "transmitter", the receiving device that gets
the message is called "receiver". The device that
controls the message is called "master". The de-
vices that are controlled by the master are called
"slaves".
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line while the clock line is
High will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
(1, 2)
Table 5. Capacitance
(T = 25 °C, f = MHz)
A
Symbol
Parameter
Min
Max
Unit
C
IN
Input Capacitance (SCL)
7
pF
(3)
Output Capacitance (SDA, FT/OUT)
10
pF
ns
C
OUT
t
Low-pass filter input time constant (SDA and SCL)
250
1000
LP
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled, not 100% tested.
3. Outputs deselected.
5/19
M41T11
Table 6. DC Characteristics
(T = –40 to 85 °C; V = 2.0V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
0V ≤ V ≤ V
Input Leakage Current
±1
µA
I
IN
CC
LI
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
±1
300
70
µA
µA
µA
V
I
OUT
LO
I
Switch Frequency = 100kHz
CC1
I
SCL, SDA = V – 0.3V
Supply Current (Standby)
Input Low Voltage
CC2
CC
V
0.3V
CC
–0.3
IL
V
V
0.7V
V
CC
+ 0.8
Input High Voltage
V
IH
CC
I
= 3mA
OL
Output Low Voltage
Battery Supply Voltage
0.4
V
OL
(1)
2
3
3.5
1
V
V
BAT
T = 25°C, V = 0V,
Oscillator ON, V
A
CC
I
Battery Supply Current
0.8
µA
BAT
= 3V
BAT
Note: 1. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
(1)
Table 7. Power Down/Up Trip Points DC Characteristics
(T = –40 to 85 °C)
A
Symbol
Parameter
Min
–0.70
Typ
–0.50
Max
V –0.30
BAT
Unit
(2)
V
V
Battery Back-up Switchover Voltage
V
V
SO
BAT
BAT
Note: 1. All voltages referenced to V
.
SS
2. Switch-over and deselect point.
Table 8. Crystal Electrical Characteristics
(Externally Supplied if using the SO8 package)
Symbol
Parameter
Resonant Frequency
Min
Typ
Max
Unit
kHz
kΩ
f
32.768
O
R
S
Series Resistance
Load Capacitance
35
C
L
12.5
pF
Note: Load capacitors are integrated within the M41T11. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
STMicroelectronics recommends the KDS DT-38 Tuning Fork Type quartz crystal for industrial temperature operations.
KDS can be contacted at 913-491-6825 or http://www.kdsj.co.jp for further information on this crystal type.
All SNAPHAT battery/crystal tops meet these specifications.
6/19
M41T11
(1)
Table 9. Power Down/Up AC Characteristics
(T = –40 to 85 °C)
A
Symbol
Parameter
Min
Max
Unit
t
SCL and SDA at V before Power Down
0
ns
PD
IH
SCL and SDA at V after Power Up
10
µs
t
IH
REC
Note: 1. V fall time should not exceed 5mV/µs.
CC
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
SO
tPD
tREC
SDA
SCL
DON'T CARE
AI00596
Acknowledge. Each byte of eight bits is followed
by one acknowledge bit. This acknowledge bit is a
low level put on the bus by the receiver, whereas
the master generates an extra acknowledge relat-
ed clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
7/19
M41T11
Table 10. AC Characteristics
(T = –40 to 85 °C; V = 2.0V to 5.5V)
A
CC
Symbol
Parameter
Min
0
Max
Unit
kHz
µs
f
SCL Clock Frequency
Clock Low Period
100
SCL
t
4.7
4
LOW
t
Clock High Period
µs
HIGH
t
SDA and SCL Rise Time
SDA and SCL Fall Time
1
µs
R
t
300
ns
F
START Condition Hold Time
(after this period the first clock pulse is generated)
t
4
µs
HD:STA
START Condition Setup Time
(only relevant for a repeated start condition)
t
4.7
µs
ns
SU:STA
t
Data Setup Time
250
SU:DAT
(1)
Data Hold Time
0
µs
µs
µs
t
HD:DAT
t
STOP Condition Setup Time
4.7
4.7
SU:STO
t
Time the bus must be free before a new transmission can start
BUF
Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
WRITE MODE
ten to the on-chip address pointer. Next the
START condition and slave address are repeated,
followed by the READ mode control bit (R/W = 1).
At this point, the master transmitter becomes the
master receiver. The data byte which was ad-
dressed will be transmitted and the master receiv-
er will send an acknowledge bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an acknowledge bit. The
M41T11 slave transmitter will now place the data
In this mode the master transmitter transmits to
the M41T11 slave receiver. Bus protocol is shown
in Figure 10. Following the START condition and
slave address, a logic ’0’ (R/W = 0) is placed on the
bus and indicates to the addressed device that
word address An will follow and is to be written to
the on-chip address pointer. The data word to be
written to the memory is strobed in next and the in-
ternal address pointer is incremented to the next
memory location within the RAM on the reception
of an acknowledge clock. The M41T11 slave re-
ceiver will send an acknowledge clock to the mas-
ter transmitter after it has received the slave
address and again after it has received the word
address and each data byte (see Figure 9).
byte at address A + 1 on the bus. The master re-
n
ceiver reads and acknowledges the new byte and
the address pointer is incremented to A + 2.
n
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
An alternate READ mode may also be implement-
ed, whereby the master reads the M41T11 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer, see Figure 12.
READ MODE
In this mode, the master reads the M41T11 slave
after setting the slave address (see Figure 11).
Following the write mode control bit (R/W = 0) and
the acknowledge bit, the word address A is writ-
n
8/19
M41T11
Figure 6. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 7. Acknowledgment Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
1
2
8
9
MASTER
DATA OUTPUT
MSB
LSB
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
AI00601
CLOCK OPERATION
to stop. If the device is expected to spend a signif-
icant amount of time on the shelf, the oscillator
may be stopped to reduce current drain. When re-
set to a ’0’ the oscillator restarts within one second.
The seven Clock Registers may be read one byte
at a time, or in a sequential block. The Control
Register (Address location 7) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
seven clock addresses are being read. If a clock
address is being read, an update of the clock reg-
isters will be delayed by 250ms to allow the read
to be completed before the update occurs. This
will prevent a transition of data during the read.
The eight byte clock register (see Table 3) is used
to both set the clock and to read the date and time
from the clock, in a binary coded decimal format.
Seconds, Minutes, and Hours are contained within
the first three registers. Bits D6 and D7 of clock
register 2 (Hours Register) contain the CENTURY
ENABLE Bit (CEB) and the CENTURY Bit (CB).
Setting CEB to a ’1’ will cause CB to toggle, either
from ’0’ to ’1’ or from ’1’ to ’0’ at the turn of the cen-
tury (depending upon its initial state). If CEB is set
to a ’0’, CB will not toggle. Bits D0 through D2 of
register 3 contain the Day (day of week). Registers
4, 5 and 6 contain the Date (day of month), Month
and Years. The final register is the Control Regis-
ter (this is described in the Clock Calibration sec-
tion). Bit D7 of register 0 contains the STOP Bit
(ST). Setting this bit to a ’1’ will cause the oscillator
Note: This 250ms delay affects only the clock reg-
ister update and does not alter the actual clock
time.
9/19
M41T11
Figure 8. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
Note: P = STOP and S = START
Figure 9. Slave Address Location
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 13.
The number of times pulses are blanked (subtract-
ed, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five bit Calibration byte found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
R/W
START
SLAVE ADDRESS
A
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control register (Addr 7). This
byte can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
1
1
0
1
0
0
0
AI00602
CLOCK CALIBRATION
The M41T11 is driven by a quartz controlled oscil-
lator with a nominal frequency of 32,768Hz. The
devices are tested not to exceed 35ppm (parts per
million) oscillator frequency error at 25°C, which
equates to about ±1.53 minutes per month. With
the calibration bits properly set, the accuracy of
each M41T11 improves to better than +1/–2 ppm
at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 14). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M41T11 design, however, employs periodic
10/19
M41T11
Figure 10. Write Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (n)
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00591
Figure 11. Read Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (n)
SDA LINE
S
S
DATA n
DATA n+1
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+X
P
AI00899
Figure 12. Alternate Read Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
11/19
M41T11
Figure 13. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Two methods are available for ascertaining how
much calibration a given M41T11 may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his en-
vironment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accessed the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) bit, the seventh-most significant bit in the
Control Register, is set to a '1', and the oscillator is
running at 32,768Hz, the FT/OUT pin of the device
will toggle at 512Hz. Any deviation from 512Hz in-
dicates the degree and direction of oscillator fre-
quency shift at the test temperature.
For example, a reading of 512.01024Hz would in-
dicate a +20ppm oscillator frequency error, requir-
ing a –10(XX001010) to be loaded into the
Calibration Byte for correction. Note that setting or
changing the Calibration Byte does not affect the
Frequency test output frequency.
OUTPUT DRIVER PIN
When the FT bit is not set, the FT/OUT pin be-
comes an output driver that reflects the contents of
D7 of the control register. In other words, when D6
of location 7 is a zero and D7 of location 7 is a zero
and then the FT/OUT pin will be driven low.
Note: The FT/OUT pin is open drain which re-
quires an external pull-up resistor.
POWER-ON DEFAULTS
Upon initial application of power to the device, the
FT bit will be set to a '0' and the OUT bit will be set
to a '1'. All other Register bits will initially power-on
in a random state.
12/19
M41T11
Figure 14. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
13/19
M41T11
Table 11. Ordering Information Scheme
Example:
M41T11
M
6
TR
Device Type
M41T
Package
M = SO8 150mil Width
MH = SOH28
Temperature Range
6 = –40 to 85 °C
Shipping Method for SO
blank = Tubes
TR = Tape & Reel
Note: The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
"M4Txx-BR12SHx" in plastic tube or "M4Txx-BR12SHxTR" in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package "M4Txx-BR12SHx" in conductive foam since this will drain the lithium button-cell
battery.
For a list of available options or for further information on any aspect of this device, please contact the
STMicroelectronics Sales Office nearest to you.
Table 12. Revision History
Date
March 1999
12/23/99
Revision Details
First Issue
SOH28 package added
R
value change (Table 8)
05/22/00
S
14/19
M41T11
Table 13. SO8 - 8 pin Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
Figure 15. SO8 - 8 pin Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Drawing is not to scale.
15/19
M41T11
Table 14. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT,
Package Mechanical Data
mm
Min
inches
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Min
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
Figure 16. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
16/19
M41T11
Table 15. M4T28-BR12SH - TIMEKEEPER 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal,
Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
3.20
0.018
0.835
0.560
0.126
0.080
D
E
eB
L
2.03
Figure 17. M4T28-BR12SH - TIMEKEEPER 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal,
Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
17/19
M41T11
Table 16. M4T32-BR12SH - TIMEKEEPER 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal,
Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
8.00
0.38
0.56
21.84
18.03
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.142
0.090
8.00
7.24
0.315
0.285
0.46
21.21
17.27
3.20
0.018
0.835
0.680
0.126
0.080
D
E
eB
L
2.03
Figure 18. M4T32-BR12SH - TIMEKEEPER 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal,
Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-B
Drawing is not to scale.
18/19
M41T11
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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