M41T00SMY6 [STMICROELECTRONICS]
REAL TIME CLOCK, PDSO8, 0.300 INCH, PLASTIC, SO-8;
| 型号： | M41T00SMY6 |
| 厂家： | 
ST |
| 描述： | REAL TIME CLOCK, PDSO8, 0.300 INCH, PLASTIC, SO-8 时钟 光电二极管 外围集成电路 |
| 文件： | 总24页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M41T00S
Serial Access Real-Time Clock
PRELIMINARY DATA
FEATURES SUMMARY
■
2.0 TO 5.5V CLOCK OPERATING VOLTAGE
Figure 1. Packages
■
COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY
8
■
■
SOFTWARE CLOCK CALIBRATION
1
AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY (FIXED
REFERENCE)
SO8 (M)
8-pin SOIC
–
V
= 2.7 to 5.5V
CC
2.5V ≤ V
≤ 2.7V
PFD
2
■
SERIAL INTERFACE SUPPORTS I C BUS
(400kHz PROTOCOL)
■
■
■
■
LOW OPERATING CURRENT OF 300µA
OSCILLATOR STOP DETECTION
BATTERY OR SUPER-CAP BACK-UP
OPERATING TEMPERATURE OF –40 TO
85°C
18
1
SOX18 (MY)
18-pin (300mil) SOIC
with Embedded Crystal
■
■
ULTRA-LOW BATTERY SUPPLY CURRENT
OF 1µA
PACKAGE OPTIONS INCLUDE AN 8-LEAD
SOIC OR 18-LEAD EMBEDDED CRYSTAL
SOIC
September 2004
1/24
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M41T00S
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. 8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. 18-pin, 300mil SOIC (MY) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10.Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Oscillator Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/24
M41T00S
Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17.SO8 – 8-lead Plastic Small Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mech. Data . . . . . . 20
Figure 18.SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Outline . . . . . . . . 21
Table 13. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Mechanical. . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3/24
M41T00S
SUMMARY DESCRIPTION
The M41T00S Serial Access TIMEKEEPER
®
clock operations can be supplied by a small lithium
button supply when a power failure occurs. The
eight clock address locations contain the century,
year, month, date, day, hour, minute, and second
in 24 hour BCD format. Corrections for 28, 29
(leap year - valid until year 2100), 30 and 31 day
months are made automatically.
The M41T00S is supplied in either an 8-pin SOIC
or an 18-pin (MY), 300mil SOIC package which in-
cludes an embedded 32kHz crystal.
SRAM is a low power Serial RTC with a built-in
32.768kHz oscillator (external crystal controlled).
Eight bytes of the SRAM (see Table 2., page 11)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a
2
two line, bi-directional I C interface. The built-in
address register is incremented automatically af-
ter each WRITE or READ data byte.
The M41T00S has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
The 18-pin, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile op-
eration.
Figure 2. Logic Diagram
Table 1. Signal Names
(1)
Oscillator Input
XI
V
V
CC BAT
(1)
Oscillator Output
XO
XI(1)
XO(1)
SCL
Frequency Test / Output Driver
(Open Drain)
FT/OUT
M41T00S
FT/OUT
SDA
SCL
Serial Data Input/Output
Serial Clock Input
Battery Supply Voltage
Supply Voltage
SDA
V
BAT
V
CC
V
SS
AI09165
V
SS
Ground
Note: 1. For SO8 package only.
Note: 1. For SO8 package only.
Figure 4. 18-pin, 300mil SOIC (MY)
Connections
Figure 3. 8-pin SOIC (M) Connections
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
NC
NC
NC
NC
VCC
NC
NC
NC
NC
NC
NC
VBAT
VSS
VCC
FT/OUT(1)
SCL
XI
XO
VBAT
1
2
3
4
8
7
6
5
M41T00S
NC
M41T00S
FT/OUT(1)
NC
SDA
VSS
AI09166
SCL
SDA
AI09167
Note: 1. Open Drain Output
Note: 1. Open Drain Output
4/24
M41T00S
Figure 5. Block Diagram
REAL TIME CLOCK
CALENDAR
OSCILLATOR FAIL
CIRCUIT
32KHz
CRYSTAL
OSCILLATOR
RTC &
CALIBRATION
FT
FT/OUT(1)
FREQUENCY TEST
OUTPUT DRIVER
SDA
SCL
I2C
INTERFACE
OUT
WRITE
PROTECT
INTERNAL
POWER
VCC
VBAT
VSO
COMPARE
VPFD
AI09168
Note: 1. Open Drain Output
5/24
M41T00S
OPERATION
The M41T00S clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 8 bytes contained in the device
can then be accessed sequentially in the following
order:
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
1. Seconds Register
2. Minutes Register
3. Century/Hours Register
4. Day Register
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
5. Date Register
6. Month Register
7. Year Register
8. Calibration Register
The M41T00S clock continually monitors V
an out-of-tolerance condition. Should V
for
fall be-
CC
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
CC
low V
, the device terminates an access in
PFD
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Once V
falls below the switchover voltage
CC
(V ), the device automatically switches over to
SO
the battery and powers down into an ultra-low cur-
rent mode of operation to preserve battery life. If
V
is less than V
, the device power is
PFD
BAT
switched from V to V
when V drops below
CC
BAT
CC
V
. If V
is greater than V
, the device
when V
CC
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
BAT
BAT
PFD
power is switched from V
drops below V
switches from battery to V
rises above V
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
to V
BAT
CC
. Upon power-up, the device
PFD
at V . When V
CC
SO CC
, it will recognize the inputs.
PFD
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
The bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
–
–
–
Data transfer may be initiated only when the
bus is not busy.
During data transfer, the data line must remain
stable whenever the clock line is High.
Changes in the data line, while the clock line is
High, will be interpreted as control signals.
6/24
M41T00S
Figure 6. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 7. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
1
2
8
9
MASTER
DATA OUTPUT
MSB
LSB
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
AI00601
7/24
M41T00S
READ Mode
In this mode the master reads the M41T00S slave
after setting the slave address (see Figure
9., page 9). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an Acknowledge Bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T00S slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented
to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 06h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (07h).
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T00S slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 10., page 9).
Figure 8. Slave Address Location
R/W
START
SLAVE ADDRESS
A
1
1
0
1
0
0
0
AI00602
8/24
M41T00S
Figure 9. READ Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (An)
SDA LINE
S
S
DATA n
DATA n+1
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+X
P
AI00899
Figure 10. Alternative READ Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
9/24
M41T00S
WRITE Mode
Data Retention Mode
With valid V applied, the M41T00S can be ac-
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the pow-
In this mode the master transmitter transmits to
the M41T00S slave receiver. Bus protocol is
shown in Figure 11. Following the START condi-
tion and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T00S slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 8., page 8 and again after it has re-
ceived the word address and each data byte.
CC
er input will be switched from the V
pin to the
CC
battery when V
falls below the Battery Back-up
CC
Switchover Voltage (V ). At this time the clock
SO
registers will be maintained by the attached bat-
tery supply. On power-up, when V
nominal value, write protection continues for t
returns to a
CC
.
REC
For a further, more detailed review of lifetime cal-
culations, please see Application Note AN1012.
Figure 11. WRITE Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (An)
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00591
10/24
M41T00S
CLOCK OPERATION
The 8-byte Register Map (see Table 2) is used to
both set the clock and to read the date and time
from the clock, in a binary coded decimal format.
Seconds, Minutes, and Hours are contained within
the first three registers.
independently. Provision has been made to as-
sure that a clock update does not occur while any
of the seven clock addresses are being read. If a
clock address is being read, an update of the clock
registers will be halted. This will prevent a transi-
tion of data during the READ.
Bits D6 and D7 of Clock Register 02h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (de-
pending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
03h contain the Day (day of week). Registers 04h,
05h, and 06h contain the Date (day of month),
Month and Years. The eighth clock register is the
Calibration Register (this is described in the Clock
Calibration section). Bit D7 of Register 00h con-
tains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expect-
ed to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce cur-
rent drain. When reset to a '0' the oscillator restarts
within one second.
Clock Registers
The M41T00S offers 8 internal registers which
contain Clock and Calibration data. These regis-
ters are memory locations which contain external
(user accessible) and internal copies of the data
™
(usually referred to as BiPORT TIMEKEEPER
cells). The external copies are independent of in-
ternal functions except that they are updated peri-
odically by the simultaneous transfer of the
incremented internal copy. The internal divider (or
clock) chain will be reset upon the completion of a
WRITE to any clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 06h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to any non-clock address (07h).
The seven Clock Registers may be read one byte
at a time, or in a sequential block. The Calibration
Register (Address location 07h) may be accessed
Clock Registers store data in BCD. The Calibra-
tion Register stores data in Binary Format.
®
Table 2. TIMEKEEPER Register Map
Addr
Function/Range BCD
Format
D7
ST
OF
D6
D5
D4
D3
D2
D1
D0
00h
01h
10 Seconds
10 Minutes
Seconds
Seconds
Minutes
00-59
00-59
Minutes
Century/
Hours
02h
CEB
CB
10 Hours
Hours (24 Hour Format)
0-1/00-23
03h
04h
05h
06h
07h
0
0
0
0
0
0
0
0
0
0
Day of Week
Date: Day of Month
Month
Day
Date
01-7
01-31
01-12
00-99
10 Date
10M
Month
Year
10 Years
FT
Year
OUT
S
Calibration
Calibration
Keys: 0 = Must be set to '0'
CB = Century Bit
OF = Oscillator Fail Bit
OUT = Output level
S = Sign Bit
CEB = Century Enable Bit
FT = Frequency Test Bit
ST = Stop Bit
11/24
M41T00S
Calibrating the Clock
The M41T00S is driven by a quartz-controlled os-
cillator with a nominal frequency of 32,768 Hz. The
devices are tested not exceed ±35 ppm (parts per
ning at exactly 32,768 Hz, each of the 31 incre-
ments in the Calibration byte would represent
+10.7 or –5.35 seconds per month which corre-
sponds to a total range of +5.5 or –2.75 minutes
per month.
Two methods are available for ascertaining how
much calibration a given M41T00S may require.
o
million) oscillator frequency error at 25 C, which
equates to about ±1.53 minutes per month (see
Figure 12., page 13). When the Calibration circuit
is properly employed, accuracy improves to better
than ±2 ppm at 25°C.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEP-
The oscillation rate of crystals changes with tem-
perature. The M41T00S design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure
13., page 13. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration Bits found
in the Calibration Register. Adding counts speeds
the clock up, subtracting counts slows the clock
down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Calibration Register 07h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
®
ER CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final prod-
uct is packaged in a non-user serviceable enclo-
sure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
FT/OUT pin. The pin will toggle at 512Hz, when
the Stop Bit (ST, D7 of 00h) is '0,' and the Frequen-
cy Test Bit (FT, D6 of 07h) is '1.'
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example,
a
reading of
512.010124 Hz would indicate a +20 ppm oscilla-
tor frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register (see Figure
13., page 13). Assuming that the oscillator is run-
The FT/OUT pin is an open drain output which re-
quires a pull-up resistor to V
for proper opera-
CC
tion. A 500-10k resistor is recommended in order
to control the rise time. The FT Bit is cleared on
power-down.
12/24
M41T00S
Figure 12. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
2
∆F
F
= K x (T – TO)
–80
–100
–120
–140
–160
= –0.036 ppm/°C2 ± 0.006 ppm/°C2
O = 25°C ± 5°C
K
T
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Figure 13. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
13/24
M41T00S
Century Bit
Bits D7 and D6 of Clock Register 02h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to tog-
gle, either from a '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle.
The OF Bit will remain set to '1' until written to logic
'0.' The oscillator must start and have run for at
least 4 seconds before attempting to reset the OF
Bit to '0.'
Output Driver Pin
When the FT Bit is not set, the FT/OUT pin be-
comes an output driver that reflects the contents of
D7 of the Calibration Register. In other words,
when D7 (OUT Bit) and D6 (FT Bit) of address lo-
cation 07h are a '0,' then the FT/OUT pin will be
driven low.
Oscillator Fail Detection
If the Oscillator Fail Bit (OF) is internally set to '1,'
this indicates that the oscillator has either stopped,
or was stopped for some period of time and can be
used to judge the validity of the clock and date da-
ta.
Note: The FT/OUT pin is an open drain which re-
In the event the OF Bit is found to be set to '1' at
any time other than the initial power-up, the STOP
Bit (ST) should be written to a '1,' then immediately
reset to '0.' This will restart the oscillator.
The following conditions can cause the OF Bit to
be set:
quires an external pull-up resistor.
Preferred Initial Power-on Default
Upon initial application of power to the device, the
ST and FT bits are set to a '0' state, and the OF
and OUT Bits will be set to a '1.' All other Register
bits will initially power-on in a random state (see
Table 3).
–
The first time power is applied (defaults to a '1'
on power-up).
–
The voltage present on V is insufficient to
support oscillation.
CC
–
–
The ST Bit is set to '1.'
External interference of the crystal.
Table 3. Preferred Default Values
Condition
ST
0
Out
1
FT
0
OF
1
(1)
Initial Power-up
(2)
UC
UC
0
UC
Subsequent Power-up (with battery back-up)
Note: 1. State of other control bits undefined.
2. UC = Unchanged
14/24
M41T00S
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 4. Absolute Maximum Ratings
Sym
Parameter
Value
–55 to 125
–0.3 to 7
260
Unit
°C
T
Storage Temperature (V Off, Oscillator Off)
SOIC
STG
CC
V
CC
Supply Voltage
V
(1)
°C
°C
Lead-free lead finish
Standard (SnPb)
Lead Solder Temperature for 10 Seconds
T
SLD
240
(2,3)
lead finish
V
Input or Output Voltages
Output Current
–0.3 to Vcc+0.3
V
mA
W
IO
I
O
20
1
P
Power Dissipation
D
Note: 1. For SO8 package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
2. For SO8 package, standard (SnPb) lead finish: Reflow at peak temperature of 240°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
3. The SOX18 package has Lead-free (Pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240°C
(use same reflow profile as standard (SnPb) lead finish).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up Mode
15/24
M41T00S
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 5. Operating and AC Measurement Conditions
Parameter
M41T00S
2.7 to 5.5V
–40 to 85°C
100pF
Supply Voltage (V
)
CC
Ambient Operating Temperature (T )
A
Load Capacitance (C )
L
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
0.2V to 0.8 V
CC
CC
CC
0.3V to 0.7 V
Input and Output Timing Ref. Voltages
CC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 14. AC Measurement I/O Waveform
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI02568
Table 6. Capacitance
(1,2)
Symbol
Min
Max
7
Unit
pF
Parameter
C
Input Capacitance
Output Capacitance
IN
(3)
10
50
pF
C
OUT
t
LP
Low-pass filter input time constant (SDA and SCL)
ns
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
16/24
M41T00S
Table 7. DC Characteristics
(1)
Sym
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Min
Typ
Max
Unit
µA
Test Condition
I
LI
0V ≤ V ≤ V
±1
±1
IN
CC
I
0V ≤ V
≤ V
µA
LO
OUT CC
I
Switch Freq = 400kHz
300
µA
CC1
SCL = 0Hz
All Inputs
I
Supply Current (standby)
70
µA
CC2
≥ V – 0.2V
CC
≤ V + 0.2V
SS
V
0.3V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.3
V
V
V
V
V
V
IL
CC
V
IH
0.7V
V
CC
+ 0.3
CC
I
= 3.0mA
= 10mA
0.4
OL
V
OL
(2)
I
0.4
5.5
OL
Output Low Voltage (Open Drain)
Pull-up Supply Voltage (Open Drain)
Back-up Supply Voltage
FT/OUT
(3)
(4)
2.0
V
3.5
BAT
T = 25°C, V = 0V
A
CC
I
Battery Supply Current
0.6
1
µA
BAT
Oscillator ON, V
= 3V
BAT
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.7 to 5.5V (except where noted).
A
CC
2. For FT/OUT pin (Open Drain)
3. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
4. For rechargeable back-up, V (max) may be considered to be V
.
CC
BAT
Table 8. Crystal Electrical Characteristics
(1,2)
Sym
Min
Typ
Max
Units
kHz
kΩ
Parameter
Resonant Frequency
f
O
32.768
(3)
R
Series Resistance
Load Capacitance
S
60
C
12.5
pF
L
Note: 1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork
Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be con-
tacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T00S. Circuit board layout considerations for the 32.768kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
3. For applications requiring back-up supply operation below 2.5V, R (max) should be considered 40kΩ.
S
17/24
M41T00S
Figure 15. Power Down/Up Mode AC Waveforms
V
CC
V
SO
tPD
trec
SDA
SCL
DON'T CARE
AI00596
Table 9. Power Down/Up AC Characteristics
(1,2)
Symbol
Min
0
Typ
Max
Unit
nS
Parameter
t
SCL and SDA at V before Power Down
PD
IH
t
SCL and SDA at V after Power Up
10
µS
rec
IH
Note: 1. V fall time should not exceed 5mV/µs.
CC
2. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.7 to 5.5V (except where noted).
A
CC
Table 10. Power Down/Up Trip Points DC Characteristics
(1,2)
Sym
Min
Typ
2.6
25
Max
Unit
V
Parameter
Power-fail Deselect
Hysteresis
2.5
2.7
V
PFD
mV
V
V
V
< V
> V
V
BAT
BAT
PFD
PFD
Battery Back-up Switchover Voltage
(V < V ; V < V
)
PFD
CC
BAT CC
V
SO
V
V
BAT
PFD
Hysteresis
40
mV
Note: 1. All voltages referenced to V
.
SS
2. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.7 to 5.5V (except where noted).
A
CC
18/24
M41T00S
Figure 16. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
Table 11. AC Characteristics
Sym
(1)
Min
0
Typ
Max
Units
kHz
µs
Parameter
f
SCL Clock Frequency
400
SCL
t
Clock Low Period
1.3
600
LOW
t
Clock High Period
ns
HIGH
t
SDA and SCL Rise Time
SDA and SCL Fall Time
START Condition Hold Time
300
300
ns
R
t
ns
F
t
t
600
600
ns
ns
HD:STA
(after this period the first clock pulse is generated)
START Condition Setup Time
(only relevant for a repeated start condition)
SU:STA
(2)
Data Setup Time
100
0
ns
µs
ns
t
SU:DAT
t
Data Hold Time
HD:DAT
SU:STO
t
STOP Condition Setup Time
600
Time the bus must be free before a new
transmission can start
t
1.3
µs
BUF
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.7 to 5.5V (except where noted).
A
CC
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
19/24
M41T00S
PACKAGE MECHANICAL INFORMATION
Figure 17. SO8 – 8-lead Plastic Small Package Outline
h x 45˚
C
A2
A
B
ddd
e
D
8
1
E
H
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 12. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mech. Data
mm
Min
1.35
0.10
1.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
1.65
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.065
0.020
0.010
0.197
0.157
–
A
A1
A2
B
0.053
0.004
0.043
0.013
0.007
0.189
0.150
–
C
D
E
e
1.27
0.050
H
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
L
α
N
8
8
ddd
0.10
0.004
20/24
M41T00S
Figure 18. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Outline
D
9
1
h x 45°
C
E
H
10
18
A2
A
ddd
A1
B
e
A1
α
L
SO-J
Note: Drawing is not to scale.
Table 13. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Mechanical
millimeters
inches
Symbol
Typ
Min
Max
2.69
0.31
2.39
0.51
0.31
11.66
0.10
7.67
–
Typ
Min
Max
0.106
0.012
0.094
0.020
0.012
0.459
0.004
0.302
–
A
A1
A2
B
2.44
0.096
0.006
0.090
0.016
0.008
0.455
0.15
2.29
0.41
C
0.20
D
11.61
1.27
11.56
0.457
0.050
ddd
E
7.57
–
0.298
–
e
H
10.16
0.51
0°
10.52
0.81
8°
0.400
0.020
0°
0.414
0.032
8°
L
α
N
18
18
21/24
M41T00S
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M41T
00S
M
6
E
Device Type
M41T
Supply Voltage and Write Protect Voltage
00S = V = 2.7 to 5.5V
CC
Package
M = SO8
(1)
MY = SOX18
Temperature Range
6 = –40°C to 85°C
Shipping Method
For SO8:
blank = Tubes (Not for New Design - Use E)
®
E = Lead-free Package (ECO PACK ), Tubes
®
F = Lead-free Package (ECO PACK ), Tape & Reel
T = Tape & Reel (Not for New Design - Use F)
For SOX18:
blank = Tubes
T = Tape & Reel
Note: 1. The SOX18 package includes an embedded 32,768Hz crystal.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
22/24
M41T00S
REVISION HISTORY
Table 15. Document Revision History
Date
Version
0.1
Revision Details
February 10, 2004
20-Feb-04
First Draft
Update characteristics (Table 9, 10, 5, 7, 14)
0.2
Product promoted; reformatted; update characteristics, including Lead-free package
information (Figure 4. 12; Table 4. 11, 14)
14-Apr-04
1.0
05-May-04
16-Jun-04
13-Sep-04
1.1
1.2
2.0
Update DC Characteristics (Table 7)
Added package shipping (Table 14)
Update Maximum ratings (Table 4)
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Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watch-
dog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,
Watchdog, Watchdog, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Back-
up, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Write Protect, Write
Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect,
Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Pro-
tect, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, vIndustrial, Industrial, Industrial, SOIC, SOIC,
SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC
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