M41T0DS6T [STMICROELECTRONICS]
SERIAL REAL-TIME CLOCK; 串行实时时钟
| 型号： | M41T0DS6T |
| 厂家： | 
ST |
| 描述： | SERIAL REAL-TIME CLOCK |
| 文件： | 总20页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M41T0
SERIAL REAL-TIME CLOCK
FEATURES SUMMARY
■
2.0 TO 5.5V CLOCK OPERATING VOLTAGE
Figure 1. 8-pin SOIC Packages
■
COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEARS, and
CENTURY
8
■
■
■
■
YEAR 2000 COMPLIANT
1
I2C BUS COMPATIBLE (400kHz)
LOW OPERATING CURRENT OF 130µA
SO8 (M)
OPERATING TEMPERATURE OF –40 TO
85°C
■
■
AUTOMATIC LEAP YEAR COMPENSATION
SPECIAL SOFTWARE PROGRAMMABLE
OUTPUT
TSSOP8 3x3 (DS)
■
OSCILLATOR STOP DETECTION
July 2004
1/20
M41T0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 8-pin SOIC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. AC Testing Input/Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Stop data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/20
M41T0
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13.SO8 – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing16
Table 9. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 16
Figure 14.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 17
Table 10. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
M41T0
SUMMARY DESCRIPTION
The M41T0 TIMEKEEPER® RAM is a low power
Serial TIMEKEEPER with a built-in 32.768kHz os-
cillator (external crystal controlled). Eight registers
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a
two-line bi-directional bus. The built-in address
register is incremented automatically after each
WRITE or READ data byte.
The M41T0 is supplied in 8 lead Plastic Small Out-
line package.
Figure 2. Logic Diagram
Table 1. Signal Names
OSCI
OCSO
OUT
SDA
Oscillator Input
V
CC
Oscillator Output
Output Driver (Open Drain)
Serial Data Address Input / Output
Serial Clock
OSCO
SDA
OSCI
SCL
M41T0
SCL
OUT
(1)
No Function
Supply Voltage
Ground
NF
V
CC
V
V
SS
SS
AI07028
Note: 1. NF pin must be tied to V
.
SS
Figure 3. SOIC Connections
M41T0
OSCI
1
2
3
4
8
7
6
5
V
CC
OSCO
OUT
SCL
SDA
(1)
NF
V
SS
AI07029
Note: 1. NF pin must be tied to V
.
SS
4/20
M41T0
Figure 4. Block Diagram
1 Hz
OSCI
SECONDS
MINUTES
CENTURY/HOURS
DAY
OSCILLATOR
32.768 kHz
DIVIDER
OSCO
OUT
CONTROL
LOGIC
V
CC
V
SS
DATE
MONTH
SCL
SDA
SERIAL
BUS
INTERFACE
YEAR
ADDRESS
REGISTER
CONTROL
AI07030
5/20
M41T0
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
T
Storage Temperature (V Off, Oscillator Off)
–55 to 125
–0.3 to 7
STG
CC
V
CC
Supply Voltage
V
(1)
Lead Solder Temperature for 10 Seconds
260
°C
T
SLD
V
–0.3 to V + 0.3
Input or Output Voltages
Output Current
V
mA
W
IO
CC
I
O
20
1
P
Power Dissipation
D
Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 and 150
seconds).
6/20
M41T0
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
M41T0
2.0 to 5.5
–40 to 85
100
Unit
V
Supply Voltage (V
)
CC
Ambient Operating Temperature (T )
°C
pF
ns
V
A
Load Capacitance (C )
L
Input Rise and Fall Times
Input Pulse Voltages
≤ 5
0.2V to 0.8V
CC
CC
0.3V to 0.7V
Input and Output Timing Ref. Voltages
V
CC
CC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 5. AC Testing Input/Output Waveform
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI02568
Table 4. Capacitance
(1,2)
Symbol
Min
Max
7
Unit
Parameter
Input Capacitance (SCL)
C
pF
pF
ns
IN
(3)
Output Capacitance (SDA, OUT)
10
50
C
OUT
t
LP
Low-pass filter input time constant (SDA and SCL)
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
7/20
M41T0
Table 5. DC Characteristics
(1)
Sym
Parameter
Input Leakage Current
Output Leakage Current
Min
Typ
Max
Unit
Test Condition
I
0V ≤ V ≤ V
±1
±1
µA
µA
µA
µA
µA
µA
V
LI
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
3.0V
5.5V
3.0V
5.5V
35
130
0.9
55
I
Supply Current
Frequency (SCL) = 400kHz
CC1
200
1.2
All inputs = V – 0.2V
CC
(2)
Supply Current (Standby)
I
CC2
Frequency (SCL) = 0Hz
31
V
0.3 V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.3
IL
CC
V
CC
+
V
0.7 V
V
V
V
IH
CC
0.3
I
OL
= 3mA
0.4
0.4
V
OL
Output Low Voltage (Open
Drain)
I
= 10mA
OL
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
2. At 25°C.
Table 6. Crystal Electrical Characteristics
(1,2)
Symbol
Min
Typ
Max
Unit
Parameter
Resonant Frequency
fO
32.768
kHz
KΩ
pF
(3)
R
Series Resistance
Load Capacitance
S
60
C
L
12.5
Note: 1. These values are externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-
hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kou-
hou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T0. Circuit board layout considerations for the 32.768kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
3. R = 40kΩ when V ≤ 2.5V.
S
CC
8/20
M41T0
OPERATION
The M41T0 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 8 bytes contained in the device
can then be accessed sequentially in the following
order:
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
1. Seconds Register
2. Minutes Register
3. Century/Hours Register
4. Day Register
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
5. Date Register
By definition, a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The de-
vices that are controlled by the master are called
“slaves”.
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver, whereas
the master generates an extra acknowledge relat-
ed clock pulse.
6. Month Register
7. Years Register
8. Control Register
2-Wire Bus Characteristics
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock sig-
nals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High. Changes
in the data line while the clock line is High will be
interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
9/20
M41T0
Figure 6. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 7. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
1
2
8
9
MASTER
DATA OUTPUT
MSB
LSB
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
AI00601
Figure 8. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
Note: P = STOP and S = START
10/20
M41T0
Table 7. AC Characteristics
Symbol
(1)
Min
0
Typ
Max
Unit
kHz
µs
Parameter
f
SCL Clock Frequency
Clock Low Period
400
SCL
t
1.3
600
LOW
t
Clock High Period
ns
HIGH
t
SDA and SCL Rise Time
SDA and SCL Fall Time
300
300
ns
R
t
ns
F
START Condition Hold Time
(after this period the first clock pulse is generated)
t
600
600
ns
ns
HD:STA
START Condition Setup Time
(only relevant for a repeated start condition)
t
t
SU:STA
Data Setup Time
100
0
ns
µs
ns
µs
SU:DAT
(2)
Data Hold Time
t
HD:DAT
t
STOP Condition Setup Time
Time the bus must be free before a new transmission can start
600
1.3
SU:STO
t
BUF
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
11/20
M41T0
READ Mode
In this mode, the master reads the M41T0 slave
after setting the slave address (see Figure 9.). Fol-
lowing the WRITE Mode Control Bit (R/W = 0) and
the Acknowledge Bit, the word address An is writ-
ten to the on-chip address pointer. Next the
START condition and slave address are repeated,
followed by the READ Mode Control Bit (R/W = 1).
At this point, the master transmitter becomes the
master receiver. The data byte which was ad-
dressed will be transmitted and the master receiv-
er will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Bit. The
M41T0 slave transmitter will now place the data
byte at address An+1 on the bus. The master re-
ceiver reads and acknowledges the new byte and
An alternate READ Mode may also be implement-
ed, whereby the master reads the M41T0 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 11., page 13).
WRITE Mode
In this mode the master transmitter transmits to
the M41T0 slave receiver. Bus protocol is shown
in Figure 12., page 13. Following the START con-
dition and slave address, a logic '0' (R/W = 0) is
placed on the bus and indicates to the addressed
device that word address An will follow and is to be
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next memory location within the RAM on the
reception of an acknowledge clock. The M41T0
slave receiver will send an acknowledge clock to
the master transmitter after it has received the
slave address and again after it has received the
word address and each data byte (see Figure 9.).
the address pointer is incremented to An+2
.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
Figure 9. Slave Address Location
R/W
START
SLAVE ADDRESS
A
1
1
0
1
0
0
0
AI00602
12/20
M41T0
Figure 10. READ Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (An)
SDA LINE
S
S
DATA n
DATA n+1
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+X
P
AI00899
Figure 11. Alternate READ Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
Figure 12. WRITE Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (An)
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00591
13/20
M41T0
CLOCK OPERATION
The M41T0 is driven by a quartz controlled oscilla-
tor with a nominal frequency of 32.768kHz. The
accuracy of the Real-Time Clock depends on the
frequency of the quartz crystal that is used as the
time-base for the RTC. The M41T0 is tested to
meet ± 35 ppm with nominal crystal. The eight-
byte Clock Register (see Table 8., page 15) is
used to both set the clock and to read the date and
time from the clock, in a binary coded decimal for-
mat. Seconds, Minutes, and Hours are contained
within the first three registers. Bits D6 and D7 of
Clock Register 2 (Hours Register) contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to tog-
gle, either from '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0', CB will not toggle. Bits D0
through D2 of Register 3 contain the Day (day of
week). Registers 4, 5 and 6 contain the Date (day
of month), Month and Years. The final register is
the Control Register. Bit D7 of Register 0 contains
the STOP Bit (ST). Setting this bit to a '1' will cause
the oscillator to stop. If the device is expected to
spend a significant amount of time on the shelf, the
oscillator may be stopped to reduce current drain.
When reset to a '0' the oscillator restarts within
four seconds (typically one second).
Note: This 250ms delay affects only the clock reg-
ister update and does not alter the actual clock
time.
Output Driver Pin
The OUT pin is an output driver that reflects the
contents of D7 of the Control Register. In other
words, when D7 of location 7 is a '0' then the OUT
pin will be driven low.
Note: The OUT pin is open drain which requires
an external pull-up resistor.
Oscillator Stop Detection
If the Oscillator Fail (OF) Bit is internally set to a '1,'
this indicates that the oscillator has either stopped,
or was stopped for some period of time and can be
used to judge the validity of the clock and date da-
ta. This bit will be set to '1' any time the oscillator
stops. The following conditions can cause the OF
Bit to be set:
– The first time power is applied (defaults to a '1'
on power-up).
– The voltage present on VCC is insufficient to
support oscillation.
– The ST Bit is set to '1.'
– External interference or removal of the crystal.
This bit will remain set to '1' until written to logic '0.'
The seven clock registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 7) may be accessed inde-
pendently. Provision has been made to assure
that a clock update does not occur while any of the
seven clock addresses are being read. If a clock
address is being read, an update of the clock reg-
isters will be delayed by 250ms to allow the READ
to be completed before the update occurs. This
will prevent a transition of data during the READ.
The oscillator must start and have run for at least
4 seconds before attempting to reset the OF Bit to
'0.' This function operates both under normal pow-
er and in battery back-up.
Initial Power-on Defaults
Upon initial application of power to the device, the
OUT Bit and OF Bit will be set to a '1,' while the ST
Bit will be set to '0.' All other Register bits will ini-
tially power-on in a random state.
14/20
M41T0
Table 8. Register Map
Address
Data
Function/Range
BCD Format
D7
ST
OF
D6
D5
D4
D3
D2
D1
D0
0
1
10 Seconds
10 Minutes
Seconds
Seconds
Minutes
00-59
00-59
Minutes
Hours
(1)
2
3
4
5
6
7
CB
X
10 Hours
Century/Hours 0-1/00-23
CEB
X
X
X
X
X
X
X
Day
Day
Date
01-07
01-31
01-12
00-99
X
X
10 Date
Date
Month
Years
X
X
10 M.
X
Month
Year
10 Years
OUT
0
X
X
X
Control
Keys: ST = STOP Bit
OUT = Output level
X = Don’t care
CEB = Century Enable Bit
CB = Century Bit
OF = Oscillator Fail Bit
0 = Must be set to '0.'
Note: 1. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set).
When CEB is set to '0', CB will not toggle.
15/20
M41T0
PACKAGE MECHANICAL INFORMATION
Figure 13. SO8 – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing
h x 45˚
A2
A
C
B
ddd
e
D
8
1
E
H
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 9. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min
1.35
0.10
0.33
0.19
4.80
–
inches
Min
Symb
Typ
–
Max
1.75
0.25
0.51
0.25
5.00
0.10
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.004
0.157
–
A
A1
B
–
0.053
0.004
0.013
0.007
0.189
–
–
–
–
–
C
–
–
D
–
–
ddd
E
–
–
–
3.80
–
–
0.150
–
e
1.27
–
0.050
H
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
–
–
–
–
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
h
–
L
–
α
–
N
8
8
16/20
M41T0
Figure 14. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline
D
8
1
5
4
c
E1
E
α
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 10. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm
Min
–
inches
Min
Symb
Typ
–
Max
1.10
0.15
0.95
0.40
0.23
0.10
3.10
–
Typ
–
Max
A
A1
A2
b
–
0.043
0.006
0.037
0.016
0.009
0.004
0.122
–
–
0.05
0.75
0.25
0.13
–
–
0.002
0.030
0.010
0.005
–
0.85
–
0.034
–
c
–
–
CP
D
–
–
3.00
0.65
4.90
3.00
0.55
0.95
–
2.90
–
0.118
0.026
0.193
0.118
0.022
0.037
–
0.114
–
e
E
4.65
2.90
0.40
–
5.15
3.10
0.70
–
0.183
0.114
0.0160.028
–
0.203
0.122
0.030
–
E1
L
L1
α
0°
6°
0°
6°
N
8
8
17/20
M41T0
PART NUMBERING
Table 11. Ordering Information Scheme
Example:
M41T
0
M
6
T
Device Type
M41T
Supply Voltage and Write Protect Voltage
0 = V
= 2.0 to 5.5V
CC
Package
M = SO8 (150mils width)
DS = TSSOP8
Temperature Range
6 = –40 to 85°C
Shipping Method
blank = Tubes (Not for New Design - Use E)
®
E = Lead-Free Package (ECO PACK ), Tubes
®
F = Lead-Free Package (ECO PACK ), Tape & Reel
T = Tape & Reel (Not for New Design - Use F)
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
18/20
M41T0
REVISION HISTORY
Table 12. Document Revision History
Date
Rev. #
Revision Details
February 2003
1.0
First Issue
Add Pb-Free information (Table 2., Table 11.); update package information (Figure 1.,
Figure 14.; Table 11.)
18-Feb-03
1.1
01-Apr-03
10-Apr-03
30-Oct-03
1.2
1.3
1.4
Fix package outline and data (Figure 1., Figure 14., Table 10., Table 11.)
Revert to previous package (Figure 1., Figure 14., Table 10., Table 11.)
Remove footnote (Table 2.)
Shipping Method options updated and Note 1 removed from Table 11., Ordering
Information Scheme. Datasheet put in new template.
30-Jun-2004
23-Jul-2004
2.0
3.0
Content corrected from M41T80 to M41T0.
19/20
M41T0
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
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20/20
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