LNBP10L [STMICROELECTRONICS]
500 mA guaranteed output current;
| 型号： | LNBP10L |
| 厂家： | 
ST |
| 描述： | 500 mA guaranteed output current |
| 文件： | 总21页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LNBP8L - LNBP9L
LNBP10L - LNBP11L
LNB supply and control voltage regulator
Preliminary data
Features
■ Simplest integrated solution for LNB remote
supply and control
■ 500 mA guaranteed output current
■ Dual input supply for reducing power
dissipation (DFN package)
■ 3-state function to enable/disable and select
IPPAK
DFN8 (5 x 6 mm)
the output voltage level through a single pin
■ Fast oscillator startup for DiSEq™ encoding
(LNBP9L/11L versions)
supplied at 22 V (min.). Additionally, the
LNBP10L/11L versions have the LLC pin to
increment the selected output voltage value by 1
V (typ.) to compensate for the excess voltage
drop along the coaxial cable (LLC pin HIGH).
■ External 22 kHz modulation input pin
(LNBP8L/10L versions)
■ Cable length compensation, LLC pin
(LNBP10L, LNBP11L versions)
An analog 22 kHz modulation input pin (EXTM) is
available in the LNBP8L and LNBP10L versions.
An appropriate DC blocking capacitor must be
used to couple the modulating signal source to
the EXTM pin. The LNBP10L/11L versions are
also equipped with over-current dynamic
■ Short-circuit and over-temperature protection
■ LNB overload and short-circuit dynamic
protection (LNBP10L, LNBP11L versions)
■ Available in DFN8 (5 x 6 mm) and IPPAK
packages
protection: as soon as an overload is detected the
output is shut down for the time T
determined by the capacitor connected between
the CEXT pin and GND. After the time has
which is
OFF,
Description
Intended for analog and digital satellite receivers,
the LNBP is a monolithic linear voltage regulator,
assembled in the DFN8 5x6 and IPPAK packages,
specifically designed to provide the powering
voltages and the interfacing signals to the LNB
down-converter. The regulator output can be logic
controlled for 13 V or 18 V (typ.) by means of the
EN/VSEL 3-state pin for remotely controlling the
LNB. When the IC is powered and put in standby
(EN/VSEL pin at high impedance), the regulator
output is disabled. In order to reduce power
dissipation, the LNBP10L/11L versions (on DFN
elapsed, the output is resumed for a time T
=
ON
(1/12)*T
(typ.). If the overload is still present,
OFF
the protection circuit will cycle again through T
OFF
and T until the overload is removed. A typical
ON
T
+T
value is 1100 ms when a 4.7 µF
ON OFF
external capacitor is used on the C . This
dynamic operation can greatly reduce the power
dissipation in short-circuit condition, while
EXT
ensuring excellent power-on startup even with
highly capacitive loads on the LNB outputs.
The device is packaged in the IPPAK for through-
hole mounting and in the DFN8 5x6 for surface
mounting. Both package solutions are offered in
two versions: with ten pins (LNBP9L/11L) to use
with the integrated 22 kHz tone generator, or with
the EXTM pin (LNBP8L/10L) to use external 22
kHz sources. All versions have built-in thermal
protection to prevent overheating damage.
package) feature 2 supply inputs: V
and V
.
CC1
CC2
These pins must be powered, respectively, at 15
V (min.) and 22 V (min.), and an internal switch
will automatically select the appropriate supply
voltage according to the selected output voltage.
The LNBP8L/9L versions (in the IPPAK package)
have only one supply input pin, which must be
November 2008
Rev 1
1/21
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change
without notice.
www.st.com
21
Contents
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Contents
1
2
3
4
5
6
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Detailed description and application hints . . . . . . . . . . . . . . . . . . . . . . . 9
6.1
6.2
6.3
Input voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Single supply for the DFN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IPPAK mounting and thermal considerations . . . . . . . . . . . . . . . . . . . . . . 11
7
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8
9
10
2/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Diagram
1
Diagram
Figure 1.
Block diagram
VCC1
VCC2
RSENSE
TRISTATE ENABLE &
VOUT SELECTION
EN/VSEL
LLC
VOLTAGE
REFERENCE
OUTPUT
DYNAMIC
CURRENT LIMIT
CEXT
TEN
THERMAL
PROTECTION
22kKHHzz
OSCILLATOR
EXTM
LNBP8L/9L/10L/11L
GND
3/21
Pin configuration
LNBP8L - LNBP9L - LNBP10L - LNBP11L
2
Pin configuration
Figure 2.
Pin connections (top view for IPPAK, bottom view for DFN8)
DFN8 (5x6 mm)
IPPAK
Table 1.
Pin description
Pin n°
(IPPAK)
LNBP8/9L
Pin n° (DFN)
LNBP10/11L
Name
Pin function
Supply input 1: 15 V to 25 V supply. For DFN package it is
automatically selected when VOUT = 13 V. For IPPAK package
VCC1 and VCC2 are internally connected together to pin 1 to be
supplied at 22 V min.
VCC1
(not available for
IPPAK)
1
2
-
Supply input 2: 22 V to 25 V supply. For DFN package it is
automatically selected when VOUT = 18 V. For IPPAK package
VCC1 and VCC2 are internally connected together to the pin 1 to be
supplied at 22 V min.
VCC2
(VCC pin for
IPPAK)
1
Output: regulator output. It is 13 V typ when EN/VSEL LOW and
18 V typ when EN/VSEL HIGH.
3
2
OUTPUT
GROUND
4, ePAD
3, ePAD
GROUND
Enable and output voltage selection 3-state pin: logic control
input 3-state pin for the remote controlling of the LNB; if LOW
VOUT = 13 V, when HIGH VOUT = 18 V, if left at high impedance the
IC is set in shut down mode (VOUT = 0 V)
6
5
4
5
EN/VSEL
Tone enable (LNBP9-11): logic control input to enable internal
tone generator.
External modulation (LNBP8-10): Needs DC decoupling to the
AC source. If not used can be left floating.
EXTM/TEN
8
7
NA
NA
LLC
LLC: logic control input to add 1 V typ.
CEXT: timing capacitor used by the dynamic overload protection.
Typical application is 4.7 µF for a 1100 ms cycle
CEXT
4/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Maximum ratings
3
Maximum ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC1, VCC2
Input voltages
-0.3 to 28
-0.3 to 25
-0.3 to 25
V
V
V
VCC1-OUTPUT VCC1 voltage with respect to OUTPUT voltage (1)
VCC2-OUTPUT VCC2 voltage with respect to OUTPUT voltage (1)
EN/VSEL, TEN,
Logic input voltage
LLC
-0.3 to 7
V
EXTM
OUTPUT
TSTG
External modulation input voltage
-0.3 to 1
V
V
Output voltage
-0.3 to 25
Storage temperature range
-50 to 150
°C
kV
ESD rating with human body model (HBM) for all pins except 1, 2, 6
ESD rating with human body model (HBM) for pins 1, 2, 6
ESD rating with human body model (HBM) for all pins except 1, 4
ESD rating with human body model (HBM) for pins 1, 4
2
ESD
DFN package
1.5
2
kV
ESD
IPPAK package
1.5
1. Exposure beyond the VCC1 and VCC2 with respect to OUTPUT absolute-maximum-rated voltages during OUTPUT pin
overload or short-circuit to GROUND may cause permanent damage to the device.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to network ground terminal unless
otherwise stated.
Table 3.
Operating ratings
Symbol
Parameter
Value
Unit
TJ
Operating junction temperature range
Input voltage
0 to 125
15 to 25
22 to 25
°C
V
VCC1
VCC2
Input voltage
V
Table 4.
Thermal data
Symbol
Parameter
IPPAK
DFN8
Unit
35
RthJA
RthJC
Thermal resistance junction-ambient
Thermal resistance junction-case
°C/W
°C/W
(mounted on PCB 2s2p)
8
5/21
Electrical characteristics
LNBP8L - LNBP9L - LNBP10L - LNBP11L
4
Electrical characteristics
Table 5.
Electrical characteristics
(1)
Refer to the typical application circuits in Figure 3 and Figure 4, V
= 16 V, V
= 23 V , EN/VSEL =
CC2
CC1
LOW, TEN = LLC = LOW, EXTM = FLOATING, I
= 50 mA, T = 0 °C to 85 °C, unless otherwise stated.
OUT
J
Typical values are referred to T = 25 °C
J
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
IOUT = 500 mA, TEN=HIGH,
EN/VSEL=LOW, LLC=LOW
15
25
VCC1
VCC supply input 1 (1)
V
I
OUT = 500 mA, TEN=HIGH,
16
22
23
25
25
25
EN/VSEL=LOW, LLC= HIGH
IOUT = 500 mA, TONE=HIGH,
EN/VSEL=HIGH, LLC=LOW
VCC2
VCC supply input 2 (1)
V
IOUT = 500 mA, TONE=HIGH,
EN/VSEL=HIGH, LLC= HIGH
IOUT = 500 mA, EN/VSEL=LOW
IOUT = 500 mA, EN/VSEL=HIGH
12.5 13.25
14
19
V
V
17
18
14.25
19
VOUT
Output voltage
IOUT = 500 mA, EN/VSEL=LOW,
LLC=HIGH (2)
V
V
IOUT = 500 mA, EN/VSEL=LLC=HIGH (2)
VCC1 from 15 V to 18 V, EN/VSEL=LOW
or HIGH
ΔVOUT
ΔVOUT
Line regulation (1)
Load regulation
5
40
mV
VCC1 = VCC2 = 22 V, IOUT from 50 mA to
500 mA, EN/VSEL=LOW or HIGH
50
150
mV
IMAX
FTONE
ATONE
DTONE
tr, tf
Output current limiting
Tone frequency
550
20
0.4
40
5
700
22
850
24
mA
kHz
VPP
%
TEN=High
TEN=High
TEN=High
TEN=High (3)
Tone amplitude
0.65
50
0.9
60
Tone duty cycle
Tone Rise and Fall Time
10
15
µs
Δ VOUT/Δ VEXTM, freq. from 10 kHz to 40
GEXTM
VEXTM
ZEXTM
VILT
External modulation Gain
4.5
5.5
6.5
kHz
External modulation input
voltage
AC Coupling
400
mVPP
Ω
External modulation
impedance
Freq. from 10 kHz to 40 kHz
EN/VSEL
400
1
Control input logic LOW
threshold for 3-state pin
0.8
1.8
1.2
2.2
V
Control input logic HIGH
threshold for 3-state pin
VIHT
EN/VSEL
2
V
3-state control pin input
current HIGH
IIHT
VIHT = 5 V, EN/VSEL
-400
µA
6/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Electrical characteristics
Table 5.
Electrical characteristics (continued)
(1)
Refer to the typical application circuits in Figure 3 and Figure 4, V
= 16 V, V
= 23 V , EN/VSEL =
CC2
CC1
LOW, TEN = LLC = LOW, EXTM = FLOATING, I
= 50 mA, T = 0 °C to 85 °C, unless otherwise stated.
OUT
J
Typical values are referred to T = 25 °C
J
Symbol
Parameter
Test conditions
ILT = 0 V, EN/VSEL
TEN, LLC
Min. Typ. Max.
Unit
3-state control pin input
current LOW
IILT
V
+180
µA
VIL
VIH
IIH
Control input logic LOW
0.8
V
V
Control input logic HIGH TEN, LLC
2.5
20
Control pins input current VIH = 5 V, TEN, LLC
µA
Output disabled EN/VSEL=High
impedance (floating)
1.7
3.7
2.4
6.3
mA
mA
ms
ICC
Supply current
Output enabled EN/VSEL=HIGH,
TEN=HIGH, IOUT = 500 mA
Dynamic overload
protection OFF time
TOFF
Output shorted, CEXT = 4.7 µF (2)
Output shorted, CEXT = 4.7 µF (2)
1000
Dynamic overload
protection ON time
TOFF
/12
TON
IOBK
ms
mA
°C
Output backward current Output forced to 21 V
6
Thermal shutdown
threshold
TSHDN
165
Thermal shutdown
hysteresis
ΔTSHDN
25
°C
1. For IPPAK package VCC1 and VCC2 are internally connected to the pin 1 (VCC) to be supplied in the range from 22 V up to
25 V
2. Only DFN package
3. Guaranteed by design
7/21
Typical application circuits
LNBP8L - LNBP9L - LNBP10L - LNBP11L
5
Typical application circuits
Figure 3.
Single input supply voltage solution for IPPAK package versions
D1
1N4001
LNB OUTPUT
23V
VCC
OUTPUT
C1
10µF
C2
220nF
LNBP8/9L
D2
C3
1N5818 100nF
EN/VSEL (Tristate)
MCU I/Os
EXTM or TEN
GND
Figure 4.
Dual input supply voltage solution for DFN8 (5 x 6 mm) package versions
D1 1N4001
16V
LNB OUTPUT
VCC1
OUTPUT
C1
10µF
C2
220nF
23V
D3 1N4001
C3
100nF
D2
1N5818
VCC2
LLC
LNBP10/11L
C4
10µF
C5
220nF
CEXT
C6
4.7µF
MCU I/Os
EN/VSEL (Tristate)
EXTM or TEN
GND
Figure 5.
Single input supply voltage solution for DFN8 (5 x 6 mm) package versions
D1
1N4001
R1
15 Ohm >3W
23V
LNB OUTPUT
VCC1
VCC2
OUTPUT
C1
10µF
C2
220nF
D2
C3
1N5818 100nF
C4
220nF
LNBP10/11L
LLC
CEXT
C5
4.7µF
MCU I/Os
EN/VSEL (Tristate )
EXTM or TEN
GND
Note:
In a single supply configuration with the DFN package, an R resistor in the 12-15 Ω range
1
is recommended to reduce device power dissipation during the 13 V output condition. The
resistor can be omitted, but the power dissipation will increase.
8/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Detailed description and application hints
6
Detailed description and application hints
The LNBPxx is made up of several functional blocks (see Figure 1 on page 3), as described
below:
1. The oscillator is activated by setting the ENT pin (enable tone) = H, and is factory-
trimmed at 22 kHz 2 kHz, eliminating the need to use external trimming. The rising
and falling edges are maintained in the 5 to 15 µs range (10 µs typ.), to avoid RF
pollution of the receiver. The duty cycle is 50% typ. It modulates the DC output with a
0.325 V typ. amplitude and 0 V average. The presence of this signal usually gives the
LNB information about the band to be received.
2. The 3-state enable & V
selection block, selects the two output voltages or sets the
OUT
IC to shutdown mode, depending on the voltage applied on the EN/VSEL pin.
When EN/VSEL is set high (EN/VSEL > 2.2 V), an 18 V output voltage is selected;
when the EN/VSEL is set low (EN/VSEL < 0.8 V), a 13 V output voltage is selected.
If the EN/VSEL pin is left floating (high impedance) or if the pin is set in a range from
1.2 V to 1.8 V (1.5 V typ.), the IC goes into shutdown mode and the output voltage will
be set to 0 V.
This feature changes the LNB polarization type. The LNB switches to horizontal or
vertical polarization depending on the supply voltage it gets from the receiver.
3. For the DFN package, in order to keep the power dissipation of the device as low as
possible, the input selector automatically selects V
; that is, the lowest input voltage,
CC1
when 13 V output is selected (i.e. EN/VSEL is low). If the 18 V output is selected (i.e.
EN/VSEL is high), the V input pin is selected. For example, power dissipation at
CC2
I
= 350 mA is:
OUT
P = (23 - 18) x 0.35 = 1.75 W
D
with V
= 23 V (voltage on the V
pin) and V
OUT
= 18 V, and
= 13 V
CC2
CC2
CC1
P = (16 - 13) x 0.35 = 1.05 W
D
with V
= 16 V (voltage on the V
pin) and V
OUT
CC1
For IPPAK package, V
and V
are internally connected and must be supplied from a
CC1
CC2
single input voltage line (22 V min.) to the V pin. In this case the worst case power
CC
dissipation is 13 V output. For example: at I
= 350 mA and V = 23 V (voltage on the
OUT
CC
V
pin):
CC
P = (23 - 13) x 0.35 = 3.5 W
D
4. The line length compensation function is useful when the antenna is connected to the
receiver by a long coaxial cable that adds a considerable DC voltage drop. When the
LCC pin is H, the output voltage selected is increased by about 1 V. This function is
available for the DFN package only.
5. The reference drives all the internal blocks that require a high-precision thermally
compensated voltage source.
6. The LNBPxx has two different protection features, and both turn off the outputs. The
first one protects against overheating (i.e. for T ≥ 150 °C), and the second against
J
overload conditions (i.e. for output current > 550 mA) or short-circuit:
a) In the thermal protection case the output is disabled until the chip temperature has
fallen below 140 °C typ. and the LNBPxx output is restored.
b) The overload protection case occurs when output current request is ≥ 500 mA. For
the DFN package only, the IC features dynamic overload and short-circuit
9/21
Detailed description and application hints
LNBP8L - LNBP9L - LNBP10L - LNBP11L
protection. When an overload occurs the device limits the output current for the
time T depending on the C value (see Figure 24 and Figure 25). When T
ON
ON
EXT
has elapsed, the output goes low for a time of T
= 12 x T . This keeps the
OFF
ON
power dissipated by the device low in overload conditions, and avoids the need for
an oversized heat sink in this condition. For the IPPAK package, when the
overload or the short-circuit occurs, the device clamps the output current in a
range between 550 mA and 850 mA.
7. EXTM modulates the V
by means of a capacitor connected in series (see Figure 6).
OUT
The following equation is used to calculate the peak-to-peak voltage of V
:
OUT
V
(AC) = V
(AC) x G
EXTM EXTM
OUT
where V
(AC) and V
(AC) are, respectively, the peak-to-peak voltage of V
and
OUT
EXTM
OUT
V
. G
is the external modulation gain.
EXTM
EXTM
Figure 6.
EXTM application circuit
D1
1N4001
LNB OUTPUT
23V
VCC
OUTPUT
C1
10µF
C2
220nF
LNBP8/9L
D2
C3
1N5818 100nF
EN/VSEL (Tristate)
Vextm
EXTM
GND
C4
1µF
6.1
Input voltage protection
In some cases two or more receivers share the same coaxial cable, rendering their outputs
hard-paralleled, so the same voltage is present at the outputs of the receivers. If a receiver
is not disconnected at the mains, a current will flow from the OUTPUT to the V
or V
CC1
CC2
pins, depending the EN/VSEL pin setting. To avoid this, two diodes (only one for the IPPAK
package) in series are recommended at input pins V and V (see Figure 3). These
CC1
CC2
diodes do not cause a change at V
, but only a voltage drop, which can be minimized by
OUT
using Schottky diodes. Diodes used in Figure 4 and Figure 5 must withstand a continuous
current of almost 1 A and a breakdown voltage of 30 V (suggested type is 1N4001 or
BYV10-30). Be aware that the minimum voltage needed at the V pins must be respected,
CC
considering the voltage drop across the input diodes).
10/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Detailed description and application hints
6.2
Single supply for the DFN package
If only one power supply source is available, the V
and V
pins can be powered by the
CC2
CC1
same power source without affecting the performance of other circuits, at the cost of higher
power losses in the device and higher heat sink surface. Also, in order to reduce the power
dissipation in the device, an appropriate-value resistor can be inserted in series with the
V
line (see Figure 5). This resistor must be dimensioned considering that the minimum
CC1
voltage on the V
pin must be >= 16 V (15 V if LLC is not used).
CC1
For example, with I
= 500 mA:
R
OUT
-
-
(23 Vf 16)
500 x 10-3
≅
≤
12 Ω
Where V is the forward voltage of the input diode D1 (see Figure 5).
f
Power dissipated in this resistor is:
2
3
-
2
=
=
=
PD R* IOUT
12* 500*10
3 W
pins using 220 nF electrolytic capacitors.
CC2
(
)
It is recommended to bypass the V and V
CC1
6.3
IPPAK mounting and thermal considerations
First, it should be noted that the tab is directly connected to the GND pin, so care must be
taken when the device is connected to a heat-sink. If the heat sink is at a different voltage
than the ground, an electrical insulator must be added between the tab and the heat sink at
the cost of an increase in the thermal resistance. For better thermal performance, an
isolated heat sink or connection to ground is recommended.
11/21
Detailed description and application hints
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Several clips can be used depending on the heat sink type:
●
●
●
Saddle clips (Figure 7) for slim heat sinks
U-clips (Figure 8) for thick heat sinks
Dedicated clips for special shaped heat sinks
Figure 7.
IPPAK mounted with a saddle clip.
Figure 8.
IPPAK mounted with a U-clip.
Note that the thickness of the IPPAK package (2.3 +/- 0.1 mm) is similar to that of the SOT-
32 and SOT-82 (2.55 +/- 0.15 mm). The same clips can also be used for these packages.
The junction-to-ambient thermal resistance for the IPPAK can be calculated as follows:
RTH-JA = RTH-JC + RTH-CH + RTH-HA
where: RTH-JC is the junction-to-case thermal resistance of the IPPAK (see Table 4: Thermal
data), RTH-CH is the case-to-heat sink thermal resistance and the RTH-HA is the heat sink-to-
air thermal resistance.
12/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Typical performance characteristics
7
Typical performance characteristics
(Refer to the typical application circuit, TJ from 0 to 85 °C. Typical values are referred to
TJ = 25 °C).
Figure 9.
Output voltage vs. temperature
Figure 10. Output voltage vs. temperature
14
14
VCC1 = 15 V
VCC2 = 23 V
IOUT = 50 mA
VOUT = 13 V
VCC1 = 15 V
VCC2 = 23 V
IOUT = 500 mA
13.8
13.6
13.4
13.2
13
13.8
13.6
13.4
13.2
13
VOUT = 13 V
12.8
12.6
12.4
12.2
12
12.8
12.6
12.4
12.2
12
EN/VSEL=L
TEN=L, LLC=L
EN/VSEL=L
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
H = Logic High = 5 V
L = Logic Low = 0 V
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
T [°C]
T [°C]
Figure 11. Output voltage vs. temperature
Figure 12. Output voltage vs. temperature
19
19
VCC1 = 15 V
VCC1 = 15 V
VCC2 = 23 V
18.8
18.8
VCC2 = 23 V
IOUT = 50 mA
VOUT = 18 V
IOUT = 500 mA
VOUT = 18 V
18.6
18.4
18.2
18
18.6
18.4
18.2
18
17.8
17.6
17.4
17.2
17
17.8
17.6
17.4
17.2
17
EN/VSEL=H
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
EN/VSEL=H
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
T [°C]
T [°C]
Figure 13. Line regulation vs. temperature
Figure 14. Load regulation vs. temperature
250
200
150
100
50
40
30
20
VCC1 = 15 V
VCC2 = 23 V
IOUT = from 50 mA to 500 mA
VOUT = 13 V
VCC1 = 16 V to 25 V
V
CC2 = 23 V
OUT = 50 mA
OUT = 13 V
I
V
50
0
10
0
-50
-100
-150
-200
-250
-10
-20
-30
-40
-50
EN/VSEL=L
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
EN/VSEL=L
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
T [°C]
T [°C]
13/21
Typical performance characteristics
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Figure 15. Load regulation vs. temperature
Figure 16. Output current limiting vs.
temperature
900
250
VCC1 = 15 V
850
VCC1 = 15 V
VCC2 = 23 V
V
CC2 = 23 V
200
800
750
700
650
600
550
500
450
400
VOUT = 13 V
I
OUT = from 50 mA to 500 mA
150
100
50
VOUT = 18 V
0
-50
-100
-150
EN/VSEL=H
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
EN/VSEL=L
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
T [°C]
T [°C]
Figure 17. Output current limiting vs.
temperature
Figure 18. Dynamic overload protection ON
time vs. temperature
900
210
VCC1 = 15 V
VCC2 = 23 V
850
VCC1 = 16 V
190
VCC2 = 23 V
800
750
700
650
600
550
500
450
400
VOUT = 18 V
170
150
130
110
90
Cext = 4.7 µF
OUT = 13 V
V
70
50
EN/VSEL=L
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
EN/VSEL=H
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
30
10
-10
0
10
20
30
40
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
T [°C]
T [°C]
Figure 19. Dynamic overload protection OFF Figure 20. Tone enable
time vs. temperature
VCC1 = 23 V
V
CC2 = 23 V
I
OUT = 50 mA
1200
1100
1000
900
VOUT = 13 V
VCC1 = 15 V
VCC2 = 23 V
Cext = 4.7 µF
EN/VSEL=L
TEN=H, LLC=L
VOUT = 13 V
800
700
EN/VSEL=L
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
600
-10
0
10
20
30
40
50
60
70
80
90
T [°C]
14/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Figure 21. Tone disable
Typical performance characteristics
Figure 22. External modulation gain vs.
temperature
VCC1 = 23 V
VCC2 = 23 V
IOUT = 50 mA
VOUT = 13 V
8
7.5
7
6.5
6
5.5
5
VCC1 = 15 V
VCC2 = 23 V
IOUT = 50 mA
EN/VSEL=L
TEN=H, LLC=L
VOUT = 13 V
f = 22 kHz
4.5
4
3.5
3
2.5
2
EN/VSEL=L
TEN=L, LLC=L
H = Logic High = 5 V
L = Logic Low = 0 V
-10
0
10
20
30
40
50
60
70
80
90
T [°C]
Figure 23. External modulation gain vs.
frequency
Figure 24. T time vs. C
ON
EXT
400
350
300
250
200
150
100
50
7
VCC1 = 15 V
6.5
6
VCC2 = 23 V
IOUT = 50 mA
VOUT = 13 V
5.5
5
4.5
4
H = Logic High = 5 V
L = Logic Low = 0 V
EN/VSEL=L
TEN=L, LLC=L
3.5
1000
0
10000
F [Hz]
100000
0
5
10
15
CAPACITOR CEXT [µF]
Figure 25. T
time vs. C
OFF
EXT
4000
3500
3000
2500
2000
1500
1000
500
0
0
5
10
15
CAPACITOR CEXT [µF]
15/21
Package mechanical data
LNBP8L - LNBP9L - LNBP10L - LNBP11L
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 26. IPPAK package dimensions
0075222
16/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Package mechanical data
Table 6.
IPPAK mechanical data
Dim.
(mm.)
Typ.
Min.
Max.
A
A1
B
2.20
0.90
0.40
5.20
2.40
1.10
0.60
5.40
0.70
B2
B3
B5
B6
C
0.30
1
0.45
0.48
6
0.60
0.60
6.20
6.60
C2
D
E
6.40
e
1.27
G
4.90
2.38
15.90
9
5.25
2.70
16.30
9.40
1.20
1
G1
H
L
L1
L2
V1
0.80
0.80
10°
Note:
1
2
Controlling dimensions: millimeter.
Burrs larger than 0.25 mm are not allowed on the upper surface of the dissipater (FRONT)
on the lower surface (REAR) the maximum allowed is: 0.05 mm.
3
4
5
6
7
8
The side of the dissipater to be connected to the external dissipater must be flat within 30 µ
The leads size is comprehensive of the thickness of the leads finishing material.
Package outline exclusive of any mold flashes dimensions and metal burrs.
Max resin gate protrusion: 0.5 mm.
Max resin protrusion: 0.25 mm.
The maximum bent leads allowed, in any direction, is: # 2° if the devices are packed in tube.
17/21
Package mechanical data
LNBP8L - LNBP9L - LNBP10L - LNBP11L
DFN8 (5x6 mm) mechanical data
mm.
Typ.
inch.
Typ.
Dim.
Min.
Max.
Min.
Max.
A
A1
A3
b
0.80
0.90
0.02
0.20
0.40
5.00
4.2
1.00
0.05
0.032
0.035
0.001
0.008
0.016
0.197
0.165
0.236
0.142
0.049
0.078
0.086
0.015
0.0086
0.039
0.002
0.35
4.15
3.55
0.47
4.25
3.65
0.014
0.163
0.140
0.018
0.167
0.144
D
D2
E
6.00
3.6
E2
e
1.27
1.99
2.20
0.40
0.219
F
G
H
I
L
0.70
0.90
0.028
0.035
7286463/C
18/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
Ordering information
9
Ordering information
Table 7.
Order codes
Order codes
Part numbers
Packing
DFN8 (5x6 mm)
IPPAK
LNBP8L
LNBP9L
LNBP10L
LNBP11L
LNBP8LIT
LNBP9LIT
Tape and reel
Tape and reel
Tape and reel
Tape and reel
LNBP10LPUR
LNBP11LPUR
19/21
Revision history
LNBP8L - LNBP9L - LNBP10L - LNBP11L
10
Revision history
Table 8.
Document revision history
Revision
Date
11-Nov-2008
Changes
1
Initial release.
20/21
LNBP8L - LNBP9L - LNBP10L - LNBP11L
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21/21
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