LNBP11SP-TR [STMICROELECTRONICS]
LNBP supply and control voltage regulator (parallel interface); LNBP供应和控制稳压器（并行接口）
| 型号： | LNBP11SP-TR |
| 厂家： | 
ST |
| 描述： | LNBP supply and control voltage regulator (parallel interface) |
| 文件： | 总24页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LNBP20 / LNBP1X series
LNBP supply and control voltage regulator (parallel interface)
Feature summary
■ Complete interface for two LNBs remote supply
and control
■ LNB selection and stand-by function
10
■ Built-in tone oscillator factory trimmed at
22KHz
1
TM
■ Fast oscillator start-up facilitates DiSEqC
encoding
PowerSO-20
PowerSO-10
■ Two supply inputs for lowest dissipation
■ Bypass function for slave operation
■ LNB short circuit protection and diagnostic
■ Auxiliary modulation input extends flexibility
■ Cable length compensation
via the coaxial cable. Since most satellite
■ Internal over temperature protection
■ Backward current protection
receivers have two antenna ports, the output
voltage of the regulator is available at one of two
logic-selectable output pins (LNBA, LNBB). When
the IC is powered and put in Stand-by (EN pin
LOW), both regulator outputs are disabled to
allow the antenna downconverters to be
supplied/controlled by others satellite receivers
sharing the same coaxial lines. In this occurrence
the device will limit at 3 mA (max) the backward
current that could flow from LNBA and LNBB
output pins to GND. (See continuous description).
Description
Intended for analog and digital satellite receivers,
the LNBP is a monolithic linear voltage regulator,
assembled in PowerSO-20 and PowerSO-10,
specifically designed to provide the powering
voltages and the interfacing signals to the LNB
downconverter situated in the antenna
Order codes
Package
Part number
PowerSO-20
PowerSO-10
LNBP10
LNBP11
LNBP12
LNBP13
LNBP14
LNBP15
LNBP16
LNBP10SP-TR
LNBP11SP-TR
LNBP12SP-TR
LNBP13SP-TR
LNBP14SP-TR
LNBP15SP-TR
LNBP16SP-TR
LNBP20
LNBP20PD-TR
Rev. 10
May 2007
1/24
www.st.com
24
LNBP20 / LNBP1X series
Contents
1
2
3
4
5
6
7
8
9
Description (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24
LNBP20 / LNBP1X series
Description (continued)
1
Description (continued)
For slave operation in single dish, dual receiver systems, the bypass function is
implemented by an electronic switch between the Master Input pin (MI) and the LNBA pin,
thus leaving all LNB powering and control functions to the Master Receiver. This electronic
switch is closed when the device is powered and EN pin is LOW.
The regulator outputs can be logic controlled to be 13 or 18 V (typ.) by mean of the VSEL
pin for remote controlling of LNBs. Additionally, it is possible to increment by 1V (typ.) the
selected voltage value to compensate the excess voltage drop along the coaxial cable (LLC
pin HIGH).
In order to reduce the power dissipation of the device when the lowest output voltage is
selected, the regulator has two Supply Input pins V
and V
. They must be powered
CC1
CC2
respectively at 16V (min) and 23V (min), and an internal switch automatically will select the
suitable supply pin according to the selected output voltage. If adequate heatsink is
provided and higher power losses are acceptable, both supply pins can be powered by the
same 23V source without affecting any other circuit performance.
The ENT (Tone Enable) pin activates the internal oscillator so that the DC output is
modulated by a ±0.3 V, 22KHz (typ.) square wave. This internal oscillator is factory trimmed
within a tolerance of ±2KHz, thus no further adjustments neither external components are
required.
A burst coding of the 22KHz tone can be accomplished thanks to the fast response of the
ENT input and the prompt oscillator start-up. This helps designers who want to implement
TM
(a)
the DiSEqC protocols
.
In order to improve design flexibility and to allow implementation of newcoming LNB remote
control standards, an analogic modulation input pin is available (EXTM). An appropriate DC
blocking capacitor must be used to couple the modulating signal source to the EXTM pin.
When external modulation is not used, the relevant pin can be left open.
Two pins are dedicated to the overcurrent protection/monitoring: CEXT and OLF. The
overcurrent protection circuit works dynamically: as soon as an overload is detected in
either LNB output, the output is shut-down for a time t determined by the capacitor
off
connected between CEXT and GND. Simultaneously the OLF pin, that is an open collector
diagnostic output flag, from HIGH IMPEDANCE state goes LOW.
After the time has elapsed, the output is resumed for a time t =1/15t (typ.) and OLF goes
on
off
in HIGH IMPEDANCE. If the overload is still present, the protection circuit will cycle again
through t and ton until the overload is removed. Typical t +t value is 1200ms when a
off
on off
4.7µF external capacitor is used.
This dynamic operation can greatly reduce the power dissipation in short circuit condition,
still ensuring excellent power-on start up even with highly capacitive loads on LNB outputs.
The device is packaged in PowerSO-20 for surface mounting. When a limited functionality in
a smaller package matches design needs, a range of cost-effective PowerSO-10 solutions
is also offered. All versions have built-in thermal protection against overheating damage.
a. External components are needed to comply to level 2.x and above (bidirectional) DiSEqCTM bus hardware
requirements. DiSEqCTM is a trademark or EUTELSAT.
3/24
Pin configuration
LNBP20 / LNBP1X series
2
Pin configuration
Figure 1.
Pin connections (top view)
PowerSO-20
PowerSO-10
Table 1.
SYMBOL
Pin Description
PIN NUMBER vs SALES TYPE (LNBP)
NAME
FUNCTION
20PD 10SP 11SP 12SP 13SP 14SP 15SP 16SP
15V to 25V supply. It is
automatically selected
when VOUT= 13 or 14V
Supply input
1
VCC1
2
3
1
2
1
2
1
2
1
2
1
2
1
2
22V to 25V supply. It is
automatically selected
when VOUT= 18 or 19V
Supply input
2
VCC2
2
3
See truth table voltage
and port selection. In
stand-by mode this port
is powered by the MI pin
via the internal bypass
switch
LNBA
Output port
4
5
3
4
3
4
3
4
3
4
3
4
3
4
Output
voltage
Logic control input: see
selection:13 truth table
or 18V (typ)
VSEL
4
Logic control input: see
truth table
EN
Port enable
6
7
5
9
5
5
5
5
5
5
Logic control input: see
truth table
OSEL
Port selection
NA
NA
NA
NA
NA
NA
1
Circuit ground. It is
internally connected to
the die frame
10
11
20
GND
Ground
6
6
6
6
6
6
6
4/24
LNBP20 / LNBP1X series
Pin configuration
Table 1.
SYMBOL
Pin Description
NAME
PIN NUMBER vs SALES TYPE (LNBP)
20PD 10SP 11SP 12SP 13SP 14SP 15SP 16SP
FUNCTION
22KHz tone Logic control input: see
ENT
13
7
7
7
7
7
7
7
enable
truth table
Timing capacitor used by
the dynamic overload
protection. Typical
application is 4.7μF for a
1200ms cycle
External
capacitor
CEXT
14
8
8
8
8
8
8
8
External modulation
input. Needs DC
decoupling to the AC
source. if not used, can
be left open.
External
modulator
EXTM
LLC
15
16
NA
NA
NA
NA
NA
9
9
NA
9
9
9
Line length
compens.
(1V typ)
Logic control input: see
truth table
NA
NA
10
Logic output (open
collector). Normally in
HIGH IMPEDANCE,
goes LOW when current
or thermal overload
occurs
Over load
flag
OLF
MI
17
NA
9
NA
NA
10
10
NA
In stand-by mode, the
voltage on MI is routed to
Master input LNBA pin. Can be left
open if bypass function is
not needed
18
19
NA
10
10
10
10
NA
NA
NA
NA
NA
NA
See truth tables for
Output port voltage and port
selection
LNBB
NA
NA
NA
Note:
The limited pin availability of the PowerSO-10 package leads to drop some functions.
5/24
Maximum ratings
LNBP20 / LNBP1X series
3
Maximum ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VI
VO
IO
DC Input voltage (VCC1, VCC2, MI)
Output voltage
28
-0.3 to 28
Internally Limited
-0.5 to 7
V
V
Output current (LNBA, LNBB)
Logic input voltage (ENT, EN OSEL, VSEL, LLC)
Bypass switch current
mA
V
VI
ISW
PD
Tstg
Top
900
mA
W
Power dissipation at Tcase < 85°C
Storage temperature range
14
-40 to +150
-40 to +125
°C
°C
Operating junction temperature range
Note:
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these condition is not implied
Table 3.
Symbol
Thermal data
Parameter
PowerSO-20
PowerSO-10
Unit
RthJC
Thermal resistance junction-case
2
2
°C/W
Table 4.
Logic Controls Truth Table
CONTROL I/O
PIN NAME
L
H
OUT
IN
OLF
ENT
EN
IOUT > IOMAX or Tj > 150°C
22KHz tone OFF
IOUT < IOMAX
22KHz tone ON
See Table Below
See Table Below
See Table Below
See Table Below
IN
See Table Below
See Table Below
See Table Below
See Table Below
IN
OSEL
VSEL
LLC
IN
IN
EN
OSEL
VSEL
LLCO
VLNBA
VLNBB
L
X
L
X
L
X
L
VMI - 0.4V (typ.)
13V (typ.)
18V (typ.)
14V (typ.)
19V (typ.)
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
13V (typ.)
18V (typ.)
14V (typ.)
19V (typ.)
H
H
H
H
H
H
H
H
L
H
L
L
L
H
H
L
L
H
L
H
H
H
H
H
L
L
Disabled
H
H
Disabled
H
Disabled
Note:
All logic input pins have internal pull-down resistor (typ. = 250KW)
6/24
LNBP20 / LNBP1X series
Diagram
4
Diagram
Figure 2.
Block diagram
7/24
Electrical characteristics
LNBP20 / LNBP1X series
5
Electrical characteristics
Table 5.
Electrical characteristics for LNBP Series (T = 0 to 85°C, C = 0.22µF, C = 0.1µF,
J
I
O
EN=H, ENT=L, LLC=L, V =16V, V =23V I
=50mA, unless otherwise specified.)
IN1
IN2
OUT
Symbol
Parameter
Test conditions
O = 500 mA, ENT=H, VSEL=L, LLC=L
IO = 500 mA, ENT=H, VSEL=L, LLC=H
O = 500 mA, ENT=H, VSEL=L, LLC=L
IO = 500 mA, VSEL=L, LLC=H
Min.
Typ.
Max.
Unit
I
15
16
25
25
V
V
VIN1
VCC1 Supply voltage
I
22
25
V
VIN2
VO1
VO2
VCC2 Supply voltage
Output voltage
23
25
V
I
I
I
O = 500 mA, VSEL=H, LLC=L
O = 500 mA, VSEL=H, LLC=H
O = 500 mA, VSEL=L, LLC=L
17.3
18
19
13
14
4
18.7
V
V
12.5
13.5
V
Output voltage
IO = 500 mA, VSEL=L, LLC=H
VIN1=15 to 18V, VOUT=13V
VIN2=22 to 25V, VOUT=18V
V
40
40
mV
mV
ΔVO
ΔVO
Line regulation
Load regulation
4
VIN1=VIN2=22V, VOUT=13 or 18V
IO = 50 to 500mA
80
180
mV
SVR
IMAX
Supply voltage rejection
Output current limiting
VIN1 = VIN2 = 23 ± 0.5Vac, fac = 120 Hz,
45
dB
500
650
800
mA
Dynamic overload
protection OFF time
tOFF
tON
Output Shorted, CEXT = 4.7µF
Output Shorted, CEXT = 4.7µF
1100
ms
ms
Dynamic overload
protection ON time
tOFF/15
fTONE Tone frequency
ENT=H
20
0.55
40
22
0.72
50
24
0.9
60
15
KHz
VPP
%
ATONE Tone amplitude
DTONE Tone duty cycle
ENT=H
ENT=H
tr, tf
Tone rise and fall time
ENT=H
5
10
µs
GEXTM External modulation gain
ΔVOUT/ΔVEXTM, f = 10Hz to 40KHz
5
External modulation input
voltage
VEXTM
AC Coupling
400
mVPP
Ω
External modulation
ZEXTM
f = 10Hz to 40KHz
400
0.35
0.28
impedance
Bypass switch voltage
VSW
EN=L, ISW=300mA, VCC2-VMI=4V
0.6
0.5
10
V
drop (MI to LNBA)
Overload flag pin logic
LOW
VOL
I
OL=8mA
V
Overload flag pin OFF
IOZ
VOH = 6V
µA
V
state leakage current
Control input pin logic
LOW
VIL
0.8
8/24
LNBP20 / LNBP1X series
Electrical characteristics
Table 5.
Symbol
Electrical characteristics for LNBP Series (T = 0 to 85°C, C = 0.22µF, C = 0.1µF,
J
I
O
EN=H, ENT=L, LLC=L, V =16V, V =23V I
=50mA, unless otherwise specified.)
IN1
IN2
OUT
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Control input pin logic
HIGH
VIH
IIH
2.5
V
Control pins input current VIH = 5V
20
0.3
3.1
µA
mA
mA
Output Disabled (EN=L)
ENT=H, IOUT=500mA
EN=L, VLNBA = VLNBB = 18V
1
6
ICC
Supply current
IOBK
Output backward current
0.2
3
mA
°C
VIN1 = VIN2 = 22V or floating
Temperature shutdown
threshold
TSHDN
150
9/24
Typical characteristics
LNBP20 / LNBP1X series
6
Typical characteristics
(unless otherwise specified T = 25°C)
J
Figure 3.
Output voltage vs output current
Tone fall time vs temperature
Tone rise time vs temperature
Figure 4.
Figure 6.
Figure 8.
Tone duty cycle vs temperature
Figure 5.
Tone frequency vs temperature
Figure 7.
Tone amplitude vs temperature
10/24
LNBP20 / LNBP1X series
Typical characteristics
Figure 9.
S.V.R. vs Frequency
Figure 10. External modulation vs
temperature
Figure 11. Bypass switch drop vs output
current
Figure 12. LNBA External modulation gain vs
frequency
Figure 13. Bypass switch drop vs output
current
Figure 14. Overload flag pin logic low vs flag
current
11/24
Typical characteristics
LNBP20 / LNBP1X series
Figure 15. Supply voltage vs temperature
Figure 16. Supply voltage vs temperature
Figure 17. Dynamic overload protection (I
vs time)
Figure 18. Tone enable
SC
Figure 19. Tone disable
Figure 20. 22KHz Tone
12/24
LNBP20 / LNBP1X series
Figure 21. Enable time
Typical characteristics
Figure 22. Disable time
Figure 23. 18V to 13V Change
Figure 24. 18V to 13V Change
13/24
Typical application schematics
LNBP20 / LNBP1X series
7
Typical application schematics
Figure 25. Two antenna ports receiver
MCU+V
10uF
17V
24V
ANT CONNECTORS
JA
C2
11
1
2
AUX DATA
EXTM
OLF
VCC1
VCC2
R1
3
15
14
LNBA
LNBB
MI
47K
13
JB
TUNER
4
9
5
7
12
10
VSEL
ENT
EN
OSEL
LLC
CEXT
C1
+
4.7µF
C3 C4 C5 C6
8
GND
2x 47nF
2x 0.1µF
LNBP20CR
Vcc
I/Os
I/Os
MCU
Figure 26. Single antenna receiver with master receiver port
17V
24V
MCU+V
10uF
C2
1
2
11
13
AUX DATA
EXTM
OLF
VCC1
VCC2
R1
ANT
3
15
14
LNBA
LNBB
MI
47K
MASTER
10
4
9
5
7
12
TUNER
VSEL
ENT
EN
OSEL
LLC
CEXT
4.7µF
C1
+
C3 C4 C5
47nF
8
GND
2x 0.1µF
LNBP20CR
Vcc
I/Os
I/Os
MCU
14/24
LNBP20 / LNBP1X series
Typical application schematics
Figure 27. Using serial bus to save MPU I/os
17V
24V
MCU+V
ANT
CONNECTORS
C2
R1
11
13
1
2
AUX DATA
EXTM
VCC1
VCC2
47K
JA
10uF
3
15
14
LNBA
LNBB
MI
OLF
JB
TUNER
1
2
3
15
4
5
6
7
14
13
12
11
4
9
5
7
12
10
VSEL
STR
D
CLK
OE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CEXT
ENT
EN
OSEL
LLC
4.7µF
C1
+
C3 C4 C5 C6
8
GND
2x 0.1µF 2x 47nF
LNBP20CR
9
10
QS
QS
4094
SERIAL
BUS
MCU+V
I/Os
Vcc
MCU
Figure 28. Two antenna ports receiver - low cost solution
17V
24V
ANT CONNECTORS
JA
1
2
VCC1
VCC2
3
LNBA
LNBB
10
JB
8
4
7
5
9
TUNER
CEXT
GND
VSEL
ENT
EN
C1
+
C3
C4
C5
C6
4.7µF
OSEL
6
2x 0.1µF
2x 47nF
LNBP10SP
MCU+V
Vcc
I/Os
I/Os
MCU
15/24
Typical application schematics
LNBP20 / LNBP1X series
Figure 29. Connecting together V
and V
CC2
CC1
24V
ANT CONNECTORS
JA
1
2
VCC1
VCC2
3
LNBA
LNBB
10
JB
8
4
TUNER
CEXT
VSEL
7
ENT
5
C1
+
C4
C5
C6
4.7µF
EN
9
OSEL
6
GND
0.1µF
2x 47nF
LNBP10SP
MCU+V
Vcc
I/Os
I/Os
MCU
Figure 30. Single antenna receiver with master receiver port - low cost solution
17V
24V
C2
9
1
2
AUX DATA
EXTM
VCC1
VCC2
ANT
10µF
3
LNBA
10
8
MASTER
MI
TUNER
4
7
5
VSEL
ENT
EN
CEXT
C3
C4
C5
4.7µF C1
+
6
47nF
GND
2x 0.1µF
LNBP13SP
MCU+V
Vcc
I/Os
I/Os
MCU
16/24
LNBP20 / LNBP1X series
Typical application schematics
Figure 31. Single antenna receiver with overload diagnostic
17V
24V
MCU+V
C2
9
1
2
AUX DATA
EXTM
OLF
VCC1
VCC2
10µF
R1
3
LNBA
ANT
10
47K
8
4
7
5
TUNER
CEXT
VSEL
ENT
EN
4.7µF C1
C3 C4 C5
+
47nF
6
GND
2x 0.1µF
LNBP15SP
Vcc
I/Os
I/Os
MCU
17/24
Package mechanical data
LNBP20 / LNBP1X series
8
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
18/24
LNBP20 / LNBP1X series
Package mechanical data
PowerSO-20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
3.60
0.30
3.30
0.10
0.53
0.32
16.00
14.50
MIN.
TYP.
MAX.
0.1417
0.0118
0.1299
0.0039
0.0209
0.0013
0.630
A
a1
a2
a3
b
0.10
0.0039
0
0
0.40
0.23
15.80
13.90
0.0157
0.0090
0.6220
0.5472
c
D (1)
E
0.5710
e
1.27
0.0500
0.4500
e3
E1 (1)
E2
E3
G
11.43
10.90
11.10
2.90
6.2
0.4291
0.4370
0.1141
0.2441
0.0039
0.6260
0.0433
0.0433
10°
5.8
0
0.2283
0.0000
0.6102
0.10
15.9
1.10
1.10
10°
H
15.5
h
L
0.80
0°
0.0314
0°
N
S
8°
8°
T
10.0
0.3937
(1) “D and E1” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006”)
0056635/I
19/24
Package mechanical data
LNBP20 / LNBP1X series
PowerSO-10 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
3.70
0.146
A1
0.10
3.60
1.35
0.53
0.55
9.60
7.60
14.40
9.50
7.60
6.10
0.004
0.142
0.053
0.021
0.022
0.378
0.299
0.567
0.374
0.299
0.240
A2
A3
b
3.40
1.25
0.40
0.35
9.40
7.40
13.80
9.30
7.20
5.90
0.134
0.049
0.016
0.014
0.370
0.291
0.543
0.366
0.283
0.232
c
D
D1
E
E1
E2
E3
e
1.27
0.050
L
0.95
0°
1.65
8°
0.037
0°
0.065
8°
α
0068039-E
20/24
LNBP20 / LNBP1X series
Package mechanical data
Tape & Reel PowerSO-20 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
D
12.8
20.2
60
13.2
0.504
0.795
2.362
N
T
30.4
15.3
16.7
4.0
1.197
0.602
0.658
0.157
0.161
0.949
0.957
Ao
Bo
Ko
Po
P
15.1
16.5
3.8
0.594
0.650
0.149
0.153
0.941
0.933
3.9
4.1
23.9
23.7
24.1
24.3
W
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Package mechanical data
LNBP20 / LNBP1X series
Tape & Reel PowerSO10 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
D
12.8
20.2
60
13.2
0.504
0.795
2.362
N
T
30.4
15.1
10.1
4.35
4.1
1.197
0.594
0.398
0.171
0.161
0.949
0.957
Ao
Bo
Ko
Po
P
14.9
9.9
0.587
0.390
0.163
0.153
0.941
0.933
4.15
3.9
23.9
23.7
24.1
24.3
W
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LNBP20 / LNBP1X series
Revision history
9
Revision history
Table 6.
Revision history
Revision
Date
Changes
08-Jun-2004
21-Dec-2004
07-Sep-2006
03-May-2007
7
8
Typing Error VO1 and VO2 on Table 6 - Page 6.
Table 2 has been updated on GND row.
Add value VO on table 2 and new template.
Order codes has been updated.
9
10
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LNBP20 / LNBP1X series
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