L9951TR [STMICROELECTRONICS]
Rear door actuator driver; 后车门执行器的驱动程序
| 型号： | L9951TR |
| 厂家： | 
ST |
| 描述： | Rear door actuator driver |
| 文件： | 总36页 (文件大小：535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L9951
L9951XP
Rear door actuator driver
Features
(2)
Type
Outputs(1)
Ron
IOUT
VS
OUT1
OUT2
OUT3
OUT4
OUT5
150 mΩ
200 mΩ
200 mΩ
800 mΩ
800 mΩ
7.4 A
5 A
L9951
5 A
28 V
L9951XP
1.25 A
1.25 A
PowerSSO-36
PowerSO-36
1. See block diagram.
2. Typical values.
Applications
■ Rear door actuator driver with bridges for door
lock and safe lock and two 5W or 10W - light
bulbs.
■ One half bridge for 7.4 A load (R = 150 mΩ)
on
■ Two half bridges for 5 A load (R = 200 mΩ)
on
■ Two highside drivers for 1.25 A load
(R = 800 mΩ)
on
Description
■ Programmable softstart function to drive loads
with higher inrush currents (i.e.current > 7.4A,
>5A, >1.25A)
The L9951 and L9951XP are microcontroller
driven, multifunctional rear door actuator drivers
for automotive applications. Up to two DC motors
and two grounded resistive loads can be driven
with three half bridges and two hide side drivers.
The integrated standard serial peripheral interface
(SPI) controls all operation modes (forward,
reverse, brake and high impedance). All
■ Very low current consumption in standby mode
(I < 3µA, typ. T ≤ 85°C)
S
j
■ All outputs short circuit protected
■ Current monitor output for all highside drivers
■ All outputs over temperature protected
■ Open-load diagnostic for all outputs
■ Overload diagnostic for all outputs
diagnostic information is available via the SPI.
■ Programmable PWM control of all outputs
■ Charge pump output for reverse polarity
protection
Table 1.
Device summary
Package
Order codes
Tape and reel
Tube
PowerSO-36
L9951
L9951TR
PowerSSO-36
L9951XP
L9951XPTR
May 2010
Doc ID 14173 Rev 8
1/36
www.st.com
1
Contents
L9951 / L9951XP
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
2.6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Standby - mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Over-voltage and under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . 20
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 PWM input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12 Programmable softstart function to drive loads with higher inrush current 21
4
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Contents
4.8
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
6
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1
6.2
6.3
6.4
6.5
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 14173 Rev 8
3/36
List of tables
L9951 / L9951XP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definitions and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Charge pump output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
OUT 1 - OUT 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
EN, CSN timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI - Input data and status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI - Input data and status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4/36
Doc ID 14173 Rev 8
L9951 / L9951XP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI - driver turn-on/off timing, minimum CSN HI time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. PowerSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12. PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TM
Figure 13. PowerSO-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TM
Figure 14. PowerSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TM
Figure 15. PowerSSO-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TM
Figure 16. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 14173 Rev 8
5/36
Block diagram and pin description
L9951 / L9951XP
1
Block diagram and pin description
Figure 1.
Block diagram
VBAT
Reverse
Polarity
Protection
* Note: Value of capacitor has to be choosen carefully to limit the VS
voltage below absolute maximum ratings in case of an unexpected
100k
freewheeling condition of inductive loads (e.g. TSD, POR)
*
VS
CP
100µF
VREG
100nF
EMC
Optimization
OUT1
Charge
Pump
VCC
+
100
10
VCC
Lock
M
OUT2
OUT3
100nF
Safe Lock
M
DI
**1k
**1k
**1k
**1k
DO
CLK
CSN
Exterior Light
Safety Light
OUT4
OUT5
EN
**1k
µC
MUX
GND
CM / PWM
5
**1k
** Note: Resistors between µC and L9951 are recommended to limit currents
for negative voltage transients at VBAT (e.g. ISO type 1 pulse)
+ Note: Using a ferrite instead of 10ohm will additionally improve EMC behavior
6/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Block diagram and pin description
Function
Table 2.
Pin definitions and functions
Symbol
Pin
Ground .
1, 18, 19,
36
Reference potential.
GND
Note: For the capability of driving the full current at the outputs all pins of
GND must be externally connected.
Power supply voltage (external reverse protection required).
6, 7, 14,
15, 23, 24,
29, 32
For EMI reason a ceramic capacitor as close as possible to GND is
recommended.
VS
Note: for the capability of driving the full current at the outputs all pins of
VS must be externally connected.
Half-bridge output 1.
The output is built by a high side and a low side switch, which are
internally connected. The output stage of both switches is a power
DMOS transistor. Each driver has an internal reverse diode (bulk-drain-
diode: high side driver from output to VS, low side driver from GND to
output). This output is over-current and open-load protected.
3, 4, 34
OUT1
Note: for the capability of driving the full current at the outputs all pins of
OUT1 must be externally connected.
Serial data input.
The input requires CMOS logic levels and receives serial data from the
microcontroller. The data is a 16bit control word and the least significant
bit (LSB, bit 0) is transferred first.
8
DI
Current monitor output/PWM input.
Depending on the selected multiplexer bits (bit 9, 10, 11) of Input Data
Register this output sources an image of the instant current through the
corresponding high side driver with a ratio of 1/10.000. This pin is
bidirectional. The microcontroller can overwrite the current monitor signal
to provide a PWM input for all outputs.
9
CM/PWM
Testmode:
If CSN is raised above 7.5V the device will enter the test mode. In test
mode this output can be used to measure some internal signals (see
Table 18).
Chip select not input / Testmode .
This input is low active and requires CMOS logic levels. The serial data
transfer between L9951 and micro controller is enabled by pulling the
input CSN to low level. If an input voltage of more than 7.5V is applied to
CSN pin the L9951 will be switched into a test mode.
10
11
CSN
DO
Serial data output .
The diagnosis data is available via the SPI and this tristate-output. The
output will remain in tristate, if the chip is not selected by the input CSN
(CSN = high).
Logic supply voltage .
12
13
VCC
CLK
For this input a ceramic capacitor as close as possible to GND is
recommended.
Serial clock input .
This input controls the internal shift register of the SPI and requires
CMOS logic levels.
Doc ID 14173 Rev 8
7/36
Block diagram and pin description
L9951 / L9951XP
Table 2.
Pin
Pin definitions and functions (continued)
Symbol
Function
Half-bridge output 2 (see OUT1 - pin 3, 4).
16, 17
20, 21
26
OUT2
Note: for the capability of driving the full current at the outputs all pins of
OUT2 must be externally connected.
Half-bridge output 3 (see OUT1 - pin 3, 4).
OUT3
CP
Note: for the capability of driving the full current at the outputs all pins of
OUT3 must be externally connected.
Charge Pump Output .
This output is provided to drive the gate of an external n-channel power
MOS used for reverse polarity protection (see Figure 1).
Enable input.
27
EN
If Enable input is forced to GND the device will enter Standby-Mode. The
outputs will be switched off and all registers will be cleared
High side driver output 4, 5 .
The output is built by a high side switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy which
can be dissipated is limited. The high side driver is a power DMOS
transistor with an internal reverse diode from the output to VS (bulk-
drain-diode). The output is over-current and open-load protected.
33, 35
OUT4, OUT5
Figure 2.
Configuration diagram (top view)
GND
N.C.
OUT1
OUT1
N.C.
VS
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
OUT5
OUT1
OUT4
VS
2
3
4
5
6
N.C.
N.C.
VS.
N.C.
EN
7
VS
DI
8
9
CM/PWM
CSN
DO
Chip
10
11
12
13
14
15
16
17
18
CP
VCC
CLK
N.C.
VS
VS
VS
VS
N.C.
OUT3
OUT3
GND
OUT2
OUT2
GND
Leadframe
8/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics sure
program and other relevant quality document
Table 3.
Absolute maximum ratings
Symbol Parameter
Value
Unit
DC supply voltage
-0.3 to 28
40
V
V
V
V
V
V
A
A
VS
Single pulse tmax < 400ms
Stabilized supply voltage, logic supply
VCC
-0.3 to 5.5
-0.3 to VCC + 0.3
-0.3 to VCC + 0.3
-25 to VS + 11
10
V
DI,VDO,VCLK,VCSN,VEN Digital input / output voltage
VCM
VCP
Current monitor output
Charge pump output
Output current
IOUT1,2,3
IOUT4,5
Output current
5
2.2
ESD protection
Table 4.
ESD protection
Parameter
Value
Unit
All pins
± ±4(1)
± ±8(2)
kV
kV
Output pins: OUT1 - OUT5
1. HBM according to CDF-AEC-Q100-002.
2. HBM with all unzapped pins grounded.
2.3
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Operating junction temperature
Value
Unit
Tj
-40 to 150
°C
Doc ID 14173 Rev 8
9/36
Electrical specifications
L9951 / L9951XP
2.4
Temperature warning and thermal shutdown
Table 6.
Symbol
Temperature warning and thermal shutdown
Parameter
Min.
Typ. Max. Unit
Temperature warning threshold junction
temperature
Tj
TjTW ON
150
°C
increasing
Temperature warning threshold junction
temperature
Tj
TjTW OFF
130
°C
°K
°C
decreasing
TjTW HYS Temperature warning hysteresis
5
5
Thermal shutdown threshold junction
temperature
Tj
TjSD ON
170
increasing
Thermal shutdown threshold junction
temperature
Tj
TjSD OFF
150
°C
°K
decreasing
TjSD HYS Thermal shutdown hysteresis
2.5
Electrical characteristics
V = 8 to 16 V, V = 4.5 to 5.3 V, T = - 40 to 150 °C, unless otherwise specified.
S
CC
j
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 7.
Symbol
Supply
Parameter
Test condition
Min. Typ. Max. Unit
Operating supply voltage
range
VS
7
28
20
V
VS = 13V, VCC = 5.0V
active mode
VS DC supply current
7
mA
OUT1 - OUT5 floating
VS = 13V, VCC = 0V
standby mode
IS
3
6
10
20
µA
µA
OUT1 - OUT5 floating
Ttest =-40°C, 25°C
VS quiescent supply current
T
test = 130°C
10/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Electrical specifications
Min. Typ. Max. Unit
Table 7.
Supply (continued)
Parameter
Symbol
Test condition
VS = 13V, VCC = 5.0V
CSN = VCC
VCC DC supply current
1
1
3
3
mA
µA
active mode
ICC
VS = 13V, VCC = 5.0V
CSN = VCC
VCC quiescent supply
current
standby mode
OUT1 - OUT5 floating
VS = 13V, VCC = 5.0V
CSN = VCC
Sum quiescent supply
current
IS + ICC
7
23
µA
standby mode
OUT1 - OUT5 floating
Table 8.
Symbol
Overvoltage and undervoltage detection
Parameter Test condition
VS increasing
Min. Typ. Max. Unit
VSUV ON VS UV-threshold voltage
VSUV OFF VS UV-threshold voltage
VSUV hyst VS UV-hysteresis
6.0
5.4
7.2
6.5
V
V
V
V
V
V
V
V
V
VS decreasing
VSUV ON - VSUV OFF
VS increasing
0.55
0.5
VSOV OFF VS OV-threshold voltage
VSOV ON VS OV-threshold voltage
VSOV hyst VS OV-hysteresis
18
24.5
4.4
VS decreasing
17.5
VSOV OFF - VSOV ON
VCC increasing
VPOR OFF Power-on-reset threshold
VPOR ON Power-on-reset threshold
VPOR hyst Power-on-reset hysteresis
VCC decreasing
VPOR OFF - VPOR ON
3.1
0.3
Table 9.
Symbol
Current monitor output
Parameter
Test condition
Min.
Typ.
Max.
Unit
VCM
Functional voltage range VCC = 5V
Current monitor output
0
4
V
ratio:
ICM,r
0V ≤±VCM ≤±4V, VCC=5V
1:10000
-
ICM / IOUT1,2,3,4,5
0V ≤±VCM≤ 4V,
VCC=5V,
IOUT1-5,low =500mA
4% +
1%FS 2%FS
8% +
ICM acc Current monitor accuracy IOUT1,high =6A
IOUT2,3,high =4.9A
-
IOUT4,5,high =1.2A
(FS=full scale=600 μA)
Doc ID 14173 Rev 8
11/36
Electrical specifications
L9951 / L9951XP
Table 10. Charge pump output
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VS=8V, ICP = -60µA
VS=10V, ICP = -80µA
VS≥12V, ICP = -100µA
6
8
13
13
13
V
V
V
Charge pump output
voltage
VCP
10
VCP = VS+10V
VS =13.5V
Charge pump output
current
ICP
100
150
300
µA
Table 11.
Symbol
OUT 1 - OUT 5
Parameter
Test condition
Min.
Typ.
Max.
Unit
VS = 13.5 V, Tj = 25 °C,
150
200
mΩ
IOUT1 = ± ±3 A
VS = 13.5 V, Tj = 125 °C,
On-resistance to supply
or GND
RON OUT1
225
150
200
300
200
800
1250
800
300
200
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
IOUT1 = ± ±3 A
VS = 8.0 V, Tj = 25 °C,
IOUT1 = ± ±3 A
VS = 13.5 V, Tj = 25 °C,
270
IOUT2,3 = ± ±3 A
VS = 13.5 V, Tj = 125 °C,
RONOUT2 On-resistance to supply
RON OUT3 or GND
400
IOUT2,3 = ± ±3 A
VS = 8.0 V, Tj = 25 °C,
270
IOUT2,3 = ± ±3 A
VS = 13.5 V, Tj = 25 °C,
1100
1700
IOUT4,5 = ± ±0.8 A
VS = 13.5 V, Tj = 125 °C,
rON OUT4, On-resistance to supply
rON OUT5 or GND
IOUT4,5 = ± ±0.8 A
VS = 8.0 V, Tj = 25 °C,
1100
15.5
10.5
2.6
mΩ
A
IOUT4,5 = ± ±0.8 A
Output current limitation
to supply or GND
|IOUT1
|
Sink and source
Sink and source
Source
7.4
5.0
|IOUT2|, Output current limitation
|IOUT3 to supply or GND
A
|
|IOUT4|, Output current limitation
1.25
A
|IOUT5
|
to GND
VS = 13.5 V,
corresponding lowside
driver is not active
Output delay time,
highside driver on
td ON H
td OFF H
td ON L
20
80
20
40
200
60
90
300
80
µs
µs
µs
Output delay time,
highside driver off
VS = 13.5 V
VS = 13.5 V,
corresponding highside
driver is not active
Output delay time,
lowside driver on
12/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Electrical specifications
Table 11.
OUT 1 - OUT 5 (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Output delay time,
lowside driver off
td OFF L
VS = 13.5 V
80
150
300
µs
Cross current protection
time, source to sink
tD HL
tD LH
td ON L - td OFF H,
200
200
400
400
µs
µs
Cross current protection
time, sink to source
td ON H - td OFF L
VOUT1-5 = 0V, standby
mode
Switched-off output
current highside drivers of
OUT1-5
0
-2
-15
50
-5
0
µA
µA
µA
µA
mA
IQLH
VOUT1-5 = 0V, active mode
-40
0
VOUT1-3 = VS, standby
mode
Switched-off output
current lowside drivers of
OUT1-3
100
0
IQLL
VOUT1-3= VS, active mode
-40
70
-15
160
Open-load detection
current of OUT1
IOLD1
240
Open-load detection
current of OUT2, OUT3
IOLD23
70
5
160
15
240
40
mA
mA
Open-load detection
IOLD45 current of OUT4 and
OUT5
Minimum duration of
tdOL
open-load condition to set
the status bit
500
10
3000
100
µs
µs
Minimum duration of
over-current condition to
switch off the driver
tISC
VS =13.5 V
dV
/dt Slew rate of OUT1
0.1
0.1
0.1
0.2
0.2
0.2
0.4
0.4
0.4
V/µs
V/µs
V/µs
OUT1
OUT23
OUT45
Iload = 1.5 A
VS = 13.5 V
dV
dV
/dt Slew rate of OUT2, OUT3
/dt Slew rate of OUT4, OUT5
Iload = 1.5 A
VS = 13.5 V
Iload = - 0.8 A
Doc ID 14173 Rev 8
13/36
Electrical specifications
L9951 / L9951XP
2.6
SPI - electrical characteristics
(V = 8 to 16 V, V = 4.5 to 5.3 V, T = - 40 to 150 °C, unless otherwise specified. The
S
CC
j
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin).
Table 12. Delay time from standby to active mode
Symbol
Parameter
Test condition
Min. Typ.
Max.
Unit
Switching from standby
to active mode. Time
until not Ready Bit goes
low.
tset
Internal startup time
80
300
µs
Table 13. Inputs: CSN, CLK, PWM1/2 and DI
Symbol
Parameter
Input low level
Input high level
Test condition
Min. Typ.
Max.
Unit
VinL
VinH
VCC = 5V
VCC = 5V
1.5
2.0
3.0
V
V
3.5
VinHyst Input hysteresis
VCC = 5V
0.5
-50
10
V
ICSN in Pull up current at input CSN
ICLK in Pull down current at input CLK
VCSN = 3.5V VCC = 5V
VCLK = 1.5V
VDI = 1.5V
-25
25
-10
50
50
µA
µA
µA
IDI in
Pull down current at input DI
10
25
Pull down resistance at input
EN
IEN in
100
210
10
480
15
kΩ
Input capacitance at input
CLK, DI and PWM
C in
VCC = 0 to 5.3V
pF
Note:
Value of input capacity is not measured in production test. Parameter guaranteed by design.
(1)
Table 14. DI timing
Symbol
Parameter
Clock period
Test condition
Min. Typ.
Max.
Unit
tCLK
tCLKH
tCLKL
VCC = 5V
VCC = 5V
VCC = 5V
1000
400
ns
ns
ns
Clock high time
Clock low time
400
CSN setup time, CSN low
before rising edge of CLK
tset CSN
V
CC = 5V
400
400
ns
ns
CLK setup time, CLK high
before rising edge of CSN
tset CLK
tset DI
VCC = 5V
DI setup time
VCC = 5V
VCC = 5V
200
200
ns
ns
thold time DI hold time
14/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Electrical specifications
(1)
Table 14. DI timing (continued)
Symbol
Parameter
Test condition
Min. Typ.
Max.
Unit
Rise time of input signal DI,
CLK, CSN
tr in
VCC = 5V
100
ns
Fall time of input signal DI,
CLK, CSN
tf in
VCC = 5V
100
ns
1. See Figure 3 and Figure 4
Note:
DI timing parameters tested in production by a passed/failed test:
Tj= -40°C/+25°C: SPI communication @2MHZ.
Tj= +125°C: SPI communication @1.25MHZ.
Table 15. DO
Symbol
Parameter
Output low level
Test condition
Min. Typ. Max. Unit
VDOL
VCC = 5 V, ID = -4mA
0.2
0.4
V
V
VCC
-0.4
VCC
-0.2
VDOH
Output high level
VCC = 5 V, ID = 4 mA
V
CSN = VCC
0V < VDO < VCC
CSN = VCC
0V < VCC < 5.3V
,
IDOLK
Tristate leakage current
Tristate input capacitance
-10
10
15
µA
pF
V
,
(1)
CDO
10
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
(1)
Table 16. DO timing
Symbol
Parameter
DO rise time
Test condition
Min. Typ. Max. Unit
tr DO
tf DO
CL = 100 pF, Iload = -1mA
CL = 100 pF, Iload = 1mA
CL = 100 pF, Iload = 1mA
80
50
140
100
ns
ns
DO fall time
DO enable time
ten DO tri L
tdis DO L tri
ten DO tri H
tdis DO H tri
td DO
100
380
100
380
50
250
450
250
450
250
ns
ns
ns
ns
ns
from tristate to low level pull-up load to VCC
DO disable time CL = 100 pF, Iload = 4 mA
from low level to tristate pull-up load to VCC
DO enable time CL =100 pF, Iload = -1mA
from tristate to high level pull-down load to GND
DO disable time CL = 100 pF, Iload = -4mA
from high level to tristate pull-down load to GND
VDO < 0.3 VCC, VDO > 0.7VCC
,
DO delay time
CL = 100pF
1. See Figure 5 and Figure 6.
Doc ID 14173 Rev 8
15/36
Electrical specifications
L9951 / L9951XP
(1)
Table 17. EN, CSN timing
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
Minimum EN high before
sending first SPI frame, i.e.
CSN going low
Transfer of SPI-command
to input register
t
20
2
50
4
µs
µs
EN_CSN_LO
Minimum CSN HI time
between two SPI frames
Transfer of SPI-command
to input register
tCSN_HI,min
1. See Figure 7
Figure 3.
SPI - transfer timing diagram
CSN high to low: DO enabled
CSN
time
CLK
DI
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
time
DI: data will be accepted on the rising edge of CLK signal
actual data
new data
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
time
time
time
DO: data will change on the falling edge of CLK signal
status information
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
DO
fault bit
CSN low to high: actual data is
transfered to output power switches
old data
actual data
e.g.OUT1
Figure 4.
SPI - input timing
0.8 VCC
0.2 VCC
CSN
tset CSN
tCLKH
tset CLK
0.8 VCC
0.2 VCC
CLK
tset DI thold DI
tCLKL
0.8 VCC
0.2 VCC
Valid
Valid
DI
16/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Electrical specifications
Figure 5.
SPI - DO valid data delay time and valid time
tf in
tr in
0.8 VCC
0.5 VCC
0.2 VCC
CLK
tr DO
DO
(low to high)
0.8 VCC
0.2 VCC
td DO
tf DO
0.8 VCC
0.2 VCC
DO
(high to low)
Figure 6.
SPI - DO enable and disable time
tf in
tr in
0.8 VCC
50%
CSN
0.2 VCC
DO
pull-up load to VCC
50%
C
L
= 100 pF
ten DO tri L
tdis DO L tri
DO
50%
pull-down load to GND
= 100 pF
C
L
ten DO tri H
tdis DO H tri
Doc ID 14173 Rev 8
17/36
Electrical specifications
Figure 7.
L9951 / L9951XP
SPI - driver turn-on/off timing, minimum CSN HI time
CSN low to high: data from shift register
is transferred to output power switches
tr in
tf in
tCSN_HI,min
80%
50%
20%
CSN
tdOFF
80%
50%
20%
output current
of a driver
ON state
OFF state
tOFF
tON
tdON
80%
50%
20%
output current
of a driver
OFF state
ON state
Figure 8.
SPI - timing of status bit 0 (fault condition)
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
CSN
CLK
time
time
DI
time
DI: data is not accepted
0
-
DO
time
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
18/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Application information
3
Application information
3.1
Dual power supply: VS and VCC
The power supply voltage V supplies the half bridges and the high side drivers. An internal
S
charge-pump is used to drive the high side switches. The logic supply voltage V
CC
(stabilized 5V) is used for the logic part and the SPI of the device. Due to the independent
logic supply voltage the control and status information will not be lost, if there are temporary
spikes or glitches on the power supply voltage. In case of power-on (V increases from
CC
under voltage to V
= 4.0V, typical) the circuit is initialized by an internally generated
POR OFF
power-on-reset (POR).
If the voltage V decreases under the minimum threshold (V
=3.6V, typical), the
POR ON
CC
outputs are switched to tristate (high impedance) and the status registers are cleared.
3.2
3.3
Standby - mode
The standby mode of the L9951 is activated by switching the EN input do GND. All latched
data will be cleared and the inputs and outputs are switched to high impedance. In the
standby mode the current at V (V ) is less than 3 µA (1µA) for CSN = high (DO in tristate).
If EN is switched to 5V the device will enter the active mode. In the active mode the charge-
pump and the supervisor functions are activated.
S
CC
Inductive loads
Each half bridge is built by an internally connected high side and a low side power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The high side
drivers OUT4 to OUT5 are intended to drive resistive loads. Hence only a limited energy
(E<0.5mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For
inductive loads (L > 50µH) an external free-wheeling diode connected to GND and the
corresponding output is needed.
3.4
Diagnostic functions
All diagnostic functions (over/open-load, power supply over-/undervoltage, temperature
warning and thermal shutdown) are internally filtered and the condition has to be valid for at
least 32µs (open-load: 1ms, respectively) before the corresponding status bit in the status
registers will be set. The filters are used to improve the noise immunity of the device. Open-
load and temperature warning function are intended for information purpose and will not
change the state of the output drivers. On contrary, the over load and thermal shutdown
condition will disable the corresponding driver (over load) or all drivers (thermal shutdown),
respectively. Without setting the over-current recovery bit in the Input Data Register to logic
high, the microcontroller has to clear the over-current status bit to reactivate the
corresponding driver. Each driver has a corresponding over-current recovery bit. If this bit is
set, the device will automatically switch-on the outputs again after a short recovery time. The
duty cycle in over-current condition can be programmed by the SPI interface (12% or 25%).
With this feature the device can drive loads with start-up currents higher than the over-
current limits (e.g. inrush current of lamps, cold resistance of motors and heaters).
Doc ID 14173 Rev 8
19/36
Application information
L9951 / L9951XP
3.5
Over-voltage and under-voltage detection
If the power supply voltage V rises above the over-voltage threshold V
(typical
S
SOV OFF
21V), the outputs OUT1 to OUT5 are switched to high impedance state to protect the load
and the internal charge-pump is turned-off. When the voltage V drops below the
S
undervoltage threshold V
(UV-switch-OFF voltage), the output stages are switched
SUV OFF
to the high impedance to avoid the operation of the power devices without sufficient gate
driving voltage (increased power dissipation). If the supply voltage V recovers to normal
S
operating voltage the output stages return to the programmed state (input register 0: bit
12=0). If the undervoltage / overvoltage recovery disable bit is set, the automatic turn-on of
the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the
drivers.
3.6
Temperature warning and thermal shutdown
If junction temperature rises above T
a temperature warning flag is set and is detectable
j TW
via the SPI. If junction temperature increases above the second threshold T , the thermal
j SD
shutdown bit will be set and power DMOS transistors of all output stages are switched off to
protect the device. In order to reactivate the output stages the junction temperature must
decrease below T
microcontroller.
- T
and the thermal shutdown bit has to be cleared by the
jSD
jSD HYS
3.7
3.8
3.9
Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load
current is below the open-load detection threshold for at least 1 ms (t ) the corresponding
open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without
changing the mechanical/electrical state of the loads.
dOL
Over load detection
In case of an over-current condition a flag is set in the status register in the same way as
open-load detection. If the over-current signal is valid for at least t =32µs, the over-current
flag is set and the corresponding driver is switched off to reduce the power dissipation and
to protect the integrated circuit. If the over-current recovery bit of the output is zero the
microcontroller has to clear the status bits to reactivate the corresponding driver.
ISC
Current monitor
The current monitor output sources a current image at the current monitor output which has
a fixed ratio (1/10000) of the instantaneous current of the selected high side driver. The bits
9, 10 and 11 of the input data register 0 control which of the outputs OUT1 to OUT5 will be
multiplexed to the current monitor output. The current monitor output allows a more precise
analysis of the actual state of the load rather than the detection of an open- or overload
condition. For example this can be used to detect the motor state (starting, free-running,
stalled). Moreover, it is possible to regulate the power of the defroster more precise by
measuring the monitor current.
20/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Application information
3.10
PWM input
Each driver has a corresponding PWM enable bit which can be programmed by the SPI
interface. If the PWM enable bit is set, the outputs OUT1 to OUT5 are controlled by the
logically AND-combination of the signal applied to the PWM input and the output control bit
in input data register1.
3.11
Cross-current protection
The three half-brides of the device are cross-current protected by an internal delay time. If
one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge
will be automatically delayed by the cross-current protection time. After the cross-current
protection time is expired the slew-rate limited switch-off phase of the driver will be changed
to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to
this behavior it is always guaranteed that the previously activated driver is totally turned-off
before the opposite driver will start to conduct.
3.12
Programmable softstart function to drive loads with higher
inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable softstart function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device will automatically switch-
on the outputs again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to be about 12% or 25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition.
The device itself cannot distinguish between a real overload and a non linear load like a light
bulb. A real overload condition can only be qualified by time. As an example the
microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first
50ms. After clearing the recovery bit the output will be automatically disabled if the overload
condition still exits.
Figure 9.
Example of programmable softstart function for inductive loads
Doc ID 14173 Rev 8
21/36
Functional description of the SPI
L9951 / L9951XP
4
Functional description of the SPI
4.1
Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be
driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and
CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible
output pins and one input pin will be needed to communicate with the device. A fault
condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the
status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers
0 and 1. The microcontroller can poll the status of the device without the need of a full SPI-
communication cycle.
Note:
In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see
Figure 3).
4.2
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started.
The state when CSN is going low until the rising edge of CSN will be called a
communication frame. If the CSN-input pin is driven above 7.5V, the L9951 will go into a test
mode. In the test mode the DO will go from tristate to active mode.
4.3
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 16 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register.
The writing to the selected Data Input Register is only enabled if exactly 16 bits are
transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are
counted within one frame the complete frame will be ignored. This safety function is
implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
22/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Functional description of the SPI
4.4
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
4.5
4.6
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
Input data register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of
the two input registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register will be written to the selected input data
register only if a frame of exact 16 data bits are detected. Depending on bit 0 the contents of
the selected status register will be transferred to DO during the current communication
frame. Bit 1-8 control the behavior of the corresponding driver. The bits 9,10 and 11 are
used to control the current monitor multiplexer. Bit 15 is used to reset all status bits in both
status registers. The bits in the status registers will be cleared after the current
communication frame (rising edge of CSN).
4.7
Status register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is
used as a fault bit and is a logical-NOR combination of bits 1-14 in both status registers. The
state of this bit can be polled by the microcontroller without the need of a full SPI-
communication cycle (see Figure 8.). If one of the over-current bits is set, the corresponding
driver will be disabled. If the over-current recovery bit of the output is not set the
microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown
bit is set, all drivers will go into a high impedance state. Again the microcontroller has to
clear the bit to enable the drivers.
4.8
Test mode
The test mode can be entered by rising the CSN input to a voltage higher than 7.5V. In the
test mode the inputs CLK, DI, PWM and the internal 2MHz CLK can be multiplexed to data
output DO for testing purpose. Furthermore the over-current thresholds are reduced by a
factor of 4 to allow EWS testing at lower current. The internal logic prevents that the Hi-Side
and Low-Side driver of the same half-bridge can be switched-on at the same time. In the test
mode this combination is used to multiplex the desired signals to the CM output according to
table 18 and 19.
Doc ID 14173 Rev 8
23/36
Functional description of the SPI
Table 18. Test mode
L9951 / L9951XP
LS1 HS1 LS2 HS2 LS3 HS3
! (both HI) ! (both HI) ! (both HI)
DO
LS1 HS1 LS2 HS2 LS3 HS3
! (both HI) ! (both HI) ! (both HI)
CM
NoError
DI
N.C
both HI
! (both HI)
both HI
! (both HI) ! (both HI)
both HI
! (both HI)
both HI
! (both HI) ! (both HI)
Tsense1
Tsense2
Tsense3
Tsense4
N.C
both HI
both HI
! (both HI)
CLK
both HI
both HI
! (both HI)
! (both HI)
both HI
! (both HI) INT_CLK
both HI PWM
! (both HI) ! (both HI)
! (both HI) ! (both HI)
both HI
! (both HI)
both HI
! (both HI)
both HI
both HI
both HI
5µA Iref
Vbandgap
both HI
both HI
Table 19. SPI - Input data and status register 0
Input register 0 (write)
Status register 0 (read)
Bit
Name
Comment
Name
Comment
A broken VCC-or SPI-
connection of the L9951 can
be detected by the
microcontroller, because all 16
bits low or high is not a valid
frame.
If reset bit is set both status
registers will be cleared after
rising edge of CSN input.
15
Reset bit
Always 1
If the disable open-load bit is
Disable open- set, the open-load status
In case of an over-voltage or
undervoltage event the
VS
14
13
load
bits will be ignored for the
NonErrorBit calculation.
corresponding bit is set and
the outputs are deactivated.
over-voltage
This bit defines in
combination with the over-
current recovery bit (input
register 1) the duty cycle in
over-current condition of an
activated driver. If
temperature warning bit is
set, L9951 will always use
the lower duty cycle
OC recovery
duty cycle
If VS voltage recovers to
normal operating conditions
undervoltage outputs are reactivated
automatically.
VS
0: 12% 1: 25%
Overvoltage/
In case of an thermal
shutdown all outputs are
switched off. The
microcontroller has to clear the
TSD bit by setting the reset bit
to reactivate the outputs.
If this bit is set the
microcontroller has to clear
the status register after
undervoltage/overvoltage
event to enable the outputs.
Thermal
shutdown
under-voltage
recovery
disable
12
24/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Functional description of the SPI
Table 19. SPI - Input data and status register 0 (continued)
Input register 0 (write)
Status register 0 (read)
Name Comment
Bit
Name
Comment
Following current image
(1/10.000) of the HS driver
will be multiplexed to CM
output:
This bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.
Temperature
warning
11
After switching the device from
standby mode to active mode
an internal timer is started to
allow charge pump to settle
before the outputs can be
activated. This bit is cleared
automatically after start up
time has finished. Since this bit
is controlled by internal clock it
can be used for synchronizing
testing events (e.g. measuring
filter times).
Bit 11 Bit 10 Bit 9 Output
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
OUT1
OUT2
OUT3
OUT4
OUT5
Current monitor
select bits
10
Not ready bit
9
8
0
Not used
OUT5-HS
OUT5 - HS
on/off
over - current
If a bit is set the selected
output driver is switched on.
If the corresponding PWM
enable bit is set (Input
Register 1) the driver is only
activated if PWM input
signal is high. The outputs of
OUT1-OUT3 are half
bridges. If the bits of HS-
and LS-driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
avoid a high internal current
from VS to GND.
In case of an over-current
event the corresponding status
bit is set and the output driver
is disabled. If the over-current
recovery enable bit is set
(Input Register 1) the output
will be automatically
reactivated after a delay time
resulting in a PWM modulated
current with a programmable
duty cycle (Bit 13).
OUT4-HS
OUT4 - HS
on/off
7
6
5
4
3
2
1
over - current
OUT3-HS
OUT3 - HS
on/off
over - current
OUT3-LS
OUT3 - LS
on/off
over - current
OUT2-HS
OUT2 - HS
on/off
over - current
OUT2-LS
OUT2 - LS
on/off
If the over-current recovery bit
is not set the microcontroller
has to clear the over-current bit
(reset bit) to reactivate the
output driver.
over - current
OUT1-HS
OUT1 - HS
on/off
over - current
OUT1-LS
OUT1 - LS
on/off
over - current
A logical NOR-combination of
all bits 1 to 14 in both status
0
0
No error bit registers. If bit 14 (disable
open-load) is set, the open-
load status will be ignored.
Doc ID 14173 Rev 8
25/36
Functional description of the SPI
L9951 / L9951XP
Table 20. SPI - Input data and status register 1
Input register 1 (write)
Status register 1 (read)
Bit
Name
Comment
Name
Comment
A broken VCC-or SPI-
connection of the L9951 can
be detected by the
microcontroller, because all
16 bits low or high is not a
valid frame.
15
Not used
Always 1
In case of an over-voltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated.
14
13
Not used
Not used
VS over-voltage
VS undervoltage
In case of an over-voltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated.
In case of an thermal
shutdown all outputs are
switched off. The
microcontroller has to clear
the TSD bit by setting the
reset bit to reactivate the
outputs.
Thermal
shutdown
12
11
Not used
Not used
This bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.
Temperature
warning
26/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Functional description of the SPI
Table 20. SPI - Input data and status register 1 (continued)
Input register 1 (write)
Status register 1 (read)
Name Comment
Bit
Name
Comment
In case of an over-current
event the over-current
status bit (status register
0) is set and the output is
switched off. If the over-
current recovery enable bit
is set the output will be
automatically reactivated
after a delay time resulting
in a PWM modulated
current with a
After switching the device
from standby mode to active
mode an internal timer is
started to allow charge pump
to settle before the outputs
can be activated. This bit is
OUT5 OC
recovery enable
10
Not ready bit cleared automatically after
start up time has finished.
Since this bit is controlled by
internal clock it can be used
for synchronizing testing
events(e.g. measuring filter
times).
programmable duty cycle
(Bit 13 of Input data
register 1).
OUT4 OC
9
8
7
0
Not used.
recovery enable
OUT5-HS
open-load
OUT3 OC
recovery enable
Depending on occurrence
of overcurrent event and
internal clock phase it is
possible that one recovery
cycle is executed even if
this bit is set to zero.
OUT4-HS
open-load
OUT2 OC
recovery enable
The open-load detection
monitors the load current in
each activated output stage. If
the load current is below the
open-load detection threshold
for at least 1 ms (tdOL) the
corresponding open-load bit
is set. Due to mechanical
/electrical inertia of typical
loads a short activation of the
outputs (e.g. 3ms) can be
used to test the open-load
status without changing the
mechanical/electrical state of
the loads.
OUT3-HS
open-load
OUT1 OC
recovery enable
6
OUT3-LS
open-load
OUT5 PWM
enable
5
4
3
2
1
OUT2-HS
open-load
OUT4 PWM
enable
If the PWM enable bit is
set and the output is
enabled (input register 0)
the output is switched on if
PWM input is high and
switched off if PWM input
is low.
OUT2-LS
open-load
OUT3 PWM
enable
OUT1-HS
open-load
OUT2 PWM
enable
OUT1-LS
open-load
OUT1 PWM
enable
A logical NOR-combination of
all bits 1 to 14 in both status
registers. If bit 14 (Disable
Open-Load) is set, the open-
load status will be ignored
0
1
No error bit
Doc ID 14173 Rev 8
27/36
Packages thermal data
L9951 / L9951XP
5
Packages thermal data
Figure 10. Packages thermal data
28/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Package and packing information
6
Package and packing information
6.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
6.2
PowerSO-36™ package information
Figure 11. PowerSO-36™ package dimensions
Table 21. PowerSO-36™ mechanical data
Millimeters
Typ.
Symbol
Min.
Max.
3.60
0.30
3.30
0.10
0.38
0.32
A
a1
a2
a3
b
0.10
0
0.22
0.23
c
Doc ID 14173 Rev 8
29/36
Package and packing information
L9951 / L9951XP
Table 21. PowerSO-36™ mechanical data (continued)
Millimeters
Typ.
Symbol
Min.
15.80
9.40
Max.
16.00
9.80
D *
D1
E
13.90
10.90
14.5
E1 *
E2
E3
e
11.10
2.90
5.80
6.20
0.65
e3
G
11.05
0
0.10
15.90
1.10
H
15.50
h
L
0.8
1.10
M
N
10 deg
8 deg
R
s
30/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Package and packing information
6.3
PowerSSO-36™ package information
Figure 12. PowerSSO-36™ package dimensions
Table 22. PowerSSO-36™ mechanical data
Millimeters
Symbol
Min.
-
Typ.
Max.
2.45
2.35
0.1
A
A2
a1
b
-
2.15
0
-
-
0.18
0.23
10.10
7.4
-
-
0.36
0.32
10.50
7.6
c
-
D *
E *
e
-
-
0.5
8.5
2.3
-
-
e3
F
-
-
G
-
0.1
0.06
10.5
0.4
G1
H
-
10.1
-
-
-
h
-
k
0°
8°
L
0.55
-
-
-
0.85
10 deg
N
Doc ID 14173 Rev 8
31/36
Package and packing information
L9951 / L9951XP
Table 22. PowerSSO-36™ mechanical data (continued)
Millimeters
Symbol
Min.
4.3
Typ.
Max.
5.2
X
Y
-
-
6.9
7.5
6.4
PowerSO-36™ packing information
Figure 13. PowerSO-36TM tube shipment (no suffix)
32/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Package and packing information
Figure 14. PowerSO-36TM tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
TAPE DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
600
600
330
1.5
A0
B0
K0
K1
F
15.20 0.1
16.60 0.1
3.90 0.1
3.50 0.1
11.50 0.1
24.00 0.1
24.00 0.3
C (±0.2)
D (min)
13
20.2
24.4
60
P1
W
G (+2 / -0)
N (min)
All dimensions are in mm.
T (max)
30.4
Doc ID 14173 Rev 8
33/36
Package and packing information
L9951 / L9951XP
6.5
PowerSSO-36™ packing information
Figure 15. PowerSSO-36TM tube shipment (no suffix)
Base Qty
Bulk Qty
49
1225
532
3.5
C
Tube length (±0.5)
B
A
B
13.8
0.6
C (±0.1)
All dimensions are in mm.
A
Figure 16. PowerSSO-36TM tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
C (±0.2)
F
1000
1000
330
1.5
13
20.2
24.4
100
30.4
G (+2 / -0)
N (min)
T (max)
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 (±0.1)
P
12
D (±0.05)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
1.55
1.5
11.5
2.85
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
No components
500mm min
Top
cover
tape
No components Components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
34/36
Doc ID 14173 Rev 8
L9951 / L9951XP
Revision history
7
Revision history
Table 23. Document revision history
Date
Revision
Description of changes
Mar-2004
1
First issue
Added PowerSO-36™ package information, PowerSO-36™ package
information.
Jun-2005
Jul-2005
Sep-2005
Feb-2006
2
3
4
5
Updated Figure 1.: Block diagram .
Note 1 removal;
Updated Figure 10.: Packages thermal data.
Updated Table 4.: ESD protection.
Document restructured and reformatted.
15-Nov-2007
6
Added PowerSO-36™ packing information and PowerSSO-36™
packing information.
Table 22: PowerSSO-36™ mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F and k rows
24-Jun-2009
7
Table 22: PowerSSO-36™ mechanical data:
– Changed X: minimum value from 4.1 to 4.3 and
maximum value from 4.7 to 5.2
14-May-2010
8
– Changed Y: minimum value from 6.5 to 6.9 and
maximum value from 7.1 to 7.5
Doc ID 14173 Rev 8
35/36
L9951 / L9951XP
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