L9953XP [STMICROELECTRONICS]
Door actuator driver; 门驱动器
| 型号： | L9953XP |
| 厂家： | 
ST |
| 描述： | Door actuator driver |
| 文件： | 总38页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L9953
L9953XP
Door actuator driver
Features
■ One full bridge for 6A load (R =150mΩ)
on
■ Three half bridges for 1.5A load (R =800mΩ)
on
■ One highside driver for 6A load (R =100mΩ)
on
■
Two highside drivers for 1.5A load (Ron=800mΩ)
■ Programmable softstart function to drive loads
with higher inrush currents (i.e. current >6A,
>1.5A)
PowerSSO-36
PowerSO-36
■ Very low current consumption in stand-by
mode (I < 6µA typ; T ≤ 85 °C)
Applications
S
j
■ Door actuator driver with bridges for door lock ,
mirror axis control, mirror fold and highside
driver for mirror defroster and two 10W-light
bulbs.
■ All outputs short circuit protected
■ Current monitor output for highside OUT1,
OUT4, OUT5 and OUT8
■ All outputs over temperature protected
■ Open load diagnostic for all outputs
■ Overload diagnostic for all outputs
■ Separated half bridges for door lock motor
■ PWM control of all outputs
Description
The L9953 and L9953XP are microcontroller
driven multifunctional door actuator driver for
automotive applications. Up to three DC motors
and three grounded resistive loads can be driven
with five half bridges and three highside drivers.
The integrated standard serial peripheral interface
(SPI) controls all operation modes (forward,
reverse, brake and high impedance). All
■ Charge pump output for reverse polarity
protection
diagnostic informations are available via SPI.
Table 1.
Device summary
Package
Order codes
Tape and reel
Tube
PowerSO-36
L9953
L9953TR
PowerSSO-36
L9953XP
L9953XPTR
May 2010
Doc ID 14278 Rev 3
1/38
www.st.com
1
Contents
L9953 / L9953XP
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 20
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20
Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13 Programmable softstart function to drive loads with higher inrush current 21
4
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Contents
4.8
4.9
Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.10 SPI - input data and Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
6
6.1
6.2
6.3
6.4
6.5
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 14278 Rev 3
3/38
List of tables
L9953 / L9953XP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definitions and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Charge pump output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
OUT1 - OUT8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI - input data and Status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4/38
Doc ID 14278 Rev 3
L9953 / L9953XP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI - driver turn-on/off timing, minimum CSN hi time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. PowerSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. PowerSO-36™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. PowerSO-36™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15. PowerSSO-36™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. PowerSSO-36™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 14278 Rev 3
5/38
Block diagram and pin description
L9953 / L9953XP
1
Block diagram and pin description
Figure 1.
Block diagram
V BAT
R everse Polarity
P rotection
* N ote: Value of capacitor has to be choosen carefully to limit the VS voltage below absolute
maximum ratings in case of an unexpected freew heeling condition (e.g. TSD , POR )
*
VS
100µF
OU T1
VC C
C harge
P ump
Mirror C ommon
Mirror V ertical
OU T2
OU T3
M
M
V C C
Mirror H orizontal
D I
** 1k
** 1k
** 1k
** 1k
OU T4
OU T5
OU T6
D O
M
C LK
Lock / Folder
C S N
PW M 1
**1k
OU T7
OU T8
µC
D efroster
MU X
GN D
PW M 2
/ C M
4
**1k
** N ote: R esistors betw een µC and L9953 are recommended to lim it currents
for negative voltage transients at VBAT (e.g. ISO type pulse)
1
Table 2.
Pin
Pin definitions and functions
Symbol
Function
Ground:
Reference potential
GND
1, 18, 19, 36
Important: for the capability of driving the full current at the outputs all
pins of GND must be externally connected.
Highside driver output 8
The output is built by a highside switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy
which can be dissipated is limited. The highside driver is a power
DMOS transistor with an internal parasitic reverse diode from the
output to VS (bulk-drain-diode). The output is over-current and open
load protected.
2, 35
OUT8
Important: for the capability of driving the full current at the outputs both
pins of OUT8 must be externally connected.
Half-bridge-output 1,2,3
The output is built by a highside and a lowside switch, which are
internally connected. The output stage of both switches is a power
DMOS transistor. Each driver has an internal parasitic reverse diode
(bulk-drain-diode: highside driver from output to VS, lowside driver from
GND to output). This output is over-current and open load protected.
OUT1
OUT2
3
4
5
OUT3
6/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Block diagram and pin description
Table 2.
Pin
Pin definitions and functions (continued)
Symbol
Function
Power supply voltage (external reverse protection required)
For this input a ceramic capacitor as close as possible to GND is
recommended.
6, 7, 14, 15,
23, 25, 28, 32
VS
Important: for the capability of driving the full current at the outputs all
pins of VS must be externally connected.
Serial data input
The input requires CMOS logic levels and receives serial data from the
microcontroller. The data is an 24bit control word and the least
significant bit (LSB, bit 0) is transferred first.
8
9
DI
Current monitor output/PWM2 input
Depending on the selected multiplexer bits of Input Data Register this
output sources an image of the instant current through the
corresponding highside driver with a ratio of 1/10.000. This pin is
bidirectional. The microcontroller can overdrive the current monitor
signal to provide a second PWM input for the output OUT7.
CM/PWM2
Chip select not input / test mode
This input is low active and requires CMOS logic levels. The serial data
transfer between L9953 and micro controller is enabled by pulling the
input CSN to low level. If an input voltage of more than 7.5V is applied
to CSN pin the L9953 will be switched into a test mode.
10
11
CSN
DO
Serial data output
The diagnosis data is available via the SPI and this tristate-output. The
output will remain in tristate, if the chip is not selected by the input CSN
(CSN = high)
Logic supply voltage
12
VCC
CLK
For this input a ceramic capacitor as close as possible to GND is
recommended.
Serial clock input
13
This input controls the internal shift register of the SPI and requires
CMOS logic levels.
Half-bridge-output 4,5: see OUT1 (pin 3).
Important: for the capability of driving the full current at the outputs both
pins of OUT4 (OUT5, respectively) must be externally connected.
OUT4
OUT5
16,17, 20,21,
Charge pump output
26
27
CP
This output is provided to drive the gate of an external n-channel power
MOS used for reverse polarity protection
PWM1 input:
PWM1
This input signal can be used to control the drivers OUT1-OUT6 and
OUT8 by an external PWM signal.
Doc ID 14278 Rev 3
7/38
Block diagram and pin description
L9953 / L9953XP
Table 2.
Pin
Pin definitions and functions (continued)
Symbol
Function
Highside driver output 6,7:
Each output is built by a highside switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy
which can be dissipated is limited. Each highside driver is a power
DMOS transistor with an internal parasitic reverse diode from each
output to VS (bulk-drain-diode). Each output is over-current and open
load protected.
31
33
OUT6,
OUT7
22, 24, 29,
30, 34
NC
Not connected pins.
Figure 2.
Configuration diagram (top view)
GND 1
36 GND
OUT8
2
35
34 NC
33
OUT8
OUT1 3
4
OUT7
32 Vs
OUT2
OUT3 5
Vs 6
OUT6
31
30 NC
29 NC
Vs 7
PowerSO-36
8
9
DI
CM / PWM2
28
Vs
PowerSSO-36
CSN 10
DO 11
27 PWM1
26 CP
25 Vs
Vcc 12
24
NC
CLK
13
Vs 14
Vs 15
23 Vs
22 NC
21 OUT5
OUT4 16
OUT4 17
20
19
OUT5
GND
GND
18
8/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document
Table 3.
Absolute maximum ratings
Symbol Parameter
Value
Unit
DC supply voltage
-0.3 to28
40
V
V
V
VS
Single pulse tmax < 400ms
Stabilized supply voltage, logic supply
VCC
-0.3 to 5.5
VDI, VDO, VCLK
,
Digital input / output voltage
-0.3 to VCC + 0.3
V
VCSN, Vpwm1
VCM
VCP
Current monitor output
Charge pump output
Output current
-0.3 to VCC + 0.3
V
V
A
A
-25 to VS + 11
IOUT1,2,3,6,7
IOUT4,5,8
5
Output current
10
2.2
ESD protection
Table 4.
ESD protection
Parameter
Value
Unit
All pins
2(1)
8(2)
kV
kV
Output pins: OUT1 - OUT8
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.
2. HBM with all unzapped pins grounded.
2.3
Thermal data
Table 5.
Symbol
Operating junction temperature
Parameter
Value
Unit
Tj
Operating junction temperature
-40 to 150
°C
Doc ID 14278 Rev 3
9/38
Electrical specifications
L9953 / L9953XP
Typ. Max. Unit
Table 6.
Symbol
Temperature warning and thermal shutdown
Parameter
Min.
Temperature warning threshold junction
temperature
TjTW ON
TjSD ON
TjSD OFF
Tj
130
150
170
°C
°C
Thermal shutdown threshold junction
temperature
Tj
increasing
Thermal shutdown threshold junction
temperature
Tj
150
°C
°K
decreasing
TjSD HYS Thermal shutdown hysteresis
5
2.4
Electrical characteristics
V = 8 to 16V, V = 4.5 to 5.3V, T = - 40 to 150°C, unless otherwise specified.
S
CC
j
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 7.
Symbol
Supply
Parameter
Test condition
Min. Typ. Max. Unit
Operating supply voltage
range
VS
7
28
20
V
VS = 16V, VCC = 5.3V
active mode
VS DC supply current
7
4
mA
OUT1 - OUT8 floating
VS = 16V, VCC = 0V
standby mode
IS
12
µA
OUT1 - OUT8 floating
Ttest = -40°C, 25°C
VS quiescent supply current
VCC DC supply current
T
test = 85°C(1)
6
1
25
3
µA
VS = 16V, VCC = 5.3V
mA
CSN = VCC , active mode
ICC
VS = 16V, VCC = 5.3V
CSN = VCC standby mode
OUT1 - OUT8 floating
VCC quiescent supply
current
25
50
50
µA
µA
VS = 16V, VCC = 5.3V
CSN = VCC
Sum quiescent supply
current
IS + ICC
standby mode
100
OUT1 - OUT8 floating
Ttest = 130°C
1. Guaranteed by design.
10/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Electrical specifications
Min. Typ. Max Unit
Table 8.
Symbol
Overvoltage and under voltage detection
Parameter Test condition
VSUV ON VS UV-threshold voltage
VSUV OFF VS UV-threshold voltage
VSUV hyst VS UV-hysteresis
VS increasing
5.7
5.5
7.2
6.9
V
V
V
V
V
V
V
V
V
VS decreasing
VSUV ON - VSUV OFF
VS increasing
0.5
1
VSOV OFF VS OV-threshold voltage
VSOV ON VS OV-threshold voltage
VSOV hyst VS OV-hysteresis
18
24.5
23.5
VS decreasing
17.5
VSOV OFF - VSOV ON
VCC increasing
VPOR OFF Power-On-reset threshold
VPOR ON Power-On-reset threshold
VPOR hyst Power-On-reset hysteresis
4.4
VCC decreasing
VPOR OFF - VPOR ON
3.1
0.3
Table 9.
Symbol
Current monitor output
Parameter
Test condition
Min.
Typ.
Max
Unit
VCM
Functional voltage range VCC = 5V
0
4
V
Current monitor output
ratio:
1
-----------------
ICM,r
0V ≤ VCM ≤ 4V, VCC=5V
-
-
10.000
ICM / IOUT1,4,5,8
0 V ≤ VCM ≤ 3.8V,
CC = 5V, IOut,min=500mA,
V
4% +
1%FS 2%FS
8% +
ICM acc Current monitor accuracy
IOut max = 6A
(FS = full scale= 600μA)
Table 10. Charge pump output
Symbol
Parameter
Test condition
Min.
Typ.
Max
Unit
VS = 8V, ICP = -60µA
VS = 10V, ICP = -80µA
VS ≥ 12V, ICP = -100µA
VS+6
VS+8
VS+13
VS+13
VS+13
V
V
V
Charge pump output
voltage
VCP
VS+10
Charge pump output
current
ICP
VCP = VS+10V, VS =13.5V
95
150
300
µA
Doc ID 14278 Rev 3
11/38
Electrical specifications
L9953 / L9953XP
Table 11.
Symbol
OUT1 - OUT8
Parameter
Test condition
Min.
Typ.
Max
Unit
VS = 13.5 V, Tj = 25 °C,
800
1100
mΩ
rON OUT1,
rON OUT2
IOUT1,2,3
VS = 13.5 V, Tj = 125 °C,
IOUT1,2,3 0.8 A
VS = 13.5 V, Tj = 25 °C,
IOUT4,5 3 A
VS = 13.5 V, Tj = 125 °C,
IOUT4,5 3 A
=
0.8A
On-resistance to supply
or GND
rON OUT3
1250
150
225
500
700
100
150
1700
200
300
700
950
150
200
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
=
=
rON OUT4, On-resistance to supply
rON OUT5 or GND
=
VS = 13.5 V, Tj = 25 °C,
IOUT6,7 = − 0.8A
rON OUT6,
On-resistance to supply
rON OUT7
VS = 13.5 V, Tj = 125 °C,
IOUT6,7 = −0.8 A
VS = 13.5 V, Tj = 25 °C,
IOUT8 = -3 A
rON OUT8 On-resistance to supply
VS = 13.5 V, Tj = 125 °C,
IOUT8 = -3 A
IOUT1
Output current limitation
to GND
IOUT2
Source, VS=13.5 V
Sink, VS=13.5 V
-3.0
1.5
-1.5
3.0
A
A
IOUT3
IOUT1
Output current limitation
to supply
IOUT2
IOUT3
IOUT4
IOUT5
IOUT4
IOUT5
IOUT6
IOUT7
Output current limitation
to GND
Source, VS=13.5 V
Sink, VS=13.5 V
-10.5
6
-6
10.5
-1.5
-6
A
A
A
A
Output current limitation
to supply
Output current limitation
to GND
Source, VS=13.5 V
-3.0
-10.5
Output current limitation
to GND
IOUT8
td ON H
td OFF H
td ON L
td OFF L
Source, VS=13.5 V
VS=13.5 V,
Output delay time,
highside driver on
20
50
15
60
40
150
30
80
300
70
µs
µs
µs
µs
corresponding lowside
driver is not active
Output delay time,
highside driver off
VS=13.5 V
VS=13.5 V,
Output delay time,
lowside driver on
corresponding highside
driver is not active
Output delay time,
lowside driver off
VS=13.5 V
100
200
12/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Electrical specifications
Table 11.
OUT1 - OUT8 (continued)
Parameter
Symbol
Test condition
Min.
Typ.
Max
Unit
Cross current protection
time, source to sink
(1)
CC ONLS_OFFHS d OFF H
td HL
t
t
- t
200
400
µs
Cross current protection
time, sink to source
(1)
CC ONHS_OFFLS d OFF L
td LH
- t
200
400
µs
VOUT1-8=0V, standby
mode
Switched-off output
current highside drivers of
OUT1-8
0
-2
-5
0
µA
µA
µA
µA
IQLH
VOUT1-8=0V, active mode
-40
0
-15
80
VOUT1-5= VS, standby
mode
Switched-off output
current lowside drivers of
OUT1-5
120
0
IQLL
VOUT1-5= VS, active mode
-40
-15
Open load detection
IOLD123 current of OUT1, OUT2
and OUT3
Source and sink
15
60
40
60
mA
mA
Open load detection
IOLD45 current of OUT4 and
OUT5
Source and sink
150
300
Open load detection
IOLD67 current of OUT6 and
OUT7
Source
Source
15
30
40
60
mA
mA
µs
Open load detection
IOLD8
150
300
current of OUT8
Minimum duration of
td OL
open load condition to set
the status bit
500
3000
Minimum duration of
over-current condition to
switch off the driver
tISC
10
2
100
8
µs
Recovery frequency for
OC recovery duty cycle
bit=0
frec0
kHz
kHz
Recovery frequency for
OC recovery duty cycle
bit=1
frec1
3
16
dV
/dt
/dt
VS =13.5 V
Slew rate of OUT123 and
OUT 67
OUT123
0.08
0.08
0.08
0.2
0.2
0.2
0.4
0.4
0.4
V/µs
V/µs
V/µs
dV
Rload = 16.8 Ω
OUT67
VS =13.5 V
Slew rate of OUT4 and
OUT5
dV
/dt
OUT45
Rload = 4.5 Ω
VS =13.5 V
dV
/dt Slew rate of OUT8
OUT8
Rload = 4.5 Ω
1. tCC ON is the switch on delay time td ON if complement in half bridge has to switch Off.
Doc ID 14278 Rev 3
13/38
Electrical specifications
L9953 / L9953XP
2.5
SPI - electrical characteristics
(V = 8 to 16V, V = 4.5 to 5.3V, T = - 40 to 150°C, unless otherwise specified. The
S
CC
j
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin).
Table 12. Delay time from standby to active mode
Symbol
Parameter
Test condition
Min. Typ.
Max.
Unit
Switching from standby to active mode.
Time until output drivers are enabled
tset
Delay time
160
300
µs
Table 13. Inputs: CSN, CLK, PWM1/2 and DI
Symbol
Parameter
Input low level
Input high level
Test condition
Min. Typ.
Max.
Unit
VinL
VinH
VCC = 5V
VCC = 5V
1.5
2.0
3.0
V
V
3.5
VinHyst Input hysteresis
VCC = 5V
0.5
-40
10
V
ICSN in Pull up current at input CSN
ICLK in Pull down current at input CLK
VCSN = 3.5V VCC = 5V
VCLK = 1.5V
VDI = 1.5V
-20
25
25
-5
50
50
µA
µA
µA
IDI in
Pull down current at input DI
10
Pull down current at input
PWM1
IPWM1 in
V
PWM = 1.5V
10
25
10
50
15
µA
pF
Input capacitance at input
CSN, CLK, DI and PWM1/2
(1)
Cin
0 V < VCC < 5.3V
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
(1)
Table 14. DI timing
Symbol
Parameter
Clock period
Test condition
Min. Typ.
Max.
Unit
tCLK
tCLKH
tCLKL
VCC = 5V
VCC = 5V
VCC = 5V
1000
400
ns
ns
ns
Clock high time
Clock low time
400
CSN setup time, CSN low
before rising edge of CLK
tset CSN
VCC = 5V
VCC = 5V
400
400
ns
ns
CLK setup time, CLK high
before rising edge of CSN
tset CLK
tset DI
DI setup time
VCC = 5V
VCC = 5V
200
200
ns
ns
thold time DI hold time
Rise time of input signal DI,
tr in
VCC = 5V
VCC = 5V
100
100
ns
ns
CLK, CSN
Fall time of input signal DI,
CLK, CSN
tf in
1. DI timing parameters tested in production by a passed / failed test:
Tj= -40°C / +25°C: SPI communication @ 2MHz.
Tj= +125°C
SPI communication @ 1.25 MHz.
14/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Electrical specifications
Table 15. DO
Symbol
Parameter
Test condition
Min.
Typ.
Max. Unit
VDOL
VDOH
Output low level
Output high level
VCC = 5 V, ID = -2mA
VCC = 5 V, ID = 2 mA
0.2
0.4
V
V
VCC -0.4 VCC-0.2
-10
V
CSN = VCC
0V < VDO < VCC
VCSN = VCC
0V < VCC < 5.3V
,
IDOLK
Tristate leakage current
10
15
µA
pF
,
Tristate input
capacitance
(1)
CDO
10
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16. DO timing
Symbol
Parameter
DO rise time
Test condition
Min. Typ. Max. Unit
tr DO
tf DO
CL = 100 pF, Iload = -1mA
CL = 100 pF, Iload = 1mA
CL = 100 pF, Iload = 1mA
80
50
140
100
ns
ns
DO fall time
DO enable time
ten DO tri L
tdis DO L tri
ten DO tri H
tdis DO H tri
td DO
100
380
100
380
50
250
450
250
450
250
ns
ns
ns
ns
ns
from tristate to low level pull-up load to VCC
DO disable time CL = 100 pF, Iload = 4 mA
from low level to tristate pull-up load to VCC
DO enable time CL =100 pF, Iload = -1mA
from tristate to high level pull-down load to GND
DO disable time CL = 100 pF, Iload = -4mA
from high level to tristate pull-down load to GND
DO < 0.3 VCC, VDO > 0.7VCC
CL = 100pF
V
,
DO delay time
Table 17. CSN timing
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
CSN HI time, switching from Transfer of SPI-command
tCSN_HI,stb
20
4
µs
µs
standby mode
to Input Register
Transfer of SPI-command
to input register
tCSN_HI,min CSN HI time, active mode
Doc ID 14278 Rev 3
15/38
Electrical specifications
Figure 3.
L9953 / L9953XP
SPI - transfer timing diagram
CSN high to low: DO enabled
CSN
CLK
DI
time
0
0
1
X
18 19 20 21 22 23
0
1
2
3
4
5
6
7
X
time
DI: data will be accepted on the rising edge of CLK signal
1
0
1
1
2
3
4
5
6
7
X
X
18 19 20 21 22 23
DO: data will change on the falling edge of CLK signal
time
0
2
3
4
5
6
7
0
1
DO
X
X
18 19 20 21 22 23
time
CSN low to high: actual data is
transfered to output power switches
fault bit
Input
Data
Register
old data
new data
time
Figure 4.
SPI - input timing
0.8 VCC
0.2 VCC
CSN
t
t
t
set CLK
set CSN
CLKH
0.8 VCC
0.2 VCC
CLK
t
t
t
CLKL
set DI
hold DI
0.8 VCC
0.2 VCC
DI
Valid
Valid
16/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Electrical specifications
Figure 5.
SPI - DO valid data delay time and valid time
tf in
tr in
0.8 VCC
0.5 VCC
0.2 VCC
CLK
tr DO
DO
(low to high)
0.8 VCC
0.2 VCC
td DO
tf DO
0.8 VCC
0.2 VCC
DO
(high to low)
Figure 6.
SPI - DO enable and disable time
tf in
tr in
0.8 VCC
50%
CSN
0.2 VCC
DO
50%
pull-up load to VCC
C
L
= 100 pF
ten DO tri L
tdis DO L tri
DO
50%
pull-down load to GND
= 100 pF
C
L
ten DO tri H
tdis DO H tri
Doc ID 14278 Rev 3
17/38
Electrical specifications
Figure 7.
L9953 / L9953XP
SPI - driver turn-on/off timing, minimum CSN hi time
CSN low to high: data from shift register
is transferred to output power switches
tr in
tf in
tCSN_HI,min
80%
50%
20%
CSN
tdOFF
80%
50%
20%
output current
of a driver
ON state
OFF state
tOFF
tON
tdON
80%
50%
20%
output current
of a driver
OFF state
ON state
Figure 8.
SPI - timing of status bit 0 (fault condition)
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
CSN
CLK
time
time
DI
time
DI: data is not accepted
0
-
DO
time
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
18/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Application information
3
Application information
3.1
Dual power supply: VS and VCC
The power supply voltage V supplies the half bridges and the highside drivers. An internal
S
charge-pump is used to drive the highside switches. The logic supply voltage V (stabilized
CC
5 V) is used for the logic part and the SPI of the device.
Due to the independent logic supply voltage the control and status information will not be
lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-
on (V increases from under voltage to V
= 4.2 V) the circuit is initialized by an
CC
POR OFF
internally generated power-on-reset (POR). If the voltage V decreases under the
CC
minimum threshold (V
= 3.4 V), the outputs are switched to tristate (high impedance)
POR ON
and the status registers are cleared.
3.2
3.3
Standby mode
The standby mode of the L9953 is activated by clearing the bit 23 of the Input Data Register
0. All latched data will be cleared and the inputs and outputs are switched to high
impedance. In the standby mode the current at V (V ) is less than 6 µA (50µA) for
CSN = high (DO in tristate). By switching the V voltage a very low quiescent current can
be achieved. If bit 23 is set, the device will be switched to active mode.
S
CC
CC
Inductive loads
Each half bridge is built by an internally connected highside and a lowside power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs OUT1 to OUT5 without external free-wheeling diodes. The highside
drivers OUT6 to OUT8 are intended to drive resistive loads. Hence only a limited energy
(E<1mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For
inductive loads (L>100μH) an external free-wheeling diode connected to GND and the
corresponding output is needed.
3.4
Diagnostic functions
All diagnostic functions (over/open load, power supply over-/under voltage, temperature
warning and thermal shutdown) are internally filtered and the condition has to be valid for at
least 32 µs (open load: 1ms, respectively) before the corresponding status bit in the status
registers will be set. The filters are used to improve the noise immunity of the device. Open
load and temperature warning function are intended for information purpose and will not
change the state of the output drivers. On contrary, the overload condition will disable the
corresponding driver (over-current) and over temperature will switch off all drivers (thermal
shutdown). Without setting the over-current recovery bits in the Input Data register, the
microcontroller has to clear the over-current status bits to reactivate the corresponding
drivers.
Doc ID 14278 Rev 3
19/38
Application information
L9953 / L9953XP
3.5
Overvoltage and under voltage detection
If the power supply voltage V rises above the overvoltage threshold V
(typical 21
S
SOV OFF
V), the outputs OUT1 to OUT8 are switched to high impedance state to protect the load.
When the voltage V drops below the under voltage threshold V (UV-switch-OFF
S
SUV OFF
voltage), the output stages are switched to the high impedance to avoid the operation of the
power devices without sufficient gate driving voltage (increased power dissipation). If the
supply voltage V recovers to normal operating voltage the outputs stages return to the
S
programmed state (input register 0: bit 20=0).
If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the
drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the
drivers. It is recommended to set bit 20 to avoid a possible high current oscillation in case of
a shorted output to GND and low battery voltage.
3.6
3.7
Charge pump
The charge pump runs under all conditions in normal mode. In standby the charge pump is
disabled.
Temperature warning and thermal shutdown
If junction temperature rises above T
a temperature warning flag is set and is detectable
j TW
via the SPI. If junction temperature increases above the second threshold T , the thermal
j SD
shutdown bit will be set and power DMOS transistors of all output stages are switched off to
protect the device. Temperature warning flag and thermal shutdown bit are latched and must
be cleared by the microcontroller. The related bit is only cleared if the temperature
decreases below the trigger temperature. If the thermal shutdown bit has been cleared the
output stages are reactivated.
3.8
3.9
Open load detection
The open load detection monitors the load current in each activated output stage. If the load
current is below the open load detection threshold for at least 1 ms (t
open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3ms) can be used to test the open load status without
changing the mechanical/electrical state of the loads.
) the corresponding
dOL
Over load detection
In case of an over-current condition a flag is set in the status register in the same way as
open load detection. If the over-current signal is valid for at least t
= 32 µs, the over-
ISC
current flag is set and the corresponding driver is switched off to reduce the power
dissipation and to protect the integrated circuit. If the over-current recovery bit of the output
is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
20/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Application information
3.10
Current monitor
The current monitor output sources a current image at the current monitor output which has
a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. The bits
18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4, OUT5,
and OUT8 will be multiplexed to the current monitor output. The current monitor output
allows a more precise analysis of the actual state of the load rather than the detection of an
open- or overload condition. For example this can be used to detect the motor state
(starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster
more precise by measuring the load current. The current monitor output is bidirectional (c.f.
PWM inputs).
3.11
3.12
PWM inputs
Each driver has a corresponding PWM enable bit which can be programmed by the SPI
interface. If the PWM enable bit in Input Data Register 1 is set, the output is controlled by the
logically AND-combination of the PWM signal and the output control bit in Input Data
Register 0. The outputs OUT1-OUT6 and OUT8 are controlled by the PWM1 input and the
output OUT7 is controlled by the bidirectional input CM/PMW2. For example, the two PWM
inputs can be used to dim two lamps independently by external PWM signals.
Cross-current protection
The six half-bridges of the device are cross-current protected by an internal delay time. If
one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge
will be automatically delayed by the cross-current protection time. After the cross-current
protection time is expired the slew-rate limited switch-off phase of the driver will be changed
to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to
this behavior it is always guaranteed that the previously activated driver is totally turned-off
before the opposite driver will start to conduct.
3.13
Programmable softstart function to drive loads with higher
inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable softstart function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device will automatically switch-
on the outputs again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to be about 12% or 25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition. The PWM frequency settles at 3kHz or
6kHz. The device itself cannot distinguish between a real overload and a non linear load like
a light bulb. A real overload condition can only be qualified by time. As an example the
microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first
50ms. After clearing the recovery bit the output will be automatically disabled if the overload
condition still exits.
Doc ID 14278 Rev 3
21/38
Application information
Figure 9.
L9953 / L9953XP
Example of programmable softstart function for inductive loads
22/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Functional description of the SPI
4
Functional description of the SPI
4.1
Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be
driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and
CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible
output pins and one input pin will be needed to communicate with the device. A fault
condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the
status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers
0 and 1. The microcontroller can poll the status of the device without the need of a full SPI-
communication cycle.
Note:
In contrast to the SPI-standard the least significant bit (LSB) will be transferred first
(see Figure 3).
4.2
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started. The state when CSN is going low until the rising
edge of CSN will be called a communication frame. If the CSN-input pin is driven above
7.5V, the L9953 will go into a test mode. In the test mode the DO will go from tri-state to
active mode.
4.3
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register. The writing to the selected Data Input Register is only enabled if exactly
24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame will be ignored. This safety function
is implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
Doc ID 14278 Rev 3
23/38
Functional description of the SPI
L9953 / L9953XP
4.4
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
4.5
4.6
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
Input data register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of
the two Input Registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register will be written to the selected Input Data
Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents
of the selected status register will be transferred to DO during the current communication
frame. Bit 1-17 controls the behavior of the corresponding driver.
If bit 23 is zero, the device will go into the standby-mode. The bits 18 and 19 are used to
control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status
registers. The bits in the status registers will be cleared after the current communication
frame (rising edge of CSN).
4.7
4.8
24/38
Status register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is
used as a fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The
state of this bit can be polled by the microcontroller without the need of a full SPI-
communication cycle. If one of the over-current bits is set, the corresponding driver will be
disabled. If the over-current recovery bit of the output is not set the microcontroller has to
clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers
will go into a high impedance state. Again the microcontroller has to clear the bit to enable
the drivers.
Scan mode
The Scan Mode can be entered by rising the PWM1 input to a voltage higher than 9.5V.
Doc ID 14278 Rev 3
L9953 / L9953XP
Functional description of the SPI
4.9
Test mode
The Test Mode can be entered by rising the CSN input to a voltage higher than 9.5V. In the
test mode the inputs CLK, DI, PWM1/2, the internal 2MHz CLK, OL and OC can be
multiplexed to output DO and Iref, Tsens1-4 and Vbgp can be multiplexed to input
CM/PWM2.
Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at
lower current.
The internal logic prevents that the High-Side and Low-Side driver of the same half-bridge
can be switched-on at the same time. In the test mode this combination is used to multiplex
the desired signals according to following table:
Table 18. Test mode
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6
PWM PWM PWM PWM PWM PWM
1 EN 1 EN 1 EN 1 EN 1 EN 1 EN
DO
LS3
HS3
LS4
HS4
LS5
HS5
Test Pad
! (both HI)
both HI
! (both HI)
! (both HI)
both HI
! (both HI)
! (both HI)
! (both HI)
! (both HI)
both HI
NoError
DI
! (both HI)
both HI
! (both HI)
! (both HI)
both HI
! (both HI)
! (both HI)
! (both HI)
! (both HI)
both HI
5µA Iref
Tsens1
Tsens2
Tsens3
Tsens4
x
! (both HI)
both HI
CLK
! (both HI)
both HI
both HI
INT_CLK
PWM1
PWM2
OL
both HI
! (both HI)
both HI
! (both HI)
! (both HI)
both HI
! (both HI)
both HI
! (both HI)
! (both HI)
both HI
both HI
both HI
! (both HI)
both HI
both HI
! (both HI)
both HI
both HI
x
both HI
both HI
OC
both HI
both HI
Vbandgap
Doc ID 14278 Rev 3
25/38
Functional description of the SPI
L9953 / L9953XP
4.10
SPI - input data and Status registers
Table 19. SPI - input data and Status registers 0
Input register 0 (write)
Bit
Status register 0 (read)
Name
Comment
Name
Comment
If Enable Bit is set the
device will be switched in
active mode. If Enable Bit
is cleared the device go
into standby mode and all
bits are cleared. After
power-on reset device
starts in standby mode.
A broken VCC-or SPI-
connection of the L9953 can
be detected by the
microcontroller, because all 24
bits low or high is not a valid
frame.
23
Enable bit
Always 1
If Reset Bit is set both
status registers will be
cleared after rising edge of
CSN input.
In case of an overvoltage or
undervoltage event the
22
21
Reset bit
VS overvoltage
VS undervoltage
corresponding bit is set and
the outputs are deactivated. If
VS voltage recovers to normal
operating conditions outputs
are reactivated automatically
(if Bit 20 of status register 0 is
not set).
OC recovery This bit defines in
duty cycle
combination with the over-
current recovery bit (Input
Register 1) the duty cycle
in over-current condition of
an activated driver.
0: 12% 1: 25%
If this bit is set the
microcontroller has to
clear the status register
after
undervoltage/overvoltage
event to enable the
outputs.
In case of a thermal shutdown
all outputs are switched off.
Overvoltage/Un
dervoltage
recovery
Thermal
shutdown
The microcontroller has to
clear the TSD bit by setting the
Reset Bit to reactivate the
outputs.
20
19
disable
Depending on
This TW bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.
combination of bit 18 and
19 the current image
(1/10.000) of the selected
HS-output will be multi-
plexed to the CM output:
Temperature
warning
Bit
19
Bit
18
After switching the device from
standby mode to active mode
an internal timer is started to
allow charge pump to settle
before the outputs can be
activated. This bit is cleared
automatically after start up
time has finished. Since this bit
is controlled by internal clock it
can be used for synchronizing
testing events (e.g. measuring
filter times).
Output
Currentmonitor
select bits
0
1
0
1
0
0
1
1
OUT8
OUT1
OUT5
OUT4
18
Not ready bit
26/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Functional description of the SPI
Table 19. SPI - input data and Status registers 0 (continued)
Input register 0 (write)
Status register 0 (read)
Name Comment
Bit
Name
Comment
OUT8 – HS
on/off
OUT8 – HS
over-current
17
16
15
x (don’t care)
0
OUT7 – HS
on/off
OUT7 – HS
over-current
If a bit is set the selected
output driver is switched
on. If the corresponding
PWM enable bit is set
OUT6 – HS
on/off
OUT6 – HS
over-current
14
(Input Register 1) the
driver is only activated if
PWM1 (PWM2) input
13
12
11
x (don’t care)
x (don’t care)
x (don’t care)
0
0
In case of an over-current
event the corresponding status
bit is set and the output driver
is disabled. If the over-current
Recovery Enable bit is set
(Input Register 1) the output
will be automatically
reactivated after a delay time
resulting in a PWM modulated
current with a programmable
duty cycle (Bit 21).
signal is high. The outputs
of OUT1-OUT5 are half
bridges. If the bits of HS-
and LS-driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
avoid a high internal
current from VS to GND.
In test mode (CSN>9.5V)
this bit combinations are
used to multiplex internal
signals to the DO-output.
OUT5 – HS
on/off
OUT5 – HS
over-current
10
9
8
7
6
5
4
3
2
1
OUT5 – LS
on/off
OUT5 – LS
over-current
OUT4 – HS
on/off
OUT4 – HS
over-current
OUT4 – LS
on/off
OUT4 – LS
over-current
If the over-current recovery bit
is not set the microcontroller
has to clear the over-current
bit (Reset Bit) to reactivate the
output driver.
OUT3 – HS
on/off
OUT3 – HS
over-current
OUT3 – LS
on/off
OUT3 – LS
over-current
LS3 HS3 LS4 HS4 LS5 HS5 CM/PWM2
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
0
1
1
5µA Iref
Tsens1
Tsens2
Tsens3
Tsens4
Vbgp
OUT2 – HS
on/off
OUT2 – HS
over-current
OUT2 – LS
on/off
OUT2 – LS
over-current
OUT1 – HS
on/off
OUT1 – HS
over-current
OUT1 – LS
on/off
OUT1 – LS
over-current
A logical NOR-combination of
all bits 1 to 22 in both status
registers.
0
0
No error bit
Doc ID 14278 Rev 3
27/38
Functional description of the SPI
L9953 / L9953XP
Table 20. SPI - input data and status registers 1
Input register 1 (write)
Status register 1 (read)
Bit
Name
Comment
Name
Comment
If Enable bit is set the device
will be switched in active mode.
If Enable Bit is cleared device
goes into standby mode and all
bits are cleared. After power-
on reset device starts in
standby mode.
A broken VCC-or SPI-
connection of the L9953
can be detected by the
microcontroller, because
all 24 bits low or high is
not a valid frame.
23
Enable bit
Always 1
OUT8 OC
Recovery
Enable
In case of an overvoltage
or under voltage event
the corresponding bit is
set and the outputs are
deactivated. If Vs voltage
recovers to normal
operating conditions
outputs are reactivated
automatically.
22
21
VS overvoltage
VS undervoltage
0 / 1
In case of a thermal
shutdown all outputs are
switched off. The
OUT7 OC
Recovery
Enable
In case of an over-current
20
19
Thermal shutdown microcontroller has to
clear the TSD bit by
event the over-current status
bit (Status Register 0) is set
and the output is switched off.
If the over-current Recovery
Enable bit is set the output will
be automatically reactivated
after a delay time resulting in a
PWM modulated current with a
programmable duty cycle (Bit
21 of Input Data Register 0).
Depending on occurrence of
Overturned Event and internal
clock phase it is possible that
one recovery cycle is executed
even if this bit is set to zero.
setting the Reset Bit to
reactivate the outputs.
The TW bit can be used
for thermal management
by the microcontroller to
avoid a thermal
shutdown. The
OUT6 OC
Recovery
Enable
Temperature
warning
microcontroller has to
clear the TW bit.
After switching the
device from standby
mode to active mode an
internal timer is started
to allow charge pump to
settle before the outputs
can be activated. This bit
is only present during
start up time
18
0 / 1
Not ready bit
Since this bit is
controlled by internal
clock it can be used for
synchronizing testing
events(e.g. measuring
filter times).
28/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Functional description of the SPI
Table 20. SPI - input data and status registers 1 (continued)
Input register 1 (write)
Status register 1 (read)
Bit
17
16
Name
Comment
Name
Comment
OUT8 – HS
open load
OUT5 OC
Recovery
Enable
0
OUT4 OC
Recovery
Enable
OUT7 – HS
open load
15
14
13
12
After 50ms the bit can be
cleared. If over-current
condition still exists, a wrong
load can be assumed.
OUT3 OC
Recovery
Enable
OUT6 – HS
open load
OUT2 OC
Recovery
Enable
0
The open load detection
monitors the load current
in each activated output
stage. If the load current
is below the open load
detection threshold for at
least 1 ms (tdOL) the
corresponding open load
bit is set. Due to
mechanical/electrical
inertia of typical loads a
short activation of the
outputs (e.g. 3ms) can
be used to test the open
load status without
OUT1 OC
Recovery
Enable
0
0
OUT8 PWM1
Enable
11
10
9
OUT5 – HS
open load
0 / 1
If the PWM1/2 Enable Bit is set
and the output is enabled
(Input Register 0) the output is
switched on if PWM1/2 input is
high and switched off if
PWM1/2 input is low. OUT7 is
controlled by PWM2 input. All
other outputs are controlled by
PWM1 input. For test mode
rise CSN>9.5 V.
OUT5 – LS
open load
OUT7 PWM2
Enable
OUT4 – HS
open load
OUT6 PWM1
Enable
8
OUT4 – LS
open load
changing the
mechanical/electrical
state of the loads.
7
0 / 1
0 / 1
OUT3 – HS
open load
6
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 DO
OUT3 – LS
open load
OUT5 PWM1
Enable
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
0
0
0
No error
5
Di
CLK
1
0
0
OUT2 –HS
open load
OUT4 PWM1
Enable
4
CLK 2MHz
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
PWM1
PWM2
OL
OUT2– LS
open load
OUT3 PWM1
Enable
3
1
OC
OUT1 – HS
open load
OUT2 PWM1
Enable
2
OUT1 – LS
open load
OUT1 PWM1
Enable
1
A logical NOR-
combination of all bits 1
to 22 in both status
registers.
0
1
No Error bit
Doc ID 14278 Rev 3
29/38
Packages thermal data
L9953 / L9953XP
5
Packages thermal data
Figure 10. Packages thermal data
30/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Package and packing information
6
Package and packing information
6.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
6.2
PowerSO-36™ package information
Figure 11. PowerSO-36™ package dimensions
Doc ID 14278 Rev 3
31/38
Package and packing information
L9953 / L9953XP
Table 21. PowerSO-36™ mechanical data
Millimeters
Typ.
Symbol
Min.
Max.
3.60
0.30
3.30
0.10
0.38
0.32
16.00
9.80
14.5
11.10
2.90
6.20
A
a1
a2
a3
b
0.10
0
0.22
0.23
15.80
9.40
13.90
10.90
c
D *
D1
E
E1 *
E2
E3
e
5.80
0.65
e3
G
11.05
0
0.10
15.90
1.10
H
15.50
h
L
0.8
1.10
M
N
10 deg
8 deg
R
s
32/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Package and packing information
6.3
PowerSSO-36™ package information
Figure 12. PowerSSO-36™ package dimensions
Table 22. PowerSSO-36™ mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
2.45
2.35
0.1
A
A2
a1
b
-
-
2.15
-
0
-
0.18
-
0.36
0.32
10.50
7.6
c
0.23
-
D *
E *
e
10.10
-
7.4
-
-
0.5
-
e3
F
-
8.5
-
-
2.3
-
G
-
-
-
-
-
-
-
-
0.1
G1
H
-
10.1
-
0.06
10.5
0.4
h
k
0°
8°
L
0.55
-
0.85
10 deg
N
Doc ID 14278 Rev 3
33/38
Package and packing information
L9953 / L9953XP
Table 22. PowerSSO-36™ mechanical data (continued)
Millimeters
Symbol
Min.
4.3
Typ.
Max.
5.2
X
Y
-
-
6.9
7.5
6.4
PowerSO-36™ packing information
Figure 13. PowerSO-36™ tube shipment (no suffix)
34/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Package and packing information
Figure 14. PowerSO-36™ tape and reel shipment (suffix “TR”)
TAPE DIMENSIONS
REEL DIMENSIONS
A0
B0
K0
K1
F
15.20 0.1
Base Qty
Bulk Qty
A (max)
B (min)
600
600
330
1.5
16.60 0.1
3.90 0.1
3.50 0.1
11.50 0.1
24.00 0.1
24.00 0.3
C (±0.2)
D (min)
13
P1
W
20.2
24.4
60
G (+2 / -0)
N (min)
All dimensions are in mm.
T (max)
30.4
Doc ID 14278 Rev 3
35/38
Package and packing information
L9953 / L9953XP
6.5
PowerSSO-36™ packing information
Figure 15. PowerSSO-36™ tube shipment (no suffix)
Base Qty
Bulk Qty
49
1225
532
3.5
C
Tube length (±0.5)
B
A
B
13.8
0.6
C (±0.1)
All dimensions are in mm.
A
Figure 16. PowerSSO-36™ tape and reel shipment (suffix “TR”)
Reel dimensions
Base Qty
Bulk Qty
A (max)
B (min)
C (±0.2)
F
1000
1000
330
1.5
13
20.2
24.4
100
30.4
G (+2 / -0)
N (min)
T (max)
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 (±0.1)
P
12
D (±0.05)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
1.55
1.5
11.5
2.85
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
No components
500mm min
Top
cover
tape
No components Components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
36/38
Doc ID 14278 Rev 3
L9953 / L9953XP
Revision history
7
Revision history
Table 23. Document revision history
Date
Revision
Description of changes
23-Jan-2008
1
Initial release.
Table 22: PowerSSO-36™ mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F and k rows
24-Jun-2009
14-May-2010
2
3
Table 22: PowerSSO-36™ mechanical data:
– Changed X: minimum value from 4.1 to 4.3 and
maximum value from 4.7 to 5.2
– Changed Y: minimum value from 6.5 to 6.9 and
maximum value from 7.1 to 7.5
Doc ID 14278 Rev 3
37/38
L9953 / L9953XP
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2010 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
38/38
Doc ID 14278 Rev 3
相关型号：
©2020 ICPDF网 联系我们和版权申明