L9952XP_技术文档

L9952GXP

Power management system IC

Features

■ Two 5V low-drop voltage regulators (250mA,

100mA continuous mode

■ Low stand-by current: V

stby, 7µA; V stby,

, 1

BAT

45µA, (75µA in cycl. sense)

■ Window watchdog and fail-safe output

■ Interrupt output

PowerSSO-36

■ Wake-up logic with cyclic contact monitoring

■ LIN 2.1 compliant (SAEJ2602 compatible)

transceiver

Applications

■ 24 bit SPI interface for mode control and

■ Automotive ECU’ s such as door zone and

diagnostic

body control modules.

■ Output drivers

Description

■ 4 High side drivers for e.g. LED or HALL

(R

= 7 Ω )

DSon,typ

The L9952GXP is a power management system

IC containing two low drop regulators with

advanced contact monitoring and additional

peripheral functions.

■ 1 High side driver Out_HS ( R

= 1 Ω )

DSon,typ

■ 2 Relay drivers ( R

= 2 Ω )

DSon,typ

■ Outputs are short circuit protected

The integrated standard serial peripheral interface

(SPI) controls all L9952GXP operation modes

and provides driver diagnostic functions.

■ 2 Op amp's for current sensing in GND return

lines

■ Temperature warning and thermal shutdown

Table 1.

Device summary

Package

Order codes

Tape and reel

Tube

PowerSSO-36

L9952GXP

L9952GXPTR

July 2009

Doc ID 13518 Rev 5

1/68

www.st.com

1

Contents

L9952GXP

Contents

1

2

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.1

2.1.2

Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2

Power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.1

2.2.2

2.2.3

2.2.4

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

V1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

VBAT standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Wake up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Wake up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Hall sensor ports: WU3,4, Dig_Out 3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Window – watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.10 Fail safe output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.11 Reset – generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.12 V1, V2 fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.13 Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.14 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.15 Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.16 LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.17 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.17.1 Dominant TxD time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.17.2 Short to battery time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.17.3 Short to ground mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.18 Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.18.1 Normal wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.18.2 Wake up from short to GND condition . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/68

Doc ID 13518 Rev 5

L9952GXP

Contents

2.18.3 RxD pin in V1 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.19 LINPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.20 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.20.1 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.20.2 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.20.3 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.20.4 Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.20.5 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3

Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1

Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.1

3.1.2

Over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2

3.3

3.4

3.5

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 25

SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

High side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4

5

6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1

6.2

6.3

Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 30

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Reset generator (V1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 13518 Rev 5

3/68

Contents

L9952GXP

7.8

7.9

High side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.8.1

7.8.2

Output (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Outputs (OUT1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.10 Wake up inputs ( WU1..WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.11 Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.12 LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.13 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.14 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.14.1 Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.14.2 Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.14.3 Input PWM 2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.14.4 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.14.5 DO, FSO, Dig_Out3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.14.6 DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.14.7 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8

SPI control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.1

SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.1

9.2

9.3

ECOPACK^®packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4/68

Doc ID 13518 Rev 5

L9952GXP

List of tables

Table 1.

Table 2.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pins definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Power-on Reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Voltage regulator V1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Voltage regulator V2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Reset generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

High side outputs (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

High side outputs (OUT 1..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Relay drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Wake up inputs(WU1...WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

LIN receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

LIN DC parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

LIN transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

LIN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

LIN DC values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SPI (Input CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Input PWM2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DO, FSO, Digout3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Configuration bit HSxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Configuration bit OUT_HSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Configuration bit RELx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Configuration bit On_V2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Configuration bit TRIG, GO_VBAT, GO_V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Configuration bit Wx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Configuration bit Ux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Configuration bit Lx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Configuration bit Txx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Configuration bit INT_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Configuration bit OLT_HSx, VSLOCK Out, O_HS_REC, LINPU and TXD_TOUT. . . . . . . 59

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

Table 48.

Table 49.

Doc ID 13518 Rev 5

5/68

List of tables

L9952GXP

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Configuration bit LEVx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Configuration bit ICxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Configuration bit LIN slope, LS_ovuv and ICMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Configuration bit HSx_OL, HSx_OC and Relx_OC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Configuration bit SHT5V2, WUx, INH, LIN and Cold Start . . . . . . . . . . . . . . . . . . . . . . . . . 61

Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Configuration bit OV, UV, TW, TSDx and Vx Fail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Configuration bit STx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Configuration bit Rx, WDx, TRIG, SHT_GND, SHT_BAT and DOM_TXD. . . . . . . . . . . . . 63

PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6/68

Doc ID 13518 Rev 5

L9952GXP

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Operating modes, main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

FSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

NReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Lin master pull up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10. PowerSSO-36 thermal resistance junction ambient Vs. PCB copper area (V1 ON) . . . . . 32

Figure 11. PowerSSO-36 thermal impedance junction ambient single pulse (V1 ON) . . . . . . . . . . . . 32

Figure 12. PowerSSO-36 thermal fitting model (V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 13. Watchdog timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 14. Watchdog, closed and open window tolerances and save trigger area . . . . . . . . . . . . . . . 39

Figure 15. LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 16. SPI - Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 17. SPI - Edges timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 18. SPI - CSN low to high transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19. SPI - High to low transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 20. PowerSSO-36 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 21. PowerSSO-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 22. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Doc ID 13518 Rev 5

7/68

Pin definitions and functions

L9952GXP

1

Pin definitions and functions

Figure 1.

Block diagram

V_Bat

V_s

V_Bat

V_S

V_s

Temp Prewarning

& Shutdown

V2

Voltage

Regulator 2

220nF

Undervoltage -

Overvoltage -

Shutdown

CAN

M

INH

V1

Wake Up IN

R

Rel1

Rel2

Low Side

V

s

Output Clamp

C

Voltage

Regulator 1

Low Side

220nF

Output Clamp

Voltage

Monitor

PWM1

PWM2

NReset

OP1+

OP1-

+

-

OP1out

+

OP2+

OP2-

µC (ADC)

Window

Watchdog

Microcontroller

CSN

CLK

DI

-

OP2out

SPI

LOGIC

DO

e. g. Bulb,

LED, Hall

OUT_HS

High Side

Dig_Out3

Sensor

Dig_Out4 /

Interrupt

Out 1

Out 2

Out 3

TxD

RxD

High Side

LIN 2.1 ¹⁾

SAEJ2602

e. g. LED,

Hall Sensor

LINPU

LIN

¹⁾LIN 2.1 certified

Out 4

For detailed information

see

EMC test report from

IBEE Zwickau

High Side

WU3

WU4

Wake Up IN

ESDLIN1524BJ

Fail-safe Logic

Cyclic Contact

Monitoring

WU1

WU2

Wake Up IN

FSO

GND

Table 2.

Pins definitions and functions

PowerSS0-36

Function

name

GND

V2

1

2

Ground

Voltage regulator 2 output : 5 V supply for external loads e.g. IR

receiver, potentiometer

Voltage regulator 1 output : 5 V supply e.g. micro controller, Can

transceiver

V1

3

4

NReset output to micro controller - Internal pull-up of typ. 100KΩ

( reset state = low )

NReset

INH

5

6

Wake-up input e.g. from CAN transceiver

Receiver output of the LIN 2.1 transceiver

RxD

8/68

Doc ID 13518 Rev 5

L9952GXP

Pin definitions and functions

Table 2.

Pins definitions and functions (continued)

PowerSS0-36

Function

name

TxD

OP2+

7

Transmitter input of the LIN 2.1 transceiver

8

Non inverting input of operational sense amplifier

Inverting input of operational sense amplifier

Output of operational sense amplifier

SPI : serial data input

OP2-

9

OP2_OUT

DI

10

11

12

13

14

15

16

17

18

DO

SPI : serial data output

CLK

SPI : serial clock input

CSN

SPI : chip select not input

PWM1

PWM2

Dig_Out3

Dig_Out4/INT

Pulse width modulation input

Digital output

Digital output (configurable as Interrupt Output)

Wake-up input: input pins for static or cyclic monitoring of external

contacts

Wu_4..1

19 to 22

OP1_OUT

OP1-

23

24

25

Output of operational sense amplifier

Inverting input of operational sense amplifier

Non inverting input of operational sense amplifier

OP1+

High side driver (7 Ω, typ.) - to supply e.g. LED’ s, HALL sensors or

Out_4..1

26 to 29

30

external contacts

High side drivers (1 Ω, typ.) - to supply e.g. LED’ s, Bulbs, HALL

sensors or external contacts

Out_HS

Vs

LINPU

LIN

31

32

33

34

35

Power supply voltage

LIN master pull up

LIN bus line

Rel1

Rel2

Low side driver (2 Ω, typ.) - e.g. relay

Fail safe output - used to supervise or control applications in case of

watchdog and/or V1 under-voltage failure (e.g. to activate

emergency lights)

FSO

36

Doc ID 13518 Rev 5

9/68

Pin definitions and functions

L9952GXP

Figure 2.

Pins configuration

GND 1

V2 2

36 FSO

REL2

35

34 REL1

33

-

PowerSSO 36

V1 3

4

LIN

32 LINPU

Vs

NRESET

INH 5

31

RxD 6

TxD 7

30 OUT_HS

29 OUT1

OP2+ 8

OP2 - 9

L9952GXP

28

OUT2

OPOUT2 10

DI 11

27 OUT3

26 OUT4

25 OP1+

DO 12

CLK 13

24

OP1-

CSN 14

23 OPOUT1

22 WU1

PWM1 15

21 WU2

PWM2 16

Dig_Out 3 17

20

19

WU3

WU4

TAB = GND

_Out4 INT18

Dig

/

10/68

Doc ID 13518 Rev 5

L9952GXP

Description

2

Description

2.1

Voltage regulator

The L9952GXP contains 2 independent and fully protected low drop voltage regulators,

which are designed for very fast transient response.

The output voltage is stable with loads capacitors > 220nF.

2.1.1

Voltage regulator: V1

The voltage regulator V1 provides 5V supply voltage and up to 250mA continuous load

current for the external digital logic (micro controller, CAN transceiver ...). In addition the

regulator V1 drives the L9952GXP internal 5V loads. The voltage regulator is protected

against overload and over-temperature. An external reverse current protection has to be

provided by the application circuitry to prevent the output capacitor from being discharged

by negative transients or low input voltage. The output voltage precision is better than +/-2%

(incl. temperature drift and line-/load regulation) for operating mode; respectively +/-3%

during low current mode. Current limitation of the regulator ensures fast charge of external

bypass capacitors. The output voltage is stable for ceramic load capacitors > 220nF.

If device Temperature exceeds TSD1 threshold, all outputs (Hsx, Lsx, V2, LIN) will be

deactivated except V1. Hence the micro controller has the possibility for interaction or error

logging. In case of exceeding TSD2 threshold (TSD2>TSD1), also V1 will be deactivated

(see state chart Fig. 3.1: “Protection and diagnosis”). A timer is started and the voltage

regulator is deactivated for t

= 1sec. During this time, all other wakeup sources (CAN,

TSD

LIN, and WU1...4) are disabled. After 1 sec, the voltage regulator will try to restart

automatically. If TSD2 occurs within one minute and for 8 consecutive times, the L9952GXP

enters the V

- standby mode.

BAT

In case of short to GND at “V1” after initial turn on (V1 < 2V for at least 4ms) the L9952GXP

enters the V - standby mode. Reactivation (wake-up) of the device can be achieved with

BAT

signals from CAN, LIN, WU1..4, SPI.

2.1.2

Voltage regulator: V2

The voltage regulator V2 supplies additional 5V loads (e.g. Logic components, external

sensors, external potentiometers). The continuous load current is 50mA. The regulator

provides accuracy better than + 3% @ 50mA (4% @ 100mA) load current.

In case of short to GND at “V2” after initial turn on (V2 < 2V for at least 4ms) the V2

regulator is switched off. Micro processor has to send a clear command to reactivate the V2

regulator.

V2 is protected against:

●

Overload

Over temperature

Short circuit (short to ground and battery supply voltage)

Reverse biasing

Doc ID 13518 Rev 5

11/68

Description

L9952GXP

2.2

Power control in operating modes

The L9952GXP can be operated in 4 different operating modes:

●

Active

Flash

V - standby

1

V

- standby

BAT

A cyclic monitoring of wake-up inputs is available in stand-by modes.

2.2.1

2.2.2

Active mode

All functions are available.

Flash mode

To disable the watchdog feature a FLASH program mode is available.

The mode can be entered by V

≥ 9V

PWM2

In this case all other functions are the same as in active mode

Watchdog can be disabled as well as soon as L9952GXP enters the V1 standby mode (see

section 2.9 for details)

Note:

“High” level for flash mode selection is V

≥ 9V. For all other operation modes, standard

PWM2

5V logic signals are required. For proper operation PWM1 must not be set to a voltage level

above standard 5V logic.

2.2.3

V standby mode

1

Outputs and internal loads are switched off. To supply the micro controller in a low power

mode, the voltage regulator1 (V1) remains active. The intention of the V1 standby mode is

to preserve the RAM contents. A cyclic contact supply and wake-up input sense feature (for

cyclic monitoring of external contacts) can be activated by SPI.

2.2.4

V

standby mode

BAT

To achieve minimum current consumption during V

standby mode, all L9952GXP

BAT

functions (except the ones for wake up functionality) are switched off.

In V - standby mode the current consumption of the L9952GXP is reduced to 7µA, typical

BAT

(without cyclic sense feature selected).

The transitions from active mode to either V -standby or V

- standby are controlled by

BAT

1

SPI.

V

- standby mode is dominant; i.e. if both bits, V - standby and V

- standby are set to

BAT

1

“1”, the L9952GXP will enter V

- standby mode.

BAT

12/68

Doc ID 13518 Rev 5

L9952GXP

Description

2.3

Wake up events

A wake-up from standby mode will switch the device to active mode. This can be initiated by

one or more of the following sources:

●

Change of the LIN state at LIN bus interfaces

●

A current at the INH pin (I ≥200uA) controlled by the CAN-transceiver (the CAN

transceiver is not a part of the IC).

●

Positive/negative edge at wake up pins WU1...WU4 -> change of level after going into

stand-by

●

Change of open-load state at OUT1 to 4

SPI access in V1-standby mode (CSN is low and first rising edge on CLK)

Table 3.

Wake up events

Wake up source

Description

LIN

INH

Always active

WU1...4

Can be individually disabled via SPI

Open Load at HS outputs

Always active

SPI Access

(except in V_BAT- standby mode)

High level at PWM2 input

VPWM2 > 9V ⁽¹⁾

1. Only if internal oscillator is running (e. g. in cyclic sense configuration or after wake-up request).

All wake-up events (except wake-up by LIN, INH or SPI from V1standby mode) generate a

Reset pulse (NReset low for 2ms).

Wake-up events from V1standby by LIN, INH or SPI do not cause a Reset and the Reset

generation is blocked for 2ms, i. e. a watchdog failure during this timeframe will not cause a

reset.

Doc ID 13518 Rev 5

13/68

Description

L9952GXP

2.4

Functional overview (truth table)

Table 4.

Functional overview (truth table)

Operating modes

V₁-standby

static mode

V_BAT-standby

static mode

Function

Comments

Active mode

(cyclic sense) (cyclic sense)

2.3.1

2.3.2

2.3.3

Voltage-regulator, V1

Voltage-regulator, V2

Reset-generator

VOUT= 5V

On

On / Off ⁽²⁾

On

On ⁽¹⁾

On ⁽²⁾/ Off

On

Off

On ⁽²⁾/ Off

Off

Off if

(I_V1 < I_CMP

and I_CMP=0)

2.3.4

Window watchdog

V₁monitor

On

Off

or I_CMP= 1

2.3.5

2.3.6

Wake up

Off ⁽³⁾

Active ⁽⁴⁾

Oscillator

timebase

HS-cyclic supply

On / Off

On ⁽²⁾/ Off

2.3.7

2.3.8

2.3.9

2.3.10

Relay driver

Operational amplifiers

LIN line driver

On

Off

On

Off

LIN 2.1

LIN line receiver

On

Hi – no error

Fail-safe

output

Lo -> because

V1= off

2.3.11

FSO

Lo – WD or V1 Lo – WD or V1

fail

On

fail ⁽⁵⁾

(6)

(7)

2.3.12

2.3.13

Oscillator

(7)

Vs-Monitor

1. Supply the processor in low current mode

2. Only active when selected via SPI

3. Input Status can be read by SPI (Status Register 0); Inputs should be configured for static sense (Control

Register 2)

4. Unless disabled by SPI

5. Watchdog is active in V1 standby mode, until I(V1) is below I_CMPcurrent threshold

6. Activation = ON if cyclic sense is selected

7. Cyclic activation = pulsed ON during cyclic sense

14/68

Doc ID 13518 Rev 5

L9952GXP

Description

Figure 3.

Operating modes, main states

Vs > Vpor

Vbat startup

All registers

cleared to ‚0',

Cold start bit (D19, SR0)

set to ‚1'

Vpwm2>9V

Flash Mode

Watchdog: OFF

Vpwm2<7V

Active

Mode

V1: on

SPI command: ‚Go Vbat’ (D20 CR0)

Reset Generator: active

Watchdog: active

OR

Thermal Shutdown

OR

V1 fail (V1 < 2,5V for 4ms after POR)

=> short to GND

Fail Safe Out: active

Vpwm2>9V

Note 1

Or

15 x WD Failure

Wake-up

Event

SPI command: ‚Go Vcc’

(D21 CR0)

Wake-up

Event

Vpwm2>9V

Note 1

V1 Standby

Mode

Vbat Standby

Mode

V1: on

V1: off

V2: according to SPI settings

Reset Generator: off (Nreset=low)

Watchdog: off

Reset Generator: active

Watchdog:

OFF (if Iv1<I_cmpor ICMP= 1)

Fail Safe Out: active

Thermal Shutdown TSD2

OR IV1 > 1mA AND ICMP = 0 AND 15 x WD fail

Fail Safe Out: low

HSD, LSD: Off

Note 1: only if internal oscillator is running

Doc ID 13518 Rev 5

15/68

Description

L9952GXP

2.5

Wake up inputs

The de-bounced digital inputs WU1...WU4 can be used to wake up the L9952GXP from

standby modes. These inputs are sensitive to any level transition (positive and negative

edge)

For static contact monitoring, a filter time of 64 µs is implemented at WU1-4. The filter is

started when the input voltage passes the specified threshold. At Vin > 1V and Vin < (Vs –

2V), a Wake-up request is processed. During Wake-up request, the internal oscillator and

other circuit blocks are activated in order to allow more accurate monitoring of the inputs.

In addition to the continuous sensing (static contact monitoring) at the wake up inputs, a

cyclic wake up feature is implemented. This feature allows periodical activation of the wake-

up inputs to read the status of the external contacts. The periodical activation can be linked

to Timer 1 (0.5sec to 4.0sec in 0.5sec steps) or Timer 2 (50ms). The input signal is filtered

with a filter time of 16us after a programmable delay (80us or 800us). A Wake-up will be

processed if the status has changed versus the previous cycle.

The Outputs OUT_HS and OUT1-4 can be used to supply the external contacts with the

timing according to the cyclic monitoring of the wake-up inputs.

If the wake-up inputs are configured for cyclic sense mode (Icxx in control register 2), the

same input filter timing (Timer1 or Timer2) and the corresponding input filter delay (control

register 2) must be used for the HS Outputs (Hsxx in control register 0) which supply the

external contact switches.

In Standby mode, the inputs WU1-4 are SPI configurable for pull-up or pull-down current

source configuration according to the setup of the external contacts (pull-up for active low

contacts, pull-down for active high contacts). In active mode the inputs have a pull down

resistor of 100 kOhm (typ).

In Active mode, the input status can be read by SPI (Status Register 0). Static sense should

be configured (Control Register 2) before the read operation is started (In cyclic sense

configuration, the input status is updated according to the cyclic sense timing; Therefore,

reading the input status in this mode may not reflect the actual status).

2.6

Hall sensor ports: WU3,4, Dig_Out 3,4

Applications like Hall sensor outputs need high processing speed. The 12V signals

connected to the wakeup inputs WU3 and WU4 can be looped through to the digital outputs

Dig_Out 3 and Dig_Out 4 (5V) in order to avoid read out of the input state by SPI.

The setup is programmable by SPI.

The open load states of the High Side Drivers OUT1 and OUT2 can be looped through the

digital outputs Dig_Out3 and Dig_Out4 without delay. In addition, the status of OUT1 and

OUT2 can be accessed through the SPI interface. This feature is intended for 2-pin HALL

sensors. Open Load information is only valid during ON state.

The Open Load threshold at pins OUT1...4 can be switched from I

= 2mA to

OLD1

I

= 8 mA via SPI .

OLD2

16/68

Doc ID 13518 Rev 5

L9952GXP

Description

2.7

Interrupt

Dig_Out4 can be configured via SPI as Interrupt output (INT) by setting Bit 20 /

CR1:INT_enable=’1’.

This configuration will enable the following behaviour:

●

INT pin is pulled high for 2ms in case of any wake-up from V1 standby mode (WU

inputs, LIN, INH, SPI, open load HS, Iv1 > I _ris)

CMP

Wake-up events from V1 standby do not generate a reset (i.e. NRESET is not pulled

low)

The Dig_Out4 settings in CR1 (Bits 12..14) will be ignored

2.8

Cyclic contact supply

In V1 and V

standby mode, any high side driver output (OUT1..4, OUTHS) can be used

BAT -

to periodically supply external contacts.

The timing is selectable by SPI

Timer 1: period is X sec, the on-time is 10ms resp. 20ms

With X ∈ {0.5, 1.0, 1.5, ... 4 }

Timer 2: period is 50ms, the on- time is 100us resp. 1ms:

Note:

Cyclic sense setup: if cyclic sense feature is used for wake-up inputs (Icxx in control register

2), same input filter timing (Timer1 or Timer2) must be used for HS Outputs (Hsxx in control

register 0).

2.9

Window – watchdog

During normal operation the watchdog monitors the micro controller within a nominal trigger

cycle of 10ms.

In V

-standby V1-standby and Flash program modes, the watchdog circuit is

,

BAT

automatically disabled. However, the watchdog will remain enabled in V1-standby mode

until the current at V1 decreases below I _fall. The V1 current monitoring can be

CMP

disabled, if the I

bit (CR2, D20) is set to '1'.

CMP

After ‘power-on’, ‘standby mode’ or reset, the window watchdog starts with a long open

window (65ms). The long open window allows the micro controller to run its own setup and

then to trigger the watchdog via the SPI. The trigger is finally accepted when the CSN input

becomes HIGH after the transmission of the SPI word.

A correct watchdog trigger will start the window watchdog with a closed window (< 6ms)

followed by an open window (< 10ms), see timing diagrams. Subsequently, the micro

controller has to serve the watchdog by alternating the watchdog trigger bit (CR0, D19). The

“negative” or “positive” edge has to meet the open window time. A correct watchdog trigger

signal will immediately start the next closed window.

After 8 watchdog failures in sequence, the V1 regulator is switched off for 200ms. In case of

7 further watchdog failures, the V1 regulator is completely turned off and the device goes

into V

standby mode until a wakeup occurs. (e.g. via LIN, CAN/INH).

BAT -

Doc ID 13518 Rev 5

17/68

Description

L9952GXP

The watchdog is triggered by toggling the trigger bit (CR0, D19).

Note:

The active trigger window will be reset after each correct trigger write operation.

In case of reset (NReset low for 2ms) the trigger bit is set to “0”.

In case of a WD failure, the outputs (Lsx, Hsx, V2) are switched off and NReset is pulled low

for 2ms.

Writing to control register 0 without inverting the WD trigger bit is possible at any time.

Figure 4. Watchdog

Watchdog Failure

Wake up event

Vbatstdby

Mode

8+7

WD Failures

Toggle WD Trigger Bit

Within nominal window

V1 off

for 200ms

t=200ms

8x WD Failure

Watchdog active

With

Normal window

(10ms)

HSD, LSD : according to

CR0

Reset

(Nreset =low for 2ms)

LSD: Off (control bits set to 0‚ ')

HSD: Off (control bits remain

unchanged)

Watchdog Failure (‚long

open window’ passed

without TRIG=1

Set WD Trigger Bit = ‚1' or

toggle trigger bit if wake-up

from V1standby

2ms

Wake-up event

or exit Flash Mode

Go to standby mode

or Flash Mode (PWM2>9V)

Watchdog active

with

‚long open window’

(65ms nom)

HS and LS outputs are

off

Set

WD Trigger Bit = ‚0' or write

non-inverting value to trigger

bit after wake-up from

V1standby mode

Go to standby mode or

Flash Mode (PWM2>9V)

Power-on

Reset

INH, LIN, SPI

I(V1)>1mA and ICMP=0

Watchdog

Inactive

(standby modes,

Flash Mode)

18/68

Doc ID 13518 Rev 5

L9952GXP

Description

2.10

Fail safe output

After power-on (Vs > V

) or wakeup from V

-standby mode, the output FSO is set to

BAT

POR

“HIGH”, if V1 is above the V1 threshold. FSO is set to “LOW” in case of V1 under voltage or

watchdog failure.

During V1-standby mode, FSO is HIGH unless a V1 under-voltage or watchdog reset

occurs. WD remains enabled in V1 standby mode until I drops below 150uA. In V

-

V1

BAT

standby mode, FSO is low. At exit from V

is stable.

- standby mode, it goes to high as soon as V1

BAT

At wakeup FSO remains high, provided that the watchdog is triggered successfully. It is set

low if the watchdog is not served during the long open window of if a V1 under-voltage

occurs.

Figure 5.

FSO

V1 undervoltage

Watchdog Failure

TSD2

Vbatstdby Mode

FSO = 0

2.11

Reset – generator

IF V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output

“NRESET” is switched to “HIGH” after a 2ms reset delay time. This is necessary for a

defined start of the micro controller when the application is switched on.

As soon as an under voltage condition of the output voltage (V1 < VRT) for more than 8us

appears, the reset output is switched low again.

Figure 6.

NReset

V1 Undervoltage

Wake-up Event 1)

Vpwm2 < 9V

(Exit Flash Mode)

Watchdog

Failure

NReset = 0

1) Only if

(INT_en = 0) and (wake-up by WU-input or High Side Open Load)

Doc ID 13518 Rev 5

19/68

Description

L9952GXP

2.12

V1, V2 fail

The V and V regulator output voltages are monitored.

1,

2

In case of a drop below the V V – fail thresholds (V < 2V,typ for t > 2us), the V - fail

1,

2

1,2

bits are latched. The fail bits are cleared by a dedicated SPI command.

If 4ms after turn on of the regulator the V voltage is below the V fail thresholds,

1,2

(independent for V1,2 ), the L9952GXP will identify a short circuit condition at the related

regulator output and the regulator will be switched off.

In case of a V1 failure the device enters V

- standby mode automatically.

BAT

In case of a V2 failure the SHT5V2 bit (SR0 Bit12) is set.

2.13

Low side driver outputs Rel1, Rel2

The outputs Rel1, Rel2 (R

loads.

= 2 Ω typ. @25 °C) are specially designed to drive relay

DSon

Typical relays used have the following characteristics:

Relay type 1:

–

closed armature: R = 160 Ω +10%, L= 300mH

open armature: R = 160 Ω +10%, L= 240mH

Relay type 2:

–

closed armature: R= 220 Ω +10%, L= 420mH

open armature: R= 220 Ω +10%, L= 330mH

The outputs provide an active output zener clamping (40V) feature for the demagnetisation

of the relay coil, even though a load dump condition exists. In case of watchdog failure the

relay drivers will be switched off and the low side driver control bits are cleared.

Note:

1

2

Due to relays bouncing, high dV/dt and/or dI/dt transients may occur on the low side driver

outputs. In case high currents are switched (for example window lift motor), due to parasitic

capacitive inductive coupling from load side of relays to the relays coils, the Absolute

Maximum Ratings of the Low Side driver outputs may be exceeded. In order to avoid this, it

is recommended to place a 10nF capacitor at the Rel1, Rel2 outputs to GND.

If a hard short circuit to V

is possible at the "Low Side Driver" outputs, an RC network is

BAT

required with T > 1µs, R ≥ 1 Ω (see block diagram, the value is given for an output short

RC

circuit of given di/dt = 5A/µs).

2.14

PWM inputs

The inputs PWM 1,2 can be used to control the output drivers Out1..4 and OUT_HS with a

PWM signal. Each PWM input can be mapped individually to each of the above listed

outputs according to the SPI settings.

20/68

Doc ID 13518 Rev 5

L9952GXP

Description

2.15

Operational amplifiers

The operational amplifiers are especially designed to be used for sensing and amplifying the

voltage drop across ground connected shunt resistors. Therefore the input common mode

range includes - 0.2 ... 3V.

The operational amplifiers are designed for GND + 3V... GND – 0.2V input voltage swing

and rail-to-rail output voltage range. All Pins (positive, negative and outputs ) are available

to be able to operate in non-inverting and inverting mode. Both operational amplifiers are

on-chip compensated for stability over the whole operating range within the defined load

impedance.

Figure 7.

Lin master pull up

Vs

LIN

control

T_SW

LINPU

LIN

control

30k

Master node

pull up

1k

Gnd

A dedicated built-in switch “Tsw” enables the LIN to act as a master. (see chapter 2.18)

2.16

LIN bus interface

General requirements:

●

Speed communication up to 20kbit/s

LIN 2.0 compliant (SAEJ2602 compatible) transceiver

Function range from +40V to -18V DC at LIN Pin

GND disconnection fail safe at module level

Off mode: does not disturb network

GND shift operation at system level

Microcontroller Interface with CMOS compatible I/O pins.

Pull up resistor internal.

ESD: immunity against automotive transients per ISO7637 specification (see

application note)

●

Matched output slopes and propagation delay

In order to further reduce the current consumption in standby mode, the integrated LIN bus

interface offers an ultra low current consumption.

Doc ID 13518 Rev 5

21/68

Description

L9952GXP

2.17

Error handling

The L9952GXP provides the following 3 error handling features which are not described in

the LIN Spec. V2.1, but are realized in different stand alone LIN transceivers / micro

controllers to switch the application back to normal operation mode.

2.17.1

2.17.2

2.17.3

Dominant TxD time out

If TXI is in dominant state (low) for more than 12ms (typ) the transmitter will be disabled until

TXI becomes recessive (high). This feature can be disabled via SPI.

Short to battery time out

If TXI changes to dominant (low) state but RXI signal does not follow within 40µs, the

transmitter will be disabled until TXI becomes recessive (high).

Short to ground mode

A wake up caused by a message on the bus will start the voltage regulator and the micro

controller to switch the application back to normal operation mode.

2.18

Wake up (from LIN)

In standby mode the L9952GXP can receive a wake up from LIN bus. For the wake up

feature the L9952GXP logic differentiates two different conditions.

2.18.1

Normal wake up

Normal wake up can occur when the LIN transceiver was set in standby mode while LIN was

in recessive (high) state. A dominant level at LIN for at least 40µs, will switch the L9952GXP

to active mode.

2.18.2

2.18.3

Wake up from short to GND condition

If the LIN transceiver was set in standby mode while LIN was in dominant (low) state,

recessive level at LIN for at least 40us, will switch the L9952GXP to active mode.

RxD pin in V1 standby

In V1 standby condition the RxD is a tristate pin.

22/68

Doc ID 13518 Rev 5

L9952GXP

Description

2.19

LINPU

The LINPU (LIN pull up) signal is set by L9952GXP logic in order to drive the LIN transceiver

in master mode. The master mode is realized by an internal high side switch and an external

diode in series with an external 1k resistor. In master mode the high side switch is closed

causing an external pull up path in parallel to the internal one (diode & 30k resistor).

HS (high side) characteristics:

●

HS does not have an over current protection.

The HS remains active in standby mode.

Switch off only in case of over temperature (TSD2 = thermal shutdown #2).

Typical R

, 10 Ω.

DSon

The Linpu is activated by default (LIN master mode) and can be switched off with a SPI

command (see register 2) to reduce current in case of LIN shorted to ground.

2.20

Serial Peripheral Interface (SPI)

A 24 bit SPI command (2 adresses + 22 data bits) is used for bi-directional communication

with the micro controller.

During active mode, the SPI:

1) triggers the watchdog

2) controls the modes and status of all L9952GXP modules (incl. input and output drivers)

3) provides driver output diagnostic

4) provide L9952 diagnostic (incl. over temperature warning, L9952GXP operation status)

During stand-by modes, the SPI is generally deactivated.

Note:

The SPI can be driven by a micro controller with its SPI peripheral running in following

mode:

CPOL=0 and CPHA=0.

For this mode input data is sampled by the low to high transition of the clock CLK, and

output data is changed from the high to low transition of CLK.

This device is not limited to micro controller with a build-in SPI. Only three CMOS-

compatible output pins and one input pin will be needed to communicate with the device. A

fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the

global error flag (fault condition) of the device which is a logical -”OR” of all over current, Vs-

over / under voltage, temperature warning/shutdown and V1 Fail bits. The micro controller

can poll the status of the device without the need of a full SPI-communication cycle.

2.20.1

Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the

output pin (DO) will be in high impedance state. A low signal activates the output driver and

a serial communication can be started. The state during CSN = 0 is called a communication

frame.

Doc ID 13518 Rev 5

23/68

Description

L9952GXP

2.20.2

Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be

sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.

At the rising edge of the CSN signal the contents of the shift register will be transferred to

Data Input Register. The writing to the selected Data Input Register is only enabled if exactly

24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock

pulses are counted within one frame the complete frame will be ignored. This safety

function is implemented to avoid an activation of the output stages by a wrong

communication frame.

Note:

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected IC's is

recommended.

2.20.3

Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from

high impedance to a low or high level depending on the global error flag (fault condition).

The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer

the content of the selected status register into the data out shift register. Each subsequent

falling edge of the CLK will shift the next bit out.

2.20.4

2.20.5

Serial Clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input

(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the

falling edge of the CLK signal. The SPI can be driven with a CLK frequency up to 1MHz.

Data registers

The device has 3 Control registers and 2 Status registers. The first two bits (D22+D23) at

the DI-Input are used to select one of the Control registers. All bits are first shifted into an

input shift register. After the rising edge of CSN the contents of the input shift register will be

written to the selected Control register only if a frame of exact 24 bits is detected. If the

Control register 1 is selected for data transfer, the Status register 1 will be transferred to the

DO during the current communication frame. For the selection of Control register 0 or

Control register 2, the Status register 0 is transferred to DO.

24/68

Doc ID 13518 Rev 5

L9952GXP

Protection and diagnosis

3

Protection and diagnosis

3.1

Power supply fail

Over and under-voltage detection on Vs.

3.1.1

Over voltage

If the supply voltage Vs reaches the over voltage threshold (V

)

SOV

●

The outputs HS1..4, OUT_HS, Rel1,2, and LIN are switched to high impedance state

(load protection)

●

The over voltage bit is set and can be cleared with the clear bit (CR1,CLR)

Automatic recovery after Vs over-voltage; selectable via SPI (CR2, bit4)

3.1.2

Under voltage

If the supply voltage Vs drops below the under voltage threshold voltage(V

)

SUV

●

The outputs HS1..4, OUTHS, Rel1,2, and LIN are switched to high impedance state

(load protection)

●

The under voltage bit is set

Automatic recovery after Vs under-voltage; selectable via SPI (CR2, bit4)

3.2

3.3

Temperature warning and thermal shutdown

See state chart: “ Protection and diagnosis”.

SPI diagnosis

Digital diagnosis features are provided by SPI:

●

V1 reset threshold programmable

Over temperature including pre warning

Open load separately for each output stage

Overload status

Vs-supply over/under voltage

V1 and V2 fail bit

Status of the WU1...4, LIN and INH pin

Cold start bit

Number of unsuccessful V1 restarts after thermal shutdown

Number of sequential watchdog failures

Status of watchdog trigger bit TRIG: (SR1, Bit 16)

LIN status (short to ground, short to V , dominant TxD)

BAT

See the following state chart: “Protection and diagnosis”.

Doc ID 13518 Rev 5

25/68

Protection and diagnosis

L9952GXP

Figure 8.

Protection and diagnosis

Tj > 155°C

TSD2

TSD1

All outputs: off

V1: off for 1 sec

‚TSD2-bit is set (D4 SR1)

All outputs except V 1: off

‚TSD 1'-Bit is set (D3 SR1)

8x TSD2

(each TSD2

within 1 min)

Tj> 140°C

SPI command: ‚CLR’

(D21 CR1)

OR

Temperature

Warning

Power-on reset

Vbatstdby

‚Temperature Warning'-

Bit set

All outputs incl V 2: off

(D2 SR1)

SPI command: ‚CLR’

(D21 CR1)

OR

Power-on reset

Wake-up event

Power-on reset

Tj> 130°C

Active

Mode

Standby Modes

(during cyclic sense )

Vs Undervoltage

Vs Overvoltage

SPI command: ‚CLR’

(D21 CR1)

OR

Autorestart activated

(D4 CR2)

OR

Autorestart activated

(D4 CR2)

Vs Lockout

All outputs: high Impedance

OV Bit set (D0 SR1)

Auto-restart if selected by SPI

All outputs: off

UV bit set (D1 SR1)

Auto-restart if selected by SPI

V1 off for

200ms

Vbatstdby

mode

8 successive watchdog

failures

7 additional watchdog failures

in sequence

26/68

Doc ID 13518 Rev 5

L9952GXP

Protection and diagnosis

3.4

High side driver outputs

The component provides a total of 4 high side outputs Out1...4, (7 Ω typ. @ 25C) to drive

e.g. LED' s or hall sensors and 1 high side output OUT_HS with 1 Ω typ. @ 25 C).

The high side outputs are protected against

●

Over- and under voltage

Overload (short circuit)

Over temperature with pre warning

If the output current exceeds the current shutdown threshold the output transistor is turned

off and the corresponding diagnosis bit of the output is set.

The switches are automatically disabled in case of reset condition, Vs-under, Vs-over

voltage or thermal shutdown (TSD1&2).

For OUT_HS an auto recovery feature is available in active mode.

If the OUT_HS output current exceeds the current shutdown threshold, the output transistor

is turned off and the corresponding diagnosis bit of the output is set.

Via SPI command the auto recovery feature can be enabled in order to restart the driver in

case of over current shutdown. This over current recovery feature is intended for loads

which have an initial current higher than the over current limit of the output (e.g. Inrush

current of cold light bulbs).

The device itself can not distinguish between a real overload and a non linear load like a

light bulb. A real overload condition can only be qualified by time. As an example, the micro

controller can switch on light bulbs by setting the over current recovery bit for the first 50ms.

After clearing the recovery bit, the output will be automatically disabled if the overload

condition still exists.

The status of all high side outputs (over-current, open load) can be monitored by SPI

interface.

In case of a watchdog failure, the high side drivers are switched off. The control bits are not

cleared, i.e. the drivers will go to the previous state once the watchdog failure condition

disappears.

ESD structures are configured for nominal currents only. If external loads are connected to

different grounds, the current load must be limited to this nominal current.

Note:

Loss of ground or ground shift with externally grounded loads.

3.5

Low side driver outputs Rel1, Rel2

The outputs provide an active output zener clamping feature for the demagnetisation of the

relay coil, even though a load dump condition exists. For safety reasons the relay drivers

are linked with the Watchdog: in case of failure, or missing trigger signal the relay drivers will

switch off.

Doc ID 13518 Rev 5

27/68

Absolute maximum ratings

L9952GXP

4

Absolute maximum ratings

Table 5.

Absolute maximum ratings

Symbol

Parameter

Value

Unit

V_S

DC supply voltage / “jump start”

-0.3 to +28

V

Single pulse / t_max< 400 ms

“transient load dump”

-0.3 to +40

V

Stabilized supply voltage, logic

supply

V₁

V₂

-0.3 to +5.25

-0.3 to +28

V

Stabilized supply voltage

V_DIV_CLK

V_TXDV_CSN

V_DOV_RXD

Logic input / output voltage range

-0.3 to V1+0.3

V

V_NRESETV_FSO

V_DIGOUT3,4

V_INH

Wake up input voltage range

PWM input voltage range

V_PWM1,V_PWM2,

V_REL1,V_REL2,

_OUT1..4,,V_OUTH

V_WU1...4,

-0.3 to +40

V

Low side output voltage range

V

High side output voltage range

Wake up input voltage range

-0.3 to V_S+ 0.3

V

V_OP1+,V_OP1-,

V_OP2+,V_OP2-,

Opamp1 input voltage range

Opamp2 input voltage range

-0.3 to V1 + 0.3

V

V_OPOUT1,

V_OPOUT2

_LIN,V_LINPU

Analog Output voltage range

LIN bus I/O voltage range

-0.3 to V_S+ 0.3

V

-20 to +40

5

Current injection into Vs related

input pins

I_Input

mA

Note:

All maximum ratings are absolute ratings. Leaving the limitation of any of these values may

cause an irreversible damage of the integrated circuit !

28/68

Doc ID 13518 Rev 5

L9952GXP

ESD protection

5

ESD protection

Table 6.

ESD protection

Parameter

Value

Unit

All pins, except LIN⁽¹⁾

All output pins⁽²⁾

+/- 2

+/- 4

kV

V

LIN⁽³⁾

+/- 1.5

+/- 8

LIN⁽⁴⁾

All pins (charge device model)

Corner pins (charge device model)

All pins⁽⁵⁾

+/- 500

+/- 750

+/- 200

V

1. HBM (human body model, 100pF, 1.5 kΩ ) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A

2. HBM with all none zapped pins grounded

3. Without external components

4. Acc. DIN EN61000-4-2 (330Ω, 150pF), with external components:

- Diode, type ESDLIN1524BJ

- SMD Ferrite bead, type TDKMMZ2012Y202B

- Capacitor C=220pF

For detailed information please see EMC report from IBEE Zwickau (available on request)

5. Acc. Machine Model: C=220pF; L=0.75µH; R=10Ω

Doc ID 13518 Rev 5

29/68

Thermal data

L9952GXP

6

Thermal data

6.1

Operating junction temperature

Table 7.

Item

Operating junction temperature

Symbol

Parameter

Value

Unit

6.1.1

6.1.2

Tj

Operating junction temperature

- 40 to 150

°C

RthjA

Thermal resistance junction- ambient

See Figure 10.

°C/W

6.2

Temperature warning and thermal shutdown

Table 8.

Item

Temperature warning and thermal shutdown

Symbol

Parameter

Min.

Typ. Max. Unit

Thermal over temperature

warning threshold

(1)

6.2.1

6.2.2

T_{W ON}

T_j

120

130 140

°C

Thermal shutdown

junction temperature 1

(1)

T_{SD1 OFF}

T_j

130

140

140 150

155 170

5

°C

6.2.3

6.2.4

6.2.5

T_SD2OFF

T_{SD2 ON}

T_SD12hys

Thermal shutdown

junction temperature 2

Hysteresis

1. Non-overlapping

30/68

Doc ID 13518 Rev 5

L9952GXP

Thermal data

6.3

Package and PCB thermal data

Figure 9. PowerSSO-36 PC board

Note:

Layout condition of R and Z measurements ( board finish thickness 1.6 mm +/- 10%

th th

board double layer, board dimension 129x60, board Material FR4, Cu thickness 0.070mm

(front and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08

mm, Cu thickness on vias 0.025 mm ).

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31/68

Thermal data

L9952GXP

Figure 10. PowerSSO-36 thermal resistance junction ambient Vs. PCB copper area

(V1 ON)

RTHj_amb(°C/ W)

110

90

70

50

30

0

2

4

6

8

10

PCB Cu heatsink area (cm^ 2)

Figure 11. PowerSSO-36 thermal impedance junction ambient single pulse (V1 ON)

ZTH (°C/ W)

1000

Footprint

100

2 cm²

8 cm²

10

1

0,1

0,01

0,1

1

10

100

1000

Time (s)

32/68

Doc ID 13518 Rev 5

L9952GXP

Thermal data

Equation 1: pulse calculation formula

= R ⋅ δ + Z (1 – δ)

Z

THδ

TH

THtp

where δ = t /T

P

Figure 12. PowerSSO-36 thermal fitting model (V1 ON)

Table 9.

Thermal parameters

Area/island (cm²)

Footprint

2

8

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

5

18

10

22

29

10

7,8

21

29

51

0,0003

0,35

1,5

5

1

1,3

15

1,3

15

Doc ID 13518 Rev 5

33/68

Electrical characteristics

L9952GXP

7

Electrical characteristics

7.1

Supply and supply monitoring

The voltages are referred to ground and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; 4.8V < V1 < 5.2V; all outputs open; T = -40°C...130°C,

S

j

unless otherwise specified.

Table 10. Supply and supply monitoring

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

7.1.1

V_S

Supply voltage range

6

13.5

18

V

V_Sincreasing /

decreasing

7.1.2

7.1.3

7.1.4

7.1.5

V_SUV

V_{hyst_UV}

V_SOV

VS UV-threshold voltage

Undervoltage hysteresis

VS OV-threshold voltage

Overvoltage hysteresis

5.11

5.81

0.04 0.1 0.15

V_Sincreasing /

decreasing

18

22

V_{hyst_OV}

Hysteresis

0.5

1

1.5

Vs=12V, TxD LIN

high, V2 on,

Current concumption in

active mode

7.1.6

7.1.7

7.1.8

I_V(act)

2.7

20

10

mA

µA

Outputs off

Iv1=Iv2=0A

V_S=12V, both

Current consumption in

V_BAT- standby mode

voltage regulators

deactivated, no

wake-up request

I_V(BAT)

1

7

V_S=12V, both

voltage regulators

deactivated, (cyclic

sense)

Current consumption in

V_BAT- standby mode

I_V(BAT)CS

40

75

100

V1=5V, V_S=12V,

Voltage regulator

V1 active, without

cyclic sense, no

wake-up request

Current consumption in

V₁-standby mode

7.1.9

I_V(V1)

10

45

70

µA

Current consumption in

7.1.10

7.1.11

I_V(BATWU)

V_BAT-standby mode with a 1.5V<V_WU<(Vs-3V)

pending wake up request

220 320

300 410

µA

Current consumption in

I_V(V1WU)

V₁- standby mode with a

pending wake up request

1.5V<V_WU<(Vs-3V)

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Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

7.2

Oscillator

6V < V < 18V; all outputs open; T = -40°C...130°C, unless otherwise specified.

S

j

Table 11.

Item

Oscillator

Symbol

F_CLK

Parameter

Test condition

Min. Typ. Max. Unit

7.2.1

Oscillation frequency

Vs = 6V...18V

0.808 1.01 1.35 MHz

7.3

7.4

Power-on reset (Vs)

All outputs open; T = - 40°C...130 °C, unless otherwise specified.

j

Table 12. Power-on Reset (Vs)

Item

7.3.1 V_{THUP_POR}

7.3.2 V_{Hys_POR}

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

V_PORthreshold

Hysteresis

2.8 3.45 4.1

200

V

mV

Voltage regulator V1

The voltages are referred to ground and currents are assumed positive, when the current

flows into the pin. 5.25V < V < 27V; T = -40°C...130°C, unless otherwise specified.

S

j

Table 13. Voltage regulator V1

Item

Symbol

Parameter

Output voltage

Test condition

Min. Typ. Max. Unit

7.4.1

V1

5.0

V

I_LOAD= 1mA...

100mA,

Output voltage tolerance

Active mode

7.4.2

7.4.3

V1

+/- 2

+/- 3

%

VS = 13.5V

I_LOAD= 100mA ...

250mA,

%

VS = 13.5V

Output voltage tolerance

Active mode, high current

Vhc1

I_LOAD= 250mA

VS = 13.5V,

T_j>80°C

+/- 4

%

0mA< I_LOAD<I_CMP

VS = 13.5V

Output voltage tolerance

in low current mode

7.4.4

7.4.5

7.4.6

VSTB1

VDP1

ICC1

I_LOAD= 50mA,

V_S= 4.5V

0.2

0.3

0.4

0.5

V

Drop-out voltage in

undervoltage conditions

I_LOAD= 100mA,

V_S=4.5V

Output current in active

mode

Max. continuous

load current

250 mA

Doc ID 13518 Rev 5

35/68

Electrical characteristics

L9952GXP

Table 13. Voltage regulator V1 (continued)

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

Short circuit output

current

7.4.7

7.4.8

7.4.9

ICCmax1

Cload1

tTSD

Current limitation

Ceramic⁽¹⁾

400 600 950 mA

Load capacitor1

0.22

0.9

µF

s

V1 deactivation time after

thermal shutdown

1

Current comp. rising

threshold

7.4.10

7.4.11

I_{CMP_ris}

Rising current

2.5

4

mA

Falling current

Current comp. falling

threshold

I_{CMP_fal}

Tj= -40°C...130°C

Tj= 25°C...130°C

0.75 1.95

0.85 1.95

7.4.12

7.4.13

I_CMP_hys

V1fail

Current comp. hysteresis

V1 fail threshold

0.5

2

mA

V

V1 forced

1. Placement close to the PAD

7.5

Voltage regulator V2

The voltages are referred to ground and currents are assumed positive, when the current

flows into the pin. 5.25V < V < 27V; T = -40°C...130°C, unless otherwise specified.

S

j

Table 14. Voltage regulator V2

Item

Symbol

Parameter

Output voltage

Test condition

Min. Typ. Max. Unit

7.5.1

V₂

5.0

V

Output voltage tolerance

Active mode

I_LOAD= 1mA ...

50mA, V_S= 13.5V

7.5.2

7.5.3

7.5.4

V₂

+/- 3

+/- 4

+/- 5

%

Output voltage tolerance

Active mode, high current 100mA, V_S= 13,5V

I_LOAD= 50mA ...

V_hc1

%

Output voltage tolerance in I_LOAD= 0uA ...1mA

V_STB2

low current mode

Drop-out voltage

V_S= 13,5V

_LOAD= 25mA,

I

V_S= 5 V

0,3

0.4

0,4

V

7.5.5

V_DP2

I_LOAD= 50mA,

V_S= 5 V

0.7

V

Output current in Active

mode

Max. continuous

load current

7.5.6

I_CC2

100

mA

7.5.7

7.5.8

7.5.9

I_CCmax2

C_load

Short circuit output current Current limitation

200 300 500

mA

µF

V

Load capacitor

V2 fail threshold

Ceramic⁽¹⁾

0.22

V2_fail

V2 forced

2

1. Placement close to the PAD

36/68

Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

7.6

Reset generator (V1 supervision)

The voltages are referred to GND and currents are assumed positive, when the current

flows into the pin. 5.25V < V = 18V; T = -40 to 130 °C, unless otherwise specified.

S

j

Table 15. Reset generator

Item

Symbol

Parameter

Test condition

_S,V_V1inc. /

Min. Typ. Max. Unit

V

7.6.1

V_RT1

Reset threshold voltage1

Reset threshold voltage2

4.5 4.63 4.75

4.25 4.37 4.5

V

decreasing

V_S,V_V1inc. /

decreasing

7.6.2

7.6.3

V_RT2

V1 > 1V,

Reset pin low output

voltage

V_RESET

0,2

0,4

I_RESET= 1mA

7.6.4

7.6.5

7.6.6

R_RESET

t_RR

Reset pull up int. resistor

Reset reaction time

60

6

110 204

kΩ

µs

@Iload = 1mA

40

V1 under-voltage filter time

16

7.7

Watchdog

6V < V < 18V; 4.8V < V1 < 5.2V; T = -40 to 130 °C, unless otherwise specified

S

j

(1)

Table 16. Watchdog

Item

Symbol

Parameter

Test condition Min.

Typ.

Max. Unit

7.7.1

7.7.2

7.7.3

7.7.4

t_LW

t_CW

Long open window

Closed window

48,75

4.5

65

6

81,25

7.5

ms

t_OW

Open window

7.5

10

2

12.5

2. 5

t_WDR

Watchdog reset pulse time

1.5

1. See Figure 13.

Doc ID 13518 Rev 5

37/68

Electrical characteristics

L9952GXP

Figure 13. Watchdog timing

Normal startup operation and timeout failures

T_LW

= long window < 65ms

T

= closed window < 6ms

= open window < 10ms

CW

= correct trigger timing

= early trigger timing

T

OW

T_WDR= watchdog reset = 2ms

= missing trigger

T

+ T

T

+ T

CW OW

CW

OW

T

CW

T

LW

WD-

trigger

trigger signal

time / ms

T_LW

NRES-

Out

T

WDR

normal operation

missing

trigger

early

write

0

time / ms

Missing uC trigger signal

WD-

trigger

T

LW

time / ms

NRES-

Out

T_WDR

T

W DR

time / ms

0

38/68

Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

Figure 14. Watchdog, closed and open window tolerances and save trigger area

TWD = nominal trigger time

TCW = closed window

TOW = open window

TWD= 10ms

TOW, max

TCW, max

TCW, min

TOW, min

watchdog failure

undefined

save trigger area

time / ms

7.5

12

20

4.5

7.8

High side outputs

7.8.1

Output (Out_HS)

The voltages are referred to gnd and currents are assumed positive, when the current flows

into the pin. 6V < V < 18V; 4.8V < V1 < 5.2V; T = -40°C...130°C, unless otherwise

S

j

specified.

Table 17. High side outputs (Out_HS)

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

Static Drain Source

Tj = 25°C

0

1.0

1.6

1.5

3

Ω

R_DSON

OUT_HS

7.8.1

On-resistance to supply

(IOUT_HS=150mA)

Tj = 125°C

7.8.2

7.8.3

td_ONHS

Switch on delay time

Switch off delay time

0.2 VS

0.8VS

10

40

35

95

60

µs

td_OFFHS

150

64*

Tested by scan

chain

7.8.4

td_SDHS

Short circuit filter time

T_OSC

Tested by scan

chain

400*

T_OSC

7.8.5

7.8.6

7.8.7

td_ARHS

dVout/dt

I_OSDHS

Auto recovery filter time

Slew rate

0.2

0.5

0.8 V/µs

Short circuit shutdown

current

480 900 1320 mA

Open load detection

current

7.8.8

I_OLD

40

80

120

mA

Doc ID 13518 Rev 5

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Electrical characteristics

L9952GXP

7.8.2

Outputs (OUT1...4)

The voltages are referred to GND and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; 4.8V < V1 < 5.2V; T = -40°C...130°C, unless otherwise

S

j

specified.

Table 18. High side outputs (OUT 1..4)

Item

Symbol

Parameter

On – resistance

Test condition

Min. Typ. Max. Unit

I_LOAD= 60mA @

Tj=+25°C

7.8.11

R_DSON

0

7

12

Ω

Short circuit shutdown

current

7.8.12

7.8.13

7.8.14

I_OUT

I_OLD1

I_OLD2

8V < Vs < 16V

140 235 330

mA

Open load detection

current 1

Selectable via SPI

0.8

6

2

8

4

Open load detection

current 2

13

7.8.15

7.8.16

7.8.17

SR

Slew rate

0.2

10

40

0.5

35

95

0.8 V/µs

t_dONHS

t_dOFFHS

Switch ON delay time

Switch OFF delay time

0.2 V_S

0.8 V_S

60

µs

150

64*

Tested by scan

chain

7.8.18

7.8.19

t_SCF

Short circuit filter time

T_OSC

Loss of GND current

(ESD structure)

(1)

I_FW

100

mA

1. Parameter guaranteed by design

7.9

Relay drivers

The voltages are referred to GND and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; 4.8V < V1 < 5.2V; T = -40 to 130 °C, unless otherwise

S

j

specified.

Table 19. Relay drivers

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

ILOAD = 100mA @

Tj = +25°C

7.9.1

R_DSON

DC output resistance

0

2

3

Ω

Short circuit shutdown

current

7.9.2

7.9.3

7.9.4

I_OUT

V_Z

8V < Vs < 16V

I_LOAD= 100mA

250 375 500

mA

V

Output clamp voltage ⁽¹⁾

40

5

48

Turn on delay time to 10%

V_OUT

t_ONHL

50

100

µs

Turn off delay time to 90%

V_OUT

7.9.5

t_OFFLH

5

100

µs

40/68

Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

Min. Typ. Max. Unit

Table 19. Relay drivers (continued)

Item

Symbol

Parameter

Test condition

64*

Tested by scan

chain

7.9.6

7.9.7

t_SCF

SR

Short circuit filter time

Slew Rate

T_OSC

0.2

2

4

V/µs

1. The output is capable to switch off relay coils with the impedance of RL=160Ω; L = 300mH

(RL=220Ω; L= 420mH); at V_S= 40V (Load dump condition)

7.10

Wake up inputs ( WU1..WU4)

The voltages are referred to GND and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; T = -40 to 130 °C, unless otherwise specified.

S

j

(1)

Table 20. Wake up inputs (WU1...WU4)

Item

Symbol

Parameter

Test condition

Min.

Typ.

Max. Unit

Wake-up negative

edge threshold voltage

7.10.1 V_WUthp

7.10.2 V_WUthn

0.4 Vs 0.45 Vs 0.5 Vs

V

Wake-up positive edge

threshold voltage

0.5 Vs 0.55 Vs 0.6 Vs

0.05 Vs 0.1 Vs 0.15 Vs

V

7.10.3

7.10.4

V_HYSTHysteresis

Minimum time for

wake-up

t_WU

51

10

64

20

77

30

µs

Input current in standby

mode

7.10.5 I_{WU_stdby}

1.5V<V_IN< (Vs-3V)

µA

Input resistor to GND in

active mode and in

standby mode during

wake-up request

7.10.6 R_{WU_act}

100

275

450

kΩ

During OUT_HS

on, cyclic sense

mode (100us

7.10.7

Nn

Number of samples

2 (at 80µs and 100µs)

cyclic HS on time)

Pending wake up

request low threshold

7.10.8

7.10.9

V_wuthl

1.0

1.25

1.5

V

Pending wake up

request high threshold

V_wuthh

Vs-3

Vs-2.2 Vs-1.4

1. Defines whether the inputs W1..4 are configured with current source or current sink in standby mode.

Doc ID 13518 Rev 5

41/68

Electrical characteristics

L9952GXP

7.11

Wake up input (INH)

The voltages are referred to GND and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; T = -40 to 130 °C, unless otherwise specified.

S

j

Table 21. Wake up input (INH)

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

Wake-up activate

threshold current

7.11.1

I_INHth

30

75

70

120

µA

Wake-up passive

threshold current

7.11.2

I_INHUth

Wake-up current

hysteresis

7.11.3

7.11.4

I_INHhys

t_WU

10

64

20

77

µA

µs

Minimum time for wake-up

51

During OUT_HS

on, cyclic sense

mode (100µs cyclic

HS on time)

2 (at 80us and

100us)

7.11.5

Nn

Number of samples

7.12

LIN

Compatible to Lin 2.1 for Baud rates up to 20 kBit/s

The voltages are referred to GND and currents are assumed positive, when the current

flows into the pin.

6V < V < 18V; 4.8V < V1 < 5.2V; T = -40°C...130°C, unless otherwise specified.

S

j

Table 22. LIN receiver

Item

Parameter

Symbol

LIN

Test condition

Min. Typ. Max. Unit

LIN receiver

Input voltage

dominant level

7.12.1

7.12.2

7.12.3

V_TXDLOW

V_TXDHIGH

V_TXDHYS

Normal mode, V1=5V

1

1.3

2.2

0.8

V

Input voltage

recessive level

2.5

-60

V_TXDHIGH

V_TXDLOW

-

Normal mode, V1=5V

Normal and

0.5

-5

TXD pull up

current

7.12.4

I_TXDPU

-30

µA

V1-standby mode ,

V1=5V

V_BAT- standby mode,

V_TXDHIGH

TXD pull-down

current

7.12.5

7.12.6

I_TXDPD

5

30

60

µA

V

V1=5V

Output voltage

dominant level

Normal mode, V1=5V,

2mA

V_RXDLOW

0.2

1.5

42/68

Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

Min. Typ. Max. Unit

Table 22. LIN receiver (continued)

Item

LIN

Parameter

Symbol

Test condition

LIN receiver

Output voltage

recessive level

Normal mode, V1=5V,

2mA

7.12.7

7.12.8

V_RXDHIGH

4.5

V

Receiver threshold

voltage recessive

to dominant state

0.4

V_S

0.45

V_S

0.5

V_S

V_THdom

Receiver threshold

voltage dominant

to recessive state

0.5

V_S

0.55

V_S

0.6

V_S

7.12.9

V_THrec

V

0.1

V_S

Receiver threshold

hysteresis

0.07

V_S

0.175

V_S

7.12.10

7.12.11

7.12.12

7.12.13

7.12.14

V_THhys

V_THrec- V_THdom

V

0.5

V_S

Receiver tolerance

center value

0.475

V_S

0.525

V_S

V_THcnt

(V_THrec+ V_THdom) / 2

Receiver wakeup

threshold voltage

V_THwkup

V_THwkdwn

Tbus

1.0

1.5

2

V

3.5

Vs

2.5

Vs

1.5

Vs

Receiver wakeup

threshold voltage

V

Sleep mode

Dominant time for

wakeup via bus

64

µs

edge: rez.- dom.

Table 23. LIN DC parameters

Item

LIN

Parameter

Symbol

Test condition

Min. Typ. Max. Unit

DC parameters

Transmitter input

current limit in

dominant state

V_TxD= V_TxDlow

7.12.15

I_LINDomSC

40

-1

100

180

mA

µA

V_LIN= Vbatmax = 18V

Input leakage

current at the

receiver incl.

V_TxD= V_TxDhigh

7.12.16 I_{bus_PAS_dom}

V_LIN= 0V V_BAT=12V,

,

Slave mode

Pull-Up resistor

V_TxD= V_TxDhigh

8V<V_LIN,V_BAT<18V;

Transmitter input

7.12.17 I_{bus_PAS_drec}current in

recessive state

20

V_LIN≥ V_BAT

GND = Vs,

Input current if loss

of GND at Device

7.12.18 I_{bus_NO_GND}

-1

1

mA

µA

0V<V_LIN<18V

V_BAT=12V

GND = Vs,

Input current if loss

of Vbat at device

7.12.19

I_bus

100

0V<V_LIN<18V

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Electrical characteristics

L9952GXP

Table 24. LIN transmitter (continued)

Item

Parameter

Symbol

Test condition

Min. Typ. Max. Unit

LIN

LIN transmitter

V_TxD= V_TxDlow

LIN voltage level in

dominant state

7.12.20

7.12.21

7.12.22

V_LINdom

V_LINrec

R_LINup

1.2

60

V

I_LIN= 40mA

V_TxD= V_TxDhigh

I_LIN= 10µA

LIN voltage level in

recessive state

0.8

Vs

LIN output pull up

resistor

V_LIN= 0V

20

40

kΩ

Table 25. LIN timing

Parameter

LIN timing

Item

Symbol

Test condition

Min. Typ. Max. Unit

tTXpd_sym =

Symmetry of

transmitter

propagation delay

time (rising vs.

falling edge)

= tTXpdr – tTXpdf

Vs=12V,

7.12.24

t_{TXpd_sym}

-2.5

-

2.5

µs

Rbus Cbus:

1 kΩ, 1 nF

tRXpd =

= max (tRXpdr tRXpdf)

tRXpdf =

=t(0.5RXD)-t(0.45 VLin)

tRXpdr =

Receiver

propagation delay

time

=t(0.5RXD)-t(0.55 VLin)

7.12.25

t_RXpd

-

6

µs

Crxd = 20pF

Vs = 12V,

Rbus Cbus:

1 kΩ, 1 nF;

660 Ω, 6.8 nF;

500 Ω,10 nF

Symmetry of

receiver

7.12.26 tRXpd_sym propagation delay

time (rising vs.

tRXpd_sym =

-2

-

2

µs

= tRXpdr – tRXpdf

falling edge)

44/68

Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

Min. Typ. Max. Unit

Table 25. LIN timing (continued)

Parameter

Item

Symbol

Test condition

LIN timing

THRec(max)=0.744*Vs

THDom(max)=0.581*Vs

Vs= 7...18V, tbit= 50us,

7.12.27

D1

Duty cycle 1

D1=tbus_rec(min)/(2xtbit) 0.396

-

Rbus, Cbus: 1 kΩ, 1 nF;

660 Ω, 6.8 nF;

500 Ω, 10 nF

THRec(min)=0.284*Vs;

THDom(min)=0.422*Vs,

Vs= 7.6 ...18V,

tbit= 50µs,

D1=tbus_rec(max)/(2xtbit)

Rbus, Cbus:

7.12.28

7.12.29

7.12.30

D2

D3

D4

Duty cycle 2

Duty cycle 3

Duty cycle 4

-

0.581

1 kΩ, 1 nF;

660 Ω, 6.8 nF;

500 Ω, 10 nF

THRec(max)=0.778*Vs;

THDom(max)=0.616*V,

Vs= 7...18V tbit= 96µs,

D3 =tbus_rec(min)/(2xtbit)

0.417

Rbus, Cbus: 1 kΩ, 1 nF;

660 Ω, 6.8 nF;

500 Ω, 10 nF

THRec(min)=0.251*Vs;

THDom(min)=0.389*Vs,

Vs= 7.6 ...18V,

tbit= 96µs

D1=tbus_rec(max)/(2xtbit)

Rbus, Cbus:

0.59

1 kΩ, 1 nF;

660 Ω, 6.8 nF;

500 Ω,10 nF

Table 26. LIN DC values

Item

Parameter

Symbol

Test condition

Min. Typ. Max. Unit

LINPU

DC values

7.12.31

7.12.32

R_DSon

I_leak

ON resistance

10.5

16

1

Ω

Leakage current

uA

Doc ID 13518 Rev 5

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Electrical characteristics

L9952GXP

Figure 15. LIN transmit, receive timing

t_T

X pdr

X pdf

V _{T xD}

tim e

V

LIN r ec

8 0 %

V

V _{L IN}

T

H

r ec

V _T

V

H

dom

2 0 %

LIN dom

tim e

V _{R xD}

t_R

X pdr

X pdf

46/68

Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

7.13

Operational amplifier

The voltages are referred to gnd and currents are assumed positive, when the current flows

into the pin. 6V < V < 18V; T = -40...130°C, unless otherwise specified.

S

j

Table 27. Operational amplifier

Item

Symbol

Parameter

GBW product

Test condition

Min. Typ. Max. Unit

7.13.1

7.13.2

7.13.3

7.13.4

GBW

AVOL_DC

PSRR

V_off

1

3.5

7.0 MHz

DC open loop gain

Power supply rejection

Input offset voltage

80

-5

dB

DC, Vin =150 mV

+5

3

mV

V

Common mode input

range

7.13.5

7.13.6

V_ICR

-0.2

0

0.2

V_S

V_OH

Output voltage range high Iload = 1mA to Gnd

V_S

V

7.13.7

7.13.8

7.13.9

7.13.10

7.13.11

V_OL

I_lim+

I_lim-

Output voltage range low

Output current limitation +

Output current limitation -

Slew rate positive

Iload = 1mA to V_S

0

5

0.2

20

V

DC

10

-10

4

mA

V/µs

-5

1

-20

10

SR+

SR-

Slew rate negative

-1

-4

-10 V/µs

Note:

The operational amplifier is on-chip stabilized for external capacitive loads C_L< 25pF (all operating

conditions)

Doc ID 13518 Rev 5

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Electrical characteristics

L9952GXP

7.14

SPI

7.14.1

Input: CSN

The voltages are referred to ground and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; 4.5V < V1 < 5.3V; all outputs open; T = -40°C...130°C,

S

j

unless otherwise specified.

Table 28. SPI (Input CSN)

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

Active mode,

V1 = 5V

7.14.1

V_CSNLOW

Input voltage low level

0.5

1

1.0

1.6

V

Active mode,

V1=5V

7.14.2

7.14.3

V_CSNHIGH

V_CSNHYS

Input voltage high level

1.75 2.5

Active mode,

V1=5V

VCSNHIGH - VCSNLOW

0.5

1.0

-30

30

1.5

-60

60

Active mode and

V1 Standby

mode,V1=5V

7.14.4

7.14.5

I_CSNPU

CSN pull up current

-5

5

µA

In V_bat- standby

mode

I_CSNPD

CSN pull-down current

7.14.2

Inputs: CLK, DI, PWM 1, PWM 2

The voltages are referred to ground and currents are assumed positive, when the current

flows into the pin. 6V< V <18V; 4.5V < V1 < 5.3V; all outputs open; T = -40°C...130°C,

S

j

unless otherwise specified.

Table 29. Inputs: CLK, DI, PWM 1, PWM 2

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

Switching from

standby to active

mode. Time until

output drivers are

enabled after CSN

going to high.

Delay time from standby

to active mode

7.14.6

t_set

160 300

µs

7.14.7

7.14.8

7.14.9

7.14.10

V_{in L}

V_{in H}

V_{in Hyst}

I _in

Input low level

Input high level

Input hysteresis

V1 = 5 V

1.0 2.05 2.5

V

1.5

2.8

3.3

0.4 0.75 1.5

V

Pull down current at input V_in= 1.5 V

Input capacitance at input

CSN, CLK, DI and

PWM_1,2

5

30

10

60

15

µA

(1)

7.14.11

7.14.12

C_in

0V < V1 < 5.3V

pF

SPI input frequency at

CLK

f_CLK

1

MHz

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

48/68

Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

7.14.3

Input PWM 2 Vth for flash mode

The voltages are referred to ground.

6V < V < 18V; 4.5V < V1 < 5.3V; all outputs open; T = -40°C...130°C, unless otherwise

S

j

specified.

Table 30. Input PWM2 Vth for flash mode

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

7.14.13

V_{in L}

Input low level (Vin rising))

V1 = 5 V

6.1 7.25 8.4

V

Input high level

(Vin falling)

7.14.14

7.14.15

V_{in H}

V1 = 5 V

7.4

0.6

8.4

0.8

9.4

1.0

V_{in Hyst}

Input hysteresis

7.14.4

DI timing

The voltages are referred to ground and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; 4.5V < V1 < 5.3V; all outputs open; T = -40°C...130°C,

S

j

unless otherwise specified.

Table 31. DI timing

Item

Symbol

Parameter

Clock period

Test condition

Min. Typ. Max. Unit

7.14.16

7.14.17

7.14.18

t_CLK

t_CLKH

t_CLKL

V1 = 5 V

1000

400

-

ns

Clock high time

Clock low time

400

CSN setup time, CSN low

before rising edge of CLK

7.14.19

7.14.20

t_{set CSN}

t_{set CLK}

V1 = 5 V

400

-

ns

CLK setup time, CLK high

before rising edge of CSN

7.14.21

7.14.22

t_{set DI}

DI setup time

DI hold time

V1 = 5 V

200

-

ns

t_{hold DI}

Rise time of input signal

DI, CLK, CSN

7.14.23

7.14.24

t_{r_in}

V1 = 5 V

-

100

ns

Fall time of input signal

DI, CLK, CSN

t_{f_in}

Doc ID 13518 Rev 5

49/68

Electrical characteristics

L9952GXP

7.14.5

DO, FSO, Dig_Out3,4

The voltages are referred to ground and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; 4.5V < V1 < 5.3V; all outputs open; T = -40°C...130°C,

S

j

unless otherwise specified.

Table 32. DO, FSO, Digout3,4

Item

Symbol

Parameter

Output low level

Test condition

Min. Typ. Max. Unit

7.14.25

7.14.26

V_DOL

V_DOH

V1 = 5 V, I_D= -4mA

0.5

V

Output high level

V = 5 V, I_D= 4 mA 4.5

V_CSN= V1,

-10

(1)

7.14.27

7.14.28

I_DOLK

Tristate leakage current

10

15

uA

pF

0 V < V_DO<´V1

V_CSN= V1,

C_DO

Tristate input capacitance

10

0 V < V1 < 5.3 V

1. Not valid for FSO

7.14.6

DO timing

The voltages are referred to ground and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; 4.5V < V1 < 5.3V; all outputs open; T = -40°C...130°C,

S

j

unless otherwise specified.

Table 33. DO timing

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

C_L= 100 pF,

I_load= -1 mA

7.14.29

t_{r DO}

DO rise time

-

50

100

ns

C_L= 100 pF,

I_load= 1 mA

7.14.30

7.14.31

t_{f DO}

DO fall time

C_L= 100 pF,

DO enable time

t_{en DO tri L}

I

_load= 1 mA

-

50

250

ns

from tristate to low level

pull-up load to V1

C_L= 100 pF,

DO disable time

7.14.32

7.14.33

t_{dis DO L tri}

I_load= 4 mA

from low level to tristate

pull-up load to V1

C_L= 100 pF,

I_load= -1 mA

DO enable time

t_{en DO tri H}

-

50

250

ns

from tristate to high level

pull- down load to

GND

C_L= 100 pF,

I_load= -4 mA

DO disable time

7.14.34

7.14.35

t_{dis DO H tri}

-

50

250

ns

from high level to tristate

pull-down load to

GND

V_DO< 0.3 V1,

t_{d DO}

DO delay time

V_DO> 0.7 V1,

C_L= 100 pF

50/68

Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

7.14.7

CSN timing

The voltages are referred to ground and currents are assumed positive, when the current

flows into the pin. 6V < V < 18V; 4.5V < V1 < 5.3V; all outputs open; T = -40°C...130°C,

S

j

unless otherwise specified.

Table 34. CSN timing

Item

Symbol

Parameter

Test condition

Min. Typ. Max. Unit

Transfer of SPI-

command to input

register

Minimum CSN HI time,

active mode

7.14.36

t_{CSN_HI,min}

6

-

µs

Figure 16. SPI - Input timing

0.8 VCC

0.2 VCC

CSN

t_{set CSN}

t_CLKH

t_{set CLK}

0.8 VCC

0.2 VCC

CLK

t_{set DI}

t_{hold DI}

t_CLKL

0.8 VCC

0.2 VCC

DI

Valid

Doc ID 13518 Rev 5

51/68

Electrical characteristics

L9952GXP

Figure 17. SPI - Edges timing

Tf

Tr

CLK

0.8 Vcc

0.5 Vcc

0.2 Vcc

CLK

Tr_DO

0.8 Vcc

0.2 Vcc

DO

(low to high

Td_DO

Tf_DO

0.8 Vcc

0.2 Vcc

DO

(high to low

Tf_CSN

Tr_CSN

0.8 Vcc

0.5 Vcc

0.2 Vcc

CSN

50 %

Ten

DO_tri_L

Tdis_{DO_L_tri}

50 %

Ten_{DO_tri_H}

Tdis_{DO_H_tri}

52/68

Doc ID 13518 Rev 5

L9952GXP

Electrical characteristics

Figure 18. SPI - CSN low to high transition

CSN low to high: data from shift register

is transferred to output power switches

t_{r in}

t_{f in}

t

CSN_HI,min

80%

50%

20%

CSN

t_dOFF

80%

50%

20%

output current

of a driver

ON state

OFF state

t_OFF

t_ON

t_dON

80%

50%

20%

output current

of a driver

OFF state

ON state

Figure 19. SPI - High to low transition

CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO

CSN

CLK

time

DI

time

DI: data is not accepted

0

-

DO

time

DO: status information of data bit 0 (fault condition) will stay as long as CSN is low

Doc ID 13518 Rev 5

53/68

SPI control and status registers

L9952GXP

8

SPI control and status registers

8.1

SPI registers

24bit shift register: first 2 bits are address (A1,A0) and 22 bits are data.

During power-on reset, all registers are set to zero.

Table 35. SPI registers

D23

D22 D21

D20

D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06

D05

D04 D03 D02 D01 D00

A1

A0

Data

Address

[write]

On5V2

On Signals

Control

Register 0

ON

V21

OUT

HS2

HS

42

GO

VCC

ON

V20

REL REL

OUT OUT

HS1 HS0

HS

41

HS

40

HS

32

HS

31

HS

30

HS

22

HS

21

HS

20

HS

12

HS

11

HS

10

GO

V_BAT

TRIG

2

1

0

Address

Timer

2

Timer

1

[write]

Loop

Pullup / down

Wakeup Sources OL

Wakeup Sources

Control

Register 1

CLR INT_en T20 T13 T12

T11

T10

L2

L1

L0

U3

U2

U1

U0

W7

W6

W5

W4

W3 W2 W1 W0

0

1

Address

[write]

Input config

Reset level

LEV LEV TXT

LIN

Openload treshold

Control

Register 2

IC

41

IC

40

IC

31

IC

20

IC

11

IC

10

LS

OVUV

OLT OLT OLT OLT

HS4 HS3 HS2 HS1

O_HS VLOCK

LIN

Slope

RES I_CMP

LINPU

REC

OUT

1

0

TOUT

30

21

1

0

Address

[read]

Reserved

Wakeup

L I N

Wakeup input status

Overcurrent

Openload

Status

Register 0

SHT5 Rel2

HS

OC

HS2

OC

HS

OL

HS4 HS3 HS2 HS1

Rel1

OC

HS4 HS3

OC OC

HS1

OC

COLD

START

RES

I NH

WU4 WU3 WU2 WU1

V2

OC

OL

Err Err

Address

5V Restarts

Reserved

LIN State

Watchdog Reset

State

Status

Register 1

WD

3

WD WD

WD

0

TSD TSD

DOM SHT SHT

TXD BAT GND

VCC

Fail

VCC₁

Fail

2

RES RES

TRIG

R2

R1

R0 ST1 ST0

TW UV

OV

2

1

2

1

Err

Address

Note:

During the shift in of the address bits, (2 clock periods) an internal error bit (Err) is fed to the

DO output.

D23,D22 -> error flags (seen from DO)

The error flag is generated by logic OR combination of following error bits:

VCC_Fail1,2; TSD1,2; TW; OV,UW; OC_HS1..4; OC_OUTHS; OC_REL1..2; OC_V2

54/68

Doc ID 13518 Rev 5

L9952GXP

SPI control and status registers

8.1.1

Control register 0

While writing to the control register 0, the status register 0 can be read at the DO-Output of

the SPI.

Table 36. Control register 0

5V2

Driver ON Signals

Bit

21

w

20

w

19

w

18

w

17

w

16

w

15

w

14

w

13

w

12

w

11 10

9

w

0

8

w

0

7

w

0

6

w

0

5

w

0

4

w

0

3

w

0

2

w

0

1

w

0

w

0

Access

Reset

w

0

w

0

GO GO

ON

V21 V20

ON REL REL

HS HS HS HS HS HS HS HS HS HS HS HS

OUT OUT OUT

HS2 HS1 HS0

Name

TRIG

V1

V

2

1

42 41 40 32 31 30 22 21

20

12 11 10

bat

x

Table 37. Configuration bit HSxx

Name / state

Definition/ function

HSx2 HSx1 HSx0 Defines the output configuration of the High Side Drivers 1-4

Table 38. Configuration bit OUT_HSx

Name / state

Definition/ function

OUT_HS OUT_HS OUT_HS

Defines the output configuration of the High Side Driver OUT_HS

2

1

0

1

Driver is OFF in all modes

Driver is ON in active mode, off in standby mode

Driver is cyclic ON with the timing of Timer 1 in active mode and standby

modes

0

1

0

1

Driver is cyclic ON with the timing of Timer 2 in active mode and standby

modes

1

0

1

Driver is controlled by the PWM1 Input

Driver is controlled by the PWM2 Input

Table 39. Configuration bit RELx

Name / state

Definition/ function

RELx

Defines the Output configuration of the low side relay drivers 1/2

Driver is OFF in all modes

0

1

Driver is ON in active mode (off in standby mode)

Table 40. Configuration bit On_V2x

Name / state

Definition/ function

On_V21

0

On_V20 Defines in which modes the voltage regulator 2 is on

0

Voltage regulator 2 is OFF in all modes

Doc ID 13518 Rev 5

55/68

SPI control and status registers

L9952GXP

Table 40. Configuration bit On_V2x (continued)

Name / state

Definition/ function

Voltage regulator 2 is ON in ACTIVE mode;

OFF in V₁-standby, V_Bat-standby

0

1

Voltage regulator 2 is ON in ACTIVE mode and V₁standby;

OFF in V_bat-standby

1

0

1

Voltage regulator 2 is ON in all modes

Table 41. Configuration bit TRIG, GO_VBAT, GO_V1

Trigger bit for watchdog; inverted for each Trigger event invert this bit for a

proper watchdog trigger.

TRIG

”1” enters the V_bat-standby mode. (dominant mode, if both standby modes

are selected)

GO_VBAT

GO_V1

“1” enters the V₁-standby mode.

8.1.2

Control register 1

While writing to the control register 1, the status register 1 can be read at the DO-Output of

the SPI.

Table 42. Control register 1

Cyclic Timer 1/2

Loop

13

w

Pull up

Wakeup Sources

Bit

21

w

20

w

19

w

18

w

17

w

16

w

15

w

14

w

12

w

11

w

10

9

w

8

w

7

w

6

w

5

w

4

w

3

w

2

w

1

w

0

w

Access

Reset

Name

w

0

CLR INT_EN T20 T13 T12 T11 T10

L2

L1

L0

U3

U2

U1

U0

W7

W6

W5

W4

W3

W2

W1

W0

Table 43. Configuration bit Wx

Name/state

Definition/function

W7 W6 W5 W4 W3 W2 W1 W0 Disables the corresponding wake up sources

x

1

x

1

x

1

x

1

x

Input WU1 is disabled as wake up source

Input WU2 is disabled as wake up source

Input WU3 is disabled as wake up source

Input WU4 is disabled as wake up source

Open load Appearance / Disappearance at OUT1 is

disabled as wake up source

x

1

x

1

x

1

x

Open load Appearance / Disappearance at OUT2 is

disabled as wake up source

Open load Appearance / Disappearance at OUT3 is

disabled as wake up source

56/68

Doc ID 13518 Rev 5

L9952GXP

SPI control and status registers

Definition/function

Table 43. Configuration bit Wx (continued)

Name/state

Open load Appearance / Disappearance at OUT4 is

disabled as wake up source

1

0

x

0

Default: all wake up sources are enabled

Table 44. Configuration bit Ux

Name/state

Definition/function

Defines whether the Inputs WU1..4 are configured with current source or

current sink in standby mode.

U3 U2 U1 U0

Input WU1 configured with a current source in standby mode

x

1

0

x

1

x

0

x

1

x

0

1

x

0

(R_{WU_act}pulldown resistor in active mode - see Table 20.)

Input WU2 configured with a current source in standby mode

(R_{WU_act}pulldown resistor in active mode - see Table 20.)

Input WU3 configured with a current source in standby mode

(R_{WU_act}pulldown resistor in active mode - see Table 20.)

Input WU4 configured with a current source in standby mode

(R_{WU_act}pulldown resistor in active mode - see Table 20.)

Default: All Inputs configured with a current sink in standby

(R_{WU_act}pulldown resistor in active mode - see Table 20.)

Table 45. Configuration bit Lx

Name/state

Definition/function

Defines which signal is looped to the Dig_Out3 and Dig_Out4

(see note)

L2

L1

L0

Dig_Out3

WU3 (default)

HighZ

Dig_Out4

WU4 (default)

WU4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

WU3

HighZ

WU3

Open Load HS2

WU4

Open Load HS1

HighZ

Open Load HS2

HighZ

Open Load HS2

Doc ID 13518 Rev 5

57/68

SPI control and status registers

L9952GXP

Table 46. Configuration bit Txx

Name/state

Definition/function

Defines the period of the cyclic sense Timer 1 which is selectable for Out

1..4 and Out_HS (see ON signals control register 0)

T12

T11

T10

0

1

0

1

0

1

0

1

0

1

Period: 0.5 s

Period: 1.0 s

1

Period: 1.5 s

1

Period: 2.0 s

0

Period: 2.5 s

0

Period: 3.0 s

1

Period: 3.5 s

1

Period: 4.0 s

T13

0

Defines the ON time for the cyclic sense Timer1

ON time 10 ms

ON time 20 ms

1

Defines the ON time of the cyclic sense Timer 2 which is selectable for Out

1..4 and OUTHS (see ON Signals control register 0)

T20

0

1

Period 50 ms / ON time 100 us

Period 50 ms / ON time 1ms

Table 47. Configuration bit INT_enable

Name/state

Definition/function

INT_enable

0

1

Interrupt Mode disabled ( see Section 2.7 )

Interrupt Mode enabled

CLR

Clears the contents of status register 0 and 1

Note:

In V

standby mode, DigOut 3 and DigOut4 are HighZ.

BAT

58/68

Doc ID 13518 Rev 5

L9952GXP

SPI control and status registers

8.1.3

Control register 2

While writing to the control register 2, the status register 0 can be read at the DO-Output of

the SPI.

Table 48. Control register 2

Input filter configuration

Reset

level

LIN

Open load threshold

Bit

21

W

0

20

19

W

0

18

W

0

17

W

0

16 15 14 13

12 11 10

9

8

W

0

7

W

0

6

W

0

5

W

0

4

W

0

3

W

0

2

W

0

1

W

0

W

0

Access

Reset

W

0

W

0

W

0

W

0

W

0

W

0

W

0

W

0

VS

Lock

Out

LSO

VUV Slope

LIN

IC

41

IC

IC LEV LEV

TXDT

Out

LINP

U

O_HS

REC

OLT OLT OLT OLT

HS4 HS3 HS2 HS1

Name

RES

I

CMP

40 31 30 21

20 11 10

1

0

Table 49. Configuration bit OLT_HSx, VSLOCK Out, O_HS_REC, LINPU and

TXD_TOUT

Name/state

Definition/function

Open load threshold for the High Side Drivers Out1..4

0: Iopenload = 2mA; 1: Iopenload = 8mA

OLT_HSx

Automatic recovery after VS Over/Under voltage

“0” (default): Vs lockout is disabled, i.e. outputs will automatically recover (according

to output settings in CR0) after Vs over / under - voltage conditions has disappeared

VSLOCK

Out

“1”: Vs lockout is enabled, i.e. outputs will remain Off after Vs over / under voltage

recovery conditions has disappeared, until the Vs over / under voltage Status Bits

(SR1, bit s0,1) are cleared by CLR command (CR1, bit 21).

O_HS_REC “1” = Recovery mode for OUT_HS Driver.

LINPU “1” will disable the master pull up LINPU

TXD_TOUT “1” will disable the dominant TxD time-out for the LIN Interface.

Table 50. Configuration bit LEVx

Name/state

LEV1

Definition/function

LEV0

Controls the reset level

0

1

0

1

Set the reset threshold to 4.65V, typ.

Set the reset threshold to 4.35V, typ.

X

Reserved (do not use for operation, set LEV1 to “0”)

Doc ID 13518 Rev 5

59/68

SPI control and status registers

L9952GXP

Table 51. Configuration bit ICxx

Name/state

Definition/function

Selects the filter configuration for the

IC(1..4)1

IC(1..4)0

Wakeup Inputs WU1 to 4

IC11

IC21

0

1

Filter with 64 us Filter time (static sense)

Enable Filter after 80 us with a Filter time of 16 us (cyclic sensing),

timer2

Enable Filter after 800 us with a Filter time of 16 us (cyclic

sensing), timer2

IC31

IC41

1

0

1

Enable Filter after 800 us with a Filter time of 16 us (cyclic

sensing), timer1

Table 52. Configuration bit LIN slope, LS_ovuv and ICMP

Name/state

Definition/function

LIN slope

Change LIN slope

High slew rate (default)

Low slew rate

0

1

LS_ovuv

Vs Over / Under voltage shutdown of REL1,2 (low side drivers)

Enable (default): REL1,2 turned Off in case of Vs Over/Undervoltage

Disable : REL1,2 remain On in case of Vs Over/Undervoltage

Current supervision of V1 regulator in V₁-standby mode.

Enable (default)

0

1

I_CMP

0

1

Disable

RES

Reserved

60/68

Doc ID 13518 Rev 5

L9952GXP

SPI control and status registers

8.1.4

Status register 0

The contents of the status register 0 can be read implicitly, while accessing the control

register 0 or control register 2.

Table 53. Status register 0

Wakeup Inputs

Over current

Open load

Bit

21

r

20

r

19

r

18

r

17

r

16

r

15

r

14

r

13

r

12

r

11

r

10

r

9

r

8

r

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Access

Reset

0

Cold

Start

WU WU WU WU

REL REL HS

HS

HS HS HS

HS

Name

RES RES

LIN INH

SHT5V2

4

3

2

1

2OC 1OC OC 4OC 3OC 2OC 10C O L 4OL 3OL 2OL 1OL

Table 54. Configuration bit HSx_OL, HSx_OC and Relx_OC

Name/state

Definition/function

Open load status from the High Side Driver OUT1..4.

No open load has been detected.

HS1..4_OL

0

1

Open load has been detected.

HS_OL

Open load status from the High Side Driver OUT_HS

No open load has been detected.

0

1

Open load has been detected.

HS1..4_OC

Over current status from the High Side Driver OUT1..4.

No over current has been detected.

0

1

Over current has been detected.

HS_OC

Over current status from the High Side Driver OUT_HS.

No over current has been detected.

0

1

Over current has been detected.

Rel 1,2_OC

Over current status from Relais1,2

0

1

No over current has been detected.

Over current has been detected.

Table 55. Configuration bit SHT5V2, WUx, INH, LIN and Cold Start

Name/state

SHT5V2

Definition/function

V2 short to ground at turn on; condition: V2 < 2V for more than 4ms. “1” = fail

Status of the corresponding Inputs WU1..4 (according to filter settings in CR2)

WU4...WU1

Doc ID 13518 Rev 5

61/68

SPI control and status registers

L9952GXP

Table 55. Configuration bit SHT5V2, WUx, INH, LIN and Cold Start (continued)

Name/state

Definition/function

Wakeup initiated through INH source

INH

LIN

Wakeup initiated through LIN source

Set to high when the internal Power on Reset occurs.

Will be cleared with the first SPI access.

Cold Start

Note:

RES = reserved bits.

8.1.5

Status register 1

The contents of the status register 1 can be read implicitly, while accessing the control

register 1.

Table 56. Status register 1

LIN state

WD resets

5V restarts

State

Bit

21

r

20

r

19

r

18

r

17

r

16

r

15

r

14

r

13

r

12

r

11

r

10

r

9

r

8

r

7

r

6

r

5

r

4

r

3

r

2

r

1

r

0

r

Access

Reset

0

SHT

GND

WD WD WD WD

TSD TSD

DOM SHT

TXD BAT

V2

Fail

V1

Fail

Name

RES RES

TRIG

R2

R1

R0

ST1 ST0

TW

UV

OV

3

2

1

0

2

1

Table 57. Configuration bit OV, UV, TW, TSDx and Vx Fail

Name

Definition, function

OV

UV

TW

Over voltage failure of Vs.

Under voltage failure of Vs.

Temperature Warning: the chip temperature exceeds 130°C

Thermal shutdown #1: The chip temperature exceeds 140°C

All Outputs, except the voltage regulator 1 are switched off.

TSD1

TSD2

Thermal shutdown #2: The chip temperature exceeds 155°C

All Outputs, including the voltage regulator 1 are switched off.

The output of Voltage Regulator 1 failed for at least 2µs. Conditions: (V1<2V for >2µs)

OR (V1<2V at 4ms after turn-on). ‘1’= fail

V1 Fail

V2 Fail

The output of Voltage Regulator 2 failed for at least 2µs. Conditions: (V2<2V for >2µs)

OR (V2<2V at 4ms after turn-on). ‘1’= fail

Table 58. Configuration bit STx

Name

Mode

ST1 ST0

0

1

Active mode

V1-standby -> a readout is wake up condition -> active mode -> 00 is read

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Doc ID 13518 Rev 5

L9952GXP

SPI control and status registers

Table 58. Configuration bit STx (continued)

Name

Mode

1

0

1

VBat-standby, a readout is not possible, as V1 is off

Flash Mode

Table 59. Configuration bit Rx, WDx, TRIG, SHT_GND, SHT_BAT and DOM_TXD

Name

Definition, function

R2 R1 R0

Number of unsuccessfully restarts after thermal shutdown

WD3 WD2 WD1 WD0 Number of Watchdog time-outs ⁽¹⁾

TRIG

SHT_GND

SHT_BAT

DOM_TXD

RES

Status of the Trigger bit from Control Register 0

LIN Short to ground

LIN Short to battery

Dominant TXT

Reserved

1. Bits are cleared at every valid WD trigger or when forced sleep mode is entered (after 15 WD failures have

been detected)

Doc ID 13518 Rev 5

63/68

Package and packing information

L9952GXP

9

Package and packing information

9.1

ECOPACK^®packages

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

9.2

PowerSSO-36 package information

Figure 20. PowerSSO-36 package dimensions

Table 60. PowerSSO-36 mechanical data

Millimeters

Symbol

Min.

-

Typ.

Max.

2.45

2.35

0.1

A

A2

a1

b

-

2.15

0

0.18

0.23

0.36

0.32

c

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Doc ID 13518 Rev 5

L9952GXP

Package and packing information

Table 60. PowerSSO-36 mechanical data (continued)

Millimeters

Symbol

Min.

Typ.

Max.

D

E

10.10

-

10.50

7.4

7.6

e

-

0.5

8.5

2.3

-

e3

F

-

G

G1

H

h

-

0.1

-

0.06

10.1

-

10.5

-

0.4

k

0°

-

8°

L

0.55

-

0.85

M

N

O

Q

S

-

4.3

-

10 deg

-

1.2

0.8

2.9

3.65

1.0

-

T

-

U

X

-

4.1

6.5

4.7

7.1

Y

-

Doc ID 13518 Rev 5

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Package and packing information

L9952GXP

9.3

PowerSSO-36 packing information

Figure 21. PowerSSO-36 tube shipment (no suffix)

Base Qty

49

1225

532

3.5

Bulk Qty

Tube length (±0.5)

C

B

A

B

13.8

0.6

C (±0.1)

All dimensions are in mm.

A

Figure 22. PowerSSO-36 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Qty

Bulk Qty

A (max)

B (min)

C (±0.2)

F

1000

330

1.5

13

20.2

24.4

100

30.4

G (+2 / -0)

N (min)

T (max)

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

W

24

4

Tape Hole Spacing

Component Spacing

Hole Diameter

P0 (±0.1)

P

12

D (±0.05)

D1 (min)

F (±0.1)

K (max)

P1 (±0.1)

1.55

1.5

11.5

2.85

2

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

End

All dimensions are in mm.

Start

Top

cover

tape

No components Components

500mm min

No components

500mm min

Empty components pockets

sealed with cover tape.

User direction of feed

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Doc ID 13518 Rev 5

L9952GXP

Revision history

10

Revision history

Table 61. Document revision history

Date

Revision

Changes

24-Aug-2007

1

Initial release.

Table 18: High side outputs (OUT 1..4): modified openload detection

current 1 parameter value (item 7.8.13).

Table 20: Wake up inputs(WU1...WU4): modified Input current in

standby mode test condition (item 7.10.5).

07-Sep-2007

21-Sep-2007

2

3

Table 22: LIN receiver: modified symmetry of transmitter propagation

delay time parameter value (item 7.12.24).

Added Section 9.3: PowerSSO-36 packing information.

Section 7.2: Oscillator: changed Vs minimum value from 7 to 6 V.

Table 10: Supply and supply monitoring:

– changed parameter 7.1.10 (I_V(BATWU)) max value from 300 to 320 µA

– changed parameter 7.1.11 (I_V(BATWU)) max value from 380 to 410 µA.

Modified Figure 4.: Watchdog

Modified Section 2.13: Low side driver outputs Rel1, Rel2.

Added note to Section 2.2.2: Flash mode.

Section Table 48.: Control register 2: changed definition to V_SLock Out

11-Apr-2008

4

parameter.

Added Section 6.3: Package and PCB thermal data.

Modified Section 7.14.3: Input PWM 2 Vth for flash mode.

Table 42: Control register 1: modified "pull down" settings for the wake-

up inputs WU1..4 .

Table 60: PowerSSO-36 mechanical data:

– Deleted A (min) value

– Changed A (max) value from 2.47 to 2.45

– Changed A2 (max) value from 2.40 to 2.35

– Changed a1 (max) value from 0.075 to 0.1

– Added k row

08-Jul-2009

5

– Changed G (max) value from 0.075 to 0.1

Doc ID 13518 Rev 5

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L9952GXP

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Doc ID 13518 Rev 5


型号：	L9952XP
厂家：	ST
描述：	Power management system IC 电源管理系统IC
文件：	总68页 (文件大小：854K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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