L9950XPTR [STMICROELECTRONICS]
Door actuator driver; 门驱动器型号: | L9950XPTR |
厂家: | ST |
描述: | Door actuator driver |
文件: | 总39页 (文件大小:623K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
L9950
L9950XP
Door actuator driver
Features
■ One full bridge for 6A load (R =150 mΩ )
on
■ Two half bridges for 3A load (R =300 mΩ )
on
■ Two half bridges for 1.5A load (R =800 mΩ )
on
■ One highside driver for 6A load (R =100 mΩ )
on
■ Four highside drivers for 1.5 A load
PowerSSO-36
PowerSO-36
(R =800 mΩ )
on
■ Programmable softstart function to drive loads
with higher inrush currents (i.e. current
>6 A,>3 A,>1.5 A)
Applications
■ Very low current consumption in standby mode
(I < 6 μA typ; I <25 μA typ; T ≤ 85 °C)
■ Door actuator driver with bridges for door lock
and safe lock, mirror axis control, mirror fold
and highside driver for mirror defroster and four
10W-light bulbs.
S
CC
j
■ All outputs short circuit protected
■ Current monitor output for 300 mΩ, 150 mΩ
and 100 m highside drivers
Description
■ All outputs over temperature protected
■ Open load diagnostic for all outputs
■ Overload diagnostic for all outputs
■ Seperated half bridges for door lock motor
■ PWM control of all outputs
The L9950 and L9950XP are microcontroller
driven multifunctional door actuator driver for
automotive applications.Up to five DC motors and
five grounded resistive loads can be driven with
six half bridges and five highside drivers. The
integrated standard serial peripheral interface
(SPI) controls all operation modes (forward,
reverse, brake and high impedance). All
■ Charge pump output for reverse polarity
protection
diagnostic informations are available via SPI.
Table 1.
Device summary
Package
Order codes
Part number (tube)
Part number (tape and reel)
PowerSO-36
L9950
L9950TR
PowerSSO-36
L9950XP
L9950XPTR
June 2009
Doc ID 10311 Rev 10
1/39
www.st.com
1
Contents
L9950 - L9950XP
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
2.6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 21
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 21
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12 Programmable soft start function to drive loads with higher inrush current .
22
4
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
4.2
4.3
4.4
4.5
4.6
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/39
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Contents
4.7
4.8
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
6
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1
6.2
6.3
6.4
6.5
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 10311 Rev 10
3/39
List of tables
L9950 - L9950XP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definitions and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Charge pump output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
OUT1 - OUT11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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L9950 - L9950XP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI - driver turn-on/off timing, minimum csn hi time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Example of programmable soft start function for inductive loads . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. PowerSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. PowerSO-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. PowerSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 10311 Rev 10
5/39
Block diagram and pin description
L9950 - L9950XP
1
Block diagram and pin description
Figure 1.
Block diagram
VBAT
Reverse
Polarity
Protection
* Note: Value of capacitor has to be choosen carefully to limit the VS
voltage below absolute maximum ratings in case of an unexpected
100k
freewheeling condition of inductive loads (e.g. TSD, POR)
*
VS
CP
100µF
VREG
xy-Mirror
Motors
100nF
OUT1
EMC
Optimization
OUT2
OUT3
Charge
Pump
M
M
VCC
+
100
10
VCC
OUT4
OUT5
OUT6
100nF
M
Lock
Safe Lock
M
DI
**1k
**1k
**1k
**1k
DO
CLK
CSN
Folder
M
OUT7
Exterior Light
Footstep Light
Safety Light
OUT8
OUT9
PWM1
**1k
µC
OUT10
OUT11
Turn Indicator
Defroster
MUX
CM / PWM2
**1k
5
GND
** Note: Resistors between µC and L9950 are recommended to limit currents
for negative voltage transients at VBAT (e.g. ISO type 1 pulse)
+ Note: Using a ferrite instead of 10ohm will additionally improve EMC behavior
Table 2.
Pin
Pin definitions and functions
Symbol
Function
Ground.
Reference potential.
GND
1, 18, 19, 36
Important: for the capability of driving the full current at the outputs all
pins of GND must be externally connected.
Highside driver output 11.
The output is built by a highside switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy
which can be dissipated is limited. The highside driver is a power
DMOS transistor with an internal parasitic reverse diode from the
output to VS (bulk-drain-diode). The output is over-current and open
load protected.
2, 35
OUT11
Important: for the capability of driving the full current at the outputs both
pins of OUT11 must be externally connected.
6/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Block diagram and pin description
Table 2.
Pin
Pin definitions and functions (continued)
Symbol
Function
Hal bridge output 1,2,3.
The output is built by a highside and a lowside switch, which are
internally connected. The output stage of both switches is a power
DMOS transistor. Each driver has an internal parasitic reverse diode
(bulk-drain-diode: highside driver from output to VS, lowside driver from
GND to output). This output is over-current and open load protected.
OUT1
OUT2
3
4
5
OUT3
Power supply voltage (external reverse protection required.
6, 7, 14, 15,
23, 24, 25, 28,
29, 32
For this input a ceramic capacitor as close as possible to GND is
recommended.
VS
Important: for the capability of driving the full current at the outputs all
pins of VS must be externally connected.
Serial data input.
The input requires CMOS logic levels and receives serial data from the
microcontroller. The data is an 24bit control word and the least
significant bit (LSB, bit 0) is transferred first.
8
9
DI
Current monitor output/PWM2 input.
Depending on the selected multiplexer bits of Input Data Register this
output sources an image of the instant current through the
corresponding highside driver with a ratio of 1/10.000. This pin is
bidirectional. The microcontroller can overdrive the current monitor
signal to provide a second PWM input for the outputs OUT9 and
OUT10.
CM/PWM2
Chip select not input/test mode.
This input is low active and requires CMOS logic levels. The serial data
transfer between L9950 and micro controller is enabled by pulling the
input CSN to low level. If an input voltage of more than 7.5V is applied
to CSN pin the L9950 will be switched into a test mode.
10
11
CSN
DO
Serial data output.
The diagnosis data is available via the SPI and this tristate output. The
output will remain in tristate, if the chip is not selected by the input CSN
(CSN = high).
Logic supply voltage.
12
13
VCC
CLK
For this input a ceramic capacitor as close as possible to GND is
recommended.
Serial clock input.
This input controls the internal shift register of the SPI and requires
CMOS logic levels.
Half bridge output 4,5,6: see OUT1 (pin 3).
OUT4
OUT5
OUT6
16,17, 20,21,
22
Important: for the capability of driving the full current at the outputs both
pins of OUT4 (OUT5, respectively) must be externally connected.
Charge pump output.
26
CP
This output is provided to drive the gate of an external n-channel power
MOS used for reverse polarity protection
Doc ID 10311 Rev 10
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Block diagram and pin description
L9950 - L9950XP
Table 2.
Pin
Pin definitions and functions (continued)
Symbol
Function
PWM1 input.
27
PWM1
This input signal can be used to control the drivers OUT1-OUT8 and
OUT11 by an external PWM signal.
Highside driver output 7,8,9,10.
The output is built by a highside switch and is intended for resistive
loads, hence the internal reverse diode from GND to the output is
missing. For ESD reason a diode to GND is present but the energy
which can be dissipated is limited. The highside driver is a power
DMOS transistor with an internal parasitic reverse diode from the
output to VS (bulk-drain-diode). The output is over-current and open
load protected.
30
31
33
34
OUT7,
OUT8,
OUT9,
OUT10
Figure 2.
Configuration diagram (top view)
GND
OUT11
OUT1
OUT2
OUT3
VS
1
2
3
4
5
6
7
8
9
36 GND
35 OUT11
34 OUT10
33 OUT9
32 VS
Power SO36
31 OUT8
30 OUT7
29 VS
VS
DI
CM/PWM2
28 VS
Chip
CSN 10
DO 11
27 PWM1
26 CP
VCC 12
CLK 13
VS 14
25 VS
24 VS
23 VS
VS 15
22 OUT6
21 OUT5
OUT4 16
Leadframe
OUT4
OUT5
17
20
GND 18
19 GND
8/39
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L9950 - L9950XP
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 3.
Absolute maximum ratings
Symbol Parameter
Value
Unit
DC supply voltage
-0.3 to 28
40
V
V
V
VS
Single pulse tmax < 400 ms
Stabilized supply voltage, logic supply
VCC
-0.3 to 5.5
VDI, VDO, VCLK
,
Digital input/output voltage
-0.3 to VCC + 0.3
V
VCSN, Vpwm1
VCM
VCP
Current monitor output
Charge pump output
Output current
-0.3 to VCC + 0.3
V
V
A
A
-25 to VS + 11
IOUT1,2,3,6,7,8,9,10
IOUT4,5,11
5
Output current
10
2.2
ESD protection
Table 4.
ESD protection
Parameter
Value
Unit
All pins
4 (1)
8 (2)
kV
kV
Output pins: OUT1 - OUT11
1. HBM according to CDF-AEC-Q100-002.
2. HBM with all unzapped pins grounded.
2.3
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Operating junction temperature
Value
Unit
Tj
-40 to 150
°C
Doc ID 10311 Rev 10
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Electrical specifications
L9950 - L9950XP
2.4
Temperature warning and thermal shutdown
Table 6.
Symbol
Temperature warning and thermal shutdown
Parameter
Min.
Typ. Max. Unit
Temperature warning threshold junction
temperature
Tj
TjTW ON
-
-
150
°C
increasing
Temperature warning threshold junction
temperature
Tj
TjTW OFF
130
-
5
-
-
-
°C
°K
°C
decreasing
TjTW HYS Temperature warning hysteresis
-
-
Thermal shutdown threshold junction
temperature
Tj
TjSD ON
170
increasing
Thermal shutdown threshold junction
temperature
Tj
TjSD OFF
150
-
-
-
-
°C
°K
decreasing
TjSD HYS Thermal shutdown hysteresis
5
2.5
Electrical characteristics
V = 8 to 16 V, V = 4.5 to 5.3 V, T = - 40 to 150 °C, unless otherwise specified.
S
CC
j
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 7.
Symbol
Supply
Parameter
Test condition
Min. Typ. Max. Unit
Operating supply voltage
range
VS
7
-
-
28
20
V
VS = 16 V, VCC = 5.3 V
active mode
VS DC supply current
7
mA
OUT1 - OUT11 floating
IS
VS = 16 V, VCC = 0 V
standby mode
VS quiescent supply current
VCC DC supply current
-
-
-
4
1
12
3
µA
mA
µA
OUT1 - OUT11 floating
Ttest =-40 °C, 25 °C
VS = 16 V, VCC = 5.3 V
CSN = VCC , active mode
VS = 16 V, VCC = 5.3 V
CSN = VCCstandby mode
OUT1 - OUT11 floating
Ttest =-40 °C, 25 °C
ICC
VCC quiescent supply
current
25
50
VS = 16 V, VCC = 5.3 V
CSN = VCC
Sum quiescent supply
current
IS + ICC
standby mode
-
31
75
µA
OUT1 - OUT11 floating
Ttest =-40 °C, 25 °C
10/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Electrical specifications
Min. Typ. Max. Unit
Table 8.
Symbol
Overvoltage and under voltage detection
Parameter Test condition
VS increasing
VSUV ON VS UV-threshold voltage
VSUV OFF VS UV-threshold voltage
VSUV hyst VS UV-hysteresis
5.9
5.5
-
-
7.2
6.5
-
V
V
V
V
V
V
V
V
V
VS decreasing
-
0.5
-
VSUV ON - VSUV OFF
VS increasing
VSOV OFF VS OV-threshold voltage
VSOV ON VS OV-threshold voltage
VSOV hyst VS OV-hysteresis
18
17.5
-
24.5
22
-
VS decreasing
-
VSOV OFF - VSOV ON
VCC increasing
1
VPOR OFF Power-on-reset threshold
VPOR ON Power-on-reset threshold
VPOR hyst Power-on-reset hysteresis
-
-
4.4
-
VCC decreasing
VPOR OFF - VPOR ON
3.1
-
-
0.3
-
Table 9.
Symbol
Current monitor output
Parameter
Test condition
Min.
Typ.
Max. Unit
VCM
Functional voltage range VCC = 5 V
0
4
V
Current monitor output
ratio:
1
-----------------
ICM,r
0 V ≤ VCM ≤ 4 V, VCC=5 V
-
-
-
10.000
ICM / IOUT1,4,5,6,11
0 V ≤ VCM ≤ 3.8 V,
VCC = 5 V, IOut,min=500 mA,
4% +
1%FS 2%FS
8% +
ICM acc Current monitor accuracy IOut4,5,11,max = 5.9 A
IOut1,6,max = 2.9 A
-
-
(FS = full scale= 600 µA)
Table 10. Charge pump output
Symbol
Parameter
Test condition
Min.
Typ.
Max. Unit
VS = 8 V, ICP = -60 µA
VS = 10 V, ICP = -80 µA
VS ≥ 12 V, ICP = -100 µA
6
8
-
-
-
13
13
13
V
V
V
Charge pump output
voltage
VCP
10
Charge pump output
current
ICP
VCP = VS+10 V, VS =13.5 V
95
150
300
µA
Doc ID 10311 Rev 10
11/39
Electrical specifications
L9950 - L9950XP
Table 11.
Symbol
OUT1 - OUT11
Parameter
Test condition
Min. Typ. Max. Unit
VS = 13.5 V, Tj = 25 °C,
-
-
300
450
300
400
600
400
mΩ
mΩ
mΩ
IOUT1,6
VS = 13.5 V, Tj = 125 °C,
IOUT1,6 1.5 A
VS = 8.0 V, Tj = 25 °C,
IOUT1,6 1.5 A
VS = 13.5 V, Tj = 25 °C,
IOUT2,3 0.8A
VS = 13.5 V, Tj = 125 °C,
IOUT2,3 0.8 A
VS = 8.0 V, Tj = 25 °C,
IOUT2,3 0.8 A
VS = 13.5 V, Tj = 25 °C,
IOUT4,5 3.0 A
VS = 13.5 V, Tj = 125 °C,
IOUT4,5 3.0 A
VS = 8.0 V, Tj = 25 °C,
IOUT4,5 3.0 A
=
1.5A
rON OUT1, On-resistance to supply or
rON OUT6 GND
=
-
=
-
800 1100 mΩ
1250 1700 mΩ
800 1100 mΩ
=
rON OUT2, On-resistance to supply or
rON OUT3 GND
-
=
-
=
-
150
225
150
200
300
200
mΩ
mΩ
mΩ
=
rON OUT4, On-resistance to supply or
rON OUT5 GND
-
=
-
=
VS = 13.5 V, Tj = 25 °C,
IOUT7,8,9,10 = -0.8 A
-
800 1100 mΩ
1250 1700 mΩ
800 1100 mΩ
rON OUT7,
VS = 13.5 V, Tj = 125 °C,
IOUT7,8,9,10 = -0.8 A
rON OUT8,
On-resistance to supply
rON OUT9 ,
-
r
ON OUT10
VS = 8.0 V, Tj = 25 °C,
IOUT7,8,9,10 = -0.8 A
-
VS = 13.5 V, Tj = 25 °C,
IOUT11 = - 3.0 A
-
100
150
200
150
5
mΩ
mΩ
mΩ
A
VS = 13.5 V, Tj = 125 °C,
IOUT11 = - 3.0A
rON OUT11 On-resistance to supply
-
150
VS = 8.0 V, Tj = 25 °C,
IOUT11 = - 3.0 A
-
100
|IOUT1|,
|IOUT6
Output current limitation to
supply or GND
Sink and source,
VS=13.5V
3
1.5
6
-
-
-
|
Sink and source,
VS = 13.5V
|IOUT2|,
|IOUT3
Output current limitation to
supply or GND
2.5
10
A
|
Sink and source,
VS = 13.5V
|IOUT4|,
|IOUT5
Output current limitation to
supply or GND
A
|
|IOUT7|,
|IOUT8|,
|IOUT9|,
Output current limitation to
GND
Source, VS = 13.5V
1.5
-
2.5
A
|IOUT10
|
12/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Electrical specifications
Min. Typ. Max. Unit
Table 11.
Symbol
OUT1 - OUT11 (continued)
Parameter
Test condition
Output current limitation to
GND
|IOUT11
|
Source, VS = 13.5V
6
-
10
80
A
VS = 13.5 V,
corresponding lowside
driver is not active
Output delay time,
highside driver on
td ON H
td OFF H
td ON L
20
50
15
40
µs
µs
µs
Output delay time,
highside driver off
VS = 13.5 V
150
30
300
70
VS = 13.5 V,
corresponding highside
driver is not active
Output delay time,
lowside driver on
Output delay time,
lowside driver off
td OFF L
VS = 13.5 V
80
-
150
200
200
-2
300
400
400
-5
µs
µs
µs
µA
µA
Cross current protection time,
source to sink
tD HL
td ON L - td OFF H,
Cross current protection time,
sink to source
tD LH
t
d ON H - td OFF L
-
VOUT1-11=0 V, standby
mode
0
Switched-off output current
highside drivers of OUT1-11
IQLH
VOUT1-11=0 V, active
mode
-40
0
-15
0
VOUT1-6 = VS, standby
110
-15
30
180
0
µA
µA
Switched-off output current
lowside drivers of OUT1-6
mode
IQLL
VOUT1-6 = VS, active mode -40
Open load detection current
of OUT1
IOLD1
IOLD23
IOLD45
IOLD6
5
80
mA
Open load detection current
of OUT2, OUT3
15
60
30
40
150
70
60
mA
mA
mA
Open load detection current
of OUT4 and OUT5
300
150
Open load detection current
of OUT6
Open load detection current
IOLD78910 of OUT7, OUT8, OUT9,
OUT10
15
30
40
150
-
60
mA
mA
µs
Open load detection current
of OUT11
IOLD11
300
Minimum duration of open
tdOL
load condition to set the
status bit
500
3000
Minimum duration of over-
current condition to switch off
the driver
tISC
10
-
100
µs
Doc ID 10311 Rev 10
13/39
Electrical specifications
L9950 - L9950XP
Table 11.
Symbol
OUT1 - OUT11 (continued)
Parameter
Test condition
VS =13.5 V
Min. Typ. Max. Unit
dVOUT16/dt Slew rate of OUT1,OUT6
0.1
0.09
0.1
0.2
0.2
0.2
0.2
0.4 V/µs
0.4 V/µs
0.4 V/µs
0.4 V/µs
Iload = 1.5 A
VS = 13.5 V
Iload = -0.8 A
dV
/dt, Slew rate of OUT2/3 and
/dt OUT7-OUT10
OUT23
dV
OUT78910
VS = 13.5 V
dVOUT45/dt Slew rate of OUT4, OUT5
dVOUT11/dt Slew rate of OUT11
Iload = 3.0 A
VS = 13.5 V
Iload = 3.0 A
0.1
2.6
SPI - electrical characteristics
V = 8 to 16 V, V = 4.5 to 5.3 V, T = - 40 to 150 °C, unless otherwise specified. The
S
CC
j
voltages are referred to GND and currents are assumed positive, when the current flows into
the pin.
Table 12. Delay time from standby to active mode
Symbol
Parameter
Test condition
Min. Typ.
Max.
Unit
Switching from standby to active mode.
tset
Delay time Time until output drivers are enabled
after CSN going to high.
-
160
300
µs
Table 13. Inputs: CSN, CLK, PWM1/2 and DI
Symbol
Parameter
Input low level
Input high level
Test condition
Min. Typ.
Max.
Unit
VinL
VinH
VCC = 5 V
VCC = 5 V
VCC = 5 V
1.5
-
2.0
3.0
-
-
3.5
-
V
V
VinHyst Input hysteresis
0.5
V
ICSN in Pull up current at input CSN
ICLK in Pull down current at input CLK
VCSN = 3.5 V VCC = 5 V -40
-20
25
25
-8
50
50
µA
µA
µA
VCLK = 1.5 V
VDI = 1.5 V
10
10
IDI in
Pull down current at input DI
Pull down current at input
PWM1
IPWM1 in
VPWM = 1.5 V
10
-
25
10
50
15
µA
pF
Input capacitance at input
CSN, CLK, DI and PWM1/2
Cin
VCC = 0 to 5.3 V
Note:
Value of input capacity is not measured in production test. Parameter guaranteed by design.
14/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Electrical specifications
Table 14. DI timing
Symbol
Parameter
Clock period
Test condition
Min. Typ.
Max.
Unit
tCLK
tCLKH
tCLKL
VCC = 5 V
VCC = 5 V
VCC = 5 V
1000
400
-
-
-
-
-
-
ns
ns
ns
Clock high time
Clock low time
400
CSN setup time, CSN low
before rising edge of CLK
tset CSN
VCC = 5 V
VCC = 5 V
400
400
-
-
-
-
ns
ns
CLK setup time, CLK high
before rising edge of CSN
tset CLK
tset DI
DI setup time
VCC = 5 V
VCC = 5 V
200
200
-
-
-
-
ns
ns
thold time DI hold time
Rise time of input signal DI,
CLK, CSN
tr in
tf in
VCC = 5 V
VCC = 5 V
-
-
-
-
100
100
ns
ns
Fall time of input signal DI,
CLK, CSN
Note:
DI timing parameters tested in production by a passed/failed test:
Tj=-40 °C/+25 °C: SPI communication @2 MHZ.
Tj=+125 °C: SPI communication @1.25 MHZ.
Table 15. DO
Symbol
Parameter
Test condition
Min.
Typ.
Max. Unit
VDOL
VDOH
Output low level
Output high level
VCC = 5 V, ID = -2 mA
VCC = 5 V, ID = 2 mA
-
0.2
0.4
-
V
V
VCC -0.4 VCC-0.2
V
CSN = VCC
0 V < VDO < VCC
VCSN = VCC
0 V < VCC < 5.3 V
,
IDOLK
Tristate leakage current
-10
-
-
10
15
µA
pF
,
Tristate input
capacitance
(1)
CDO
10
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Doc ID 10311 Rev 10
15/39
Electrical specifications
L9950 - L9950XP
Table 16. DO timing
Symbol
Parameter
DO rise time
Test condition
Min. Typ. Max. Unit
tr DO
tf DO
CL = 100 pF, Iload = -1 mA
CL = 100 pF, Iload = 1 mA
CL = 100 pF, Iload = 1 mA
-
-
80
50
140
100
ns
ns
DO fall time
DO enable time
ten DO tri L
tdis DO L tri
ten DO tri H
tdis DO H tri
td DO
-
-
-
-
-
100 250
380 450
100 250
380 450
ns
ns
ns
ns
ns
from tristate to low level pull-up load to VCC
DO disable time CL = 100 pF, Iload = 4 mA
from low level to tristate pull-up load to VCC
DO enable time CL =100 pF, Iload = -1 mA
from tristate to high level pull-down load to GND
DO disable time CL = 100 pF, Iload = -4 mA
from high level to tristate pull-down load to GND
VDO < 0.3 VCC, VDO > 0.7 VCC
,
DO delay time
50
250
CL = 100 pF
Table 17. CSN timing
Symbol
Parameter
Test condition
Transfer of SPI command
Min. Typ. Max. Unit
Minimum CSN HI time,
switching from standby mode to Input Register
tCSN_HI,stb
-
-
20
2
50
4
µs
µs
Maximum CSN HI time,
active mode
Transfer of SPI command
to input register
tCSN_HI,min
Figure 3.
SPI - transfer timing diagram
CSN high to low: DO enabled
CSN
CLK
DI
time
0
0
1
X
18 19 20 21 22 23
0
1
2
3
4
5
6
7
X
time
DI: data will be accepted on the rising edge of CLK signal
1
0
1
1
2
3
4
5
6
7
X
X
18 19 20 21 22 23
DO: data will change on the falling edge of CLK signal
time
0
2
3
4
5
6
7
0
1
DO
X
X
18 19 20 21 22 23
time
time
CSN low to high: actual data is
transfered to output power switches
fault bit
Input
Data
Register
old data
new data
16/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Electrical specifications
Figure 4.
SPI - input timing
0.8 VCC
0.2 VCC
CSN
t
t
t
set CLK
set CSN
CLKH
0.8 VCC
0.2 VCC
CLK
t
t
t
CLKL
set DI
hold DI
0.8 VCC
0.2 VCC
DI
Valid
Valid
Figure 5.
SPI - DO valid data delay time and valid time
tf in
tr in
0.8 VCC
0.5 VCC
0.2 VCC
CLK
tr DO
DO
(low to high)
0.8 VCC
0.2 VCC
td DO
tf DO
0.8 VCC
0.2 VCC
DO
(high to low)
Doc ID 10311 Rev 10
17/39
Electrical specifications
Figure 6.
L9950 - L9950XP
SPI - DO enable and disable time
tf in
tr in
0.8 VCC
50%
CSN
0.2 VCC
DO
50%
pull-up load to VCC
C
L
= 100 pF
ten DO tri L
tdis DO L tri
DO
50%
pull-down load to GND
= 100 pF
C
L
ten DO tri H
tdis DO H tri
Figure 7.
SPI - driver turn-on/off timing, minimum csn hi time
CSN low to high: data from shift register
is transferred to output power switches
tr in
tf in
tCSN_HI,min
80%
50%
20%
CSN
tdOFF
80%
50%
20%
output current
of a driver
ON state
OFF state
tOFF
tON
tdON
80%
50%
20%
output current
of a driver
OFF state
ON state
18/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Electrical specifications
Figure 8.
SPI - timing of status bit 0 (fault condition)
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
CSN
CLK
time
time
DI
time
DI: data is not accepted
0
-
DO
time
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
Doc ID 10311 Rev 10
19/39
Application information
L9950 - L9950XP
3
Application information
3.1
Dual power supply: VS and VCC
The power supply voltage V supplies the half bridges and the highside drivers. An internal
S
charge-pump is used to drive the highside switches. The logic supply voltage V (stabilized
CC
5 V) is used for the logic part and the SPI of the device.
Due to the independent logic supply voltage the control and status information will not be
lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-
on (V increases from under voltage to V
= 4.2 V) the circuit is initialized by an
CC
POR OFF
internally generated power on reset (POR). If the voltage V decreases under the
CC
minimum threshold (V
= 3.4 V), the outputs are switched to tristate (high impedance)
POR ON
and the status registers are cleared.
3.2
3.3
Standby mode
The standby mode of the L9950 is activated by clearing the bit 23 of the Input Data
Register 0. All latched data will be cleared and the inputs and outputs are switched to high
impedance. In the standby mode the current at V (V ) is less than 6 µA (50 µA) for
CSN = high (DO in tristate). By switching the V voltage a very low quiescent current can
be achieved. If bit 23 is set, the device will be switched to active mode.
S
CC
CC
Inductive loads
Each half bridge is built by an internally connected highside and a lowside power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs OUT1 to OUT6 without external free wheeling diodes. The highside
drivers OUT7 to OUT11 are intended to drive resistive loads. Hence only a limited energy
(E<1 mJ) can be dissipated by the internal ESD diodes in freewheeling condition. For
inductive loads (L>100 µH) an external free wheeling diode connected to GND and the
corresponding output is needed.
3.4
Diagnostic functions
All diagnostic functions (over/open load, power supply over-/undervoltage, temperature
warning and thermal shutdown) are internally filtered and the condition has to be valid for at
least 32 µs (open load: 1 ms, respectively) before the corresponding status bit in the status
registers will be set. The filters are used to improve the noise immunity of the device. Open
load and temperature warning function are intended for information purpose and will not
change the state of the output drivers. On contrary, the overload and thermal shutdown
condition will disable the corresponding driver (overload) or all drivers (thermal shutdown),
respectively. Without setting the over-current recovery bits in the Input Data register, the
microcontroller has to clear the over-current status bits to reactivate the corresponding
drivers.
20/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Application information
3.5
Overvoltage and under voltage detection
If the power supply voltage V rises above the overvoltage threshold V
(typical
S
SOV OFF
21 V), the outputs OUT1 to OUT11 are switched to high impedance state to protect the load.
When the voltage V drops below the under voltage threshold V (UV switch OFF
S
SUV OFF
voltage), the output stages are switched to the high impedance to avoid the operation of the
power devices without sufficient gate driving voltage (increased power dissipation). If the
supply voltage V recovers to normal operating voltage the outputs stages return to the
S
programmed state (input register 0: bit 20=0).
If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the
drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the
drivers. It is recommended to set bit 20 to avoid a possible high current oscillation in case of
a shorted output to GND and low battery voltage.
3.6
Temperature warning and thermal shutdown
If junction temperature rises above T
a temperature warning flag is set and is detectable
j TW
via the SPI. If junction temperature increases above the second threshold T , the thermal
j SD
shutdown bit will be set and power DMOS transistors of all output stages are switched off to
protect the device. In order to reactivate the output stages the junction temperature must
decrease below T
microcontroller.
- T
and the thermal shutdown bit has to be cleared by the
j SD
j SD HYS
3.7
3.8
Open-load detection
The open load detection monitors the load current in each activated output stage. If the load
current is below the open load detection threshold for at least 1 ms (t ) the corresponding
open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3ms) can be used to test the open load status without
changing the mechanical/electrical state of the loads.
dOL
Over load detection
In case of an over-current condition a flag is set in the status register in the same way as
open load detection. If the over-current signal is valid for at least t
= 32 µs, the over-
ISC
current flag is set and the corresponding driver is switched off to reduce the power
dissipation and to protect the integrated circuit. If the over-current recovery bit of the output
is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
Doc ID 10311 Rev 10
21/39
Application information
L9950 - L9950XP
3.9
Current monitor
The current monitor output sources a current image at the current monitor output which has
a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. The bits
18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4, OUT5,
OUT6 and OUT11 will be multiplexed to the current monitor output. The current monitor
output allows a more precise analysis of the actual state of the load rather than the detection
of an open or overload condition. For example this can be used to detect the motor state
(starting, free running, stalled). Moreover, it is possible to regulate the power of the defroster
more precise by measuring the load current. The current monitor output is bidirectional (c.f.
PWM inputs).
3.10
3.11
PWM inputs
Each driver has a corresponding PWM enable bit which can be programmed by the SPI
interface. If the PWM enable bit is set, the output is controlled by the logically AND
combination of the PWM signal and the output control bit in Input Data Register. The outputs
OUT1-OUT8 and OUT11 are controlled by the PWM1 input and the outputs OUT9/10 are
controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be
used to dim two lamps independently by external PWM signals.
Cross current protection
The six half brides of the device are cross current protected by an internal delay time. If one
driver (LS or HS) is turned off the activation of the other driver of the same half bridge will be
automatically delayed by the cross current protection time. After the cross current protection
time is expired the slew rate limited switch off phase of the driver will be changed to a fast
turn-off phase and the opposite driver is turned on with slew rate limitation. Due to this
behavior it is always guaranteed that the previously activated driver is totally turned off
before the opposite driver will start to conduct.
3.12
Programmable soft start function to drive loads with higher
inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps,
start current of motors and cold resistance of heaters) can be driven by using the
programmable soft start function (i.e. overcurrent recovery mode). Each driver has a
corresponding over-current recovery bit. If this bit is set, the device will automatically switch-
on the outputs again after a programmable recovery time. The duty cycle in over-current
condition can be programmed by the SPI interface to be about 12% or 25%. The PWM
modulated current will provide sufficient average current to power up the load (e.g. heat up
the bulb) until the load reaches operating condition.
The device itself cannot distinguish between a real overload and a non linear load like a light
bulb. A real overload condition can only be qualified by time. As an example the
microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first
50ms. After clearing the recovery bit the output will be automatically disabled if the overload
condition still exits.
22/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Application information
Figure 9.
Example of programmable soft start function for inductive loads
Doc ID 10311 Rev 10
23/39
Functional description of the SPI
L9950 - L9950XP
4
Functional description of the SPI
4.1
Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be
driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and
CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible
output pins and one input pin will be needed to communicate with the device. A fault
condition can be detected by setting CSN to low. If CSN = 0, the DO pin will reflect the
status bit 0 (fault condition) of the device which is a logical or of all bits in the status registers
0 and 1. The microcontroller can poll the status of the device without the need of a full SPI
communication cycle.
Note:
In contrast to the SPI standard the least significant bit (LSB) will be transferred first
(see Figure 3).
4.2
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started. The state when CSN is going low until the rising
edge of CSN will be called a communication frame. If the CSN input pin is driven above
7.5V, the L9950 will go into a test mode. In the test mode the DO will go from tri state to
active mode.
4.3
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register. The writing to the selected Data Input Register is only enabled if exactly
24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame will be ignored. This safety function
is implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
24/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Functional description of the SPI
4.4
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
4.5
4.6
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
Input data register
The device has two input registers. The first bit (bit 0) at the DI input is used to select one of
the two Input Registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register will be written to the selected Input Data
Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents
of the selected status register will be transferred to DO during the current communication
frame. Bit 1-17 controls the behavior of the corresponding driver.
If bit 23 is zero, the device will go into the standby mode. The bits 18 and 19 are used to
control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status
registers. The bits in the status registers will be cleared after the current communication
frame (rising edge of CSN).
4.7
Status register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is
used as a fault bit and is a logical NOR combination of bits 1-22 in both status registers. The
state of this bit can be polled by the microcontroller without the need of a full SPI
communication cycle. If one of the over-current bits is set, the corresponding driver will be
disabled. If the over-current recovery bit of the output is not set the microcontroller has to
clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers
will go into a high impedance state. Again the microcontroller has to clear the bit to enable
the drivers.
Doc ID 10311 Rev 10
25/39
Functional description of the SPI
L9950 - L9950XP
4.8
Test mode
The test mode can be entered by rising the CSN input to a voltage higher than 7.0 V. In the
test mode the inputs CLK, DI, PWM1/2 and the internal 2 MHz CLK can be multiplexed to
data output DO for testing purpose. Furthermore the over-current thresholds are reduced by
a factor of 4 to allow EWS testing at lower current. For EWS testing a special test pad is
available to measure the internal bandgap voltage, the TW and TSD thresholds.
The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can
be switched on at the same time. In the test mode this combination is used to multiplex the
desired signals according to following table:
Table 18. Test mode
LS1 HS1 LS2 HS2 LS3 HS3
DO
LS3 HS3 LS4 HS4 LS5 HS5
Test pad
! (both HI) ! (both HI) ! (both HI) No error
! (both HI) ! (both HI) ! (both HI)
5µA Iref
Tsens1
Tsens2
Tsens3
Tsens4
Tsens5
Tsens6
Vbandgap
both HI
! (both HI)
both HI
! (both HI) ! (both HI)
DI
both HI
! (both HI)
both HI
! (both HI) ! (both HI)
both HI
both HI
! (both HI)
CLK
both HI
both HI
! (both HI)
! (both HI)
both HI
! (both HI) INT_CLK
! (both HI) ! (both HI)
both HI ! (both HI)
both HI
both HI
PWM1
PWM2
! (both HI) ! (both HI)
both HI
! (both HI)
both HI
! (both HI)
both HI
both HI
both HI
both HI
both HI
26/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Functional description of the SPI
Status register 0 (read)
Table 19. SPI - input data and status registers 0
Input register 0 (write)
Bit
Name
Comment
Name
Comment
If Enable Bit is set the
device will be switched in
active mode. If Enable Bit
is cleared device go into
standby mode and all bits
are cleared. After power-
on reset device starts in
standby mode.
A broken VCC or SPI
connection of the L9950 can
be detected by the
microcontroller, because all 24
bits low or high is not a valid
frame.
23
Enable bit
Reset bit
Always 1
If Reset Bit is set both
status registers will be
cleared after rising edge
of CSN input.
In case of an overvoltage or
undervoltage event the
22
21
VS overvoltage
VS undervoltage
corresponding bit is set and
the outputs are deactivated. If
VS voltage recovers to normal
operating conditions outputs
are reactivated automatically
(if Bit 20 of status register 0 is
not set).
OC recovery
duty cycle
This bit defines in
combination with the over-
current recovery bit (Input
Register 1) the duty cycle
in over-current condition
of an activated driver.
1:
0: 12%
25%
In case of an thermal
shutdown all outputs are
switched off.
If this bit is set the
microcontroller has to
Overvoltage/Un clear the status register
dervoltage after
recovery disable undervoltage/overvoltage
event to enable the
Thermal
shutdown
20
19
The microcontroller has to
clear the TSD bit by setting the
Reset Bit to reactivate the
outputs.
outputs.
Depending on
This bit is for information
purpose only. It can be used
for a thermal management by
the microcontroller to avoid a
thermal shutdown.
combination of bit 18 and
19 the current image
(1/10.000) of the selected
HS output will be multi-
plexed to the CM output:
Temperature
warning
Bit
19
Bit
18
Output
OUT11
After switching the device from
standby mode to active mode
an internal timer is started to
allow charge pump to settle
before the outputs can be
activated. This bit is cleared
automatically after start up
time has finished. Since this
bit is controlled by internal
clock it can be used for
0
1
0
0
OUT1/OUT
6
Current monitor
select bits
0
1
1
1
OUT5
OUT4
18
Not ready bit
HS driver of OUT1 is only
selected if HS driver
OUT1 is switched on and
HS driver OUT6 is not
activated.
synchronizing testing events
(e.g. measuring filter times).
Doc ID 10311 Rev 10
27/39
Functional description of the SPI
L9950 - L9950XP
Table 19. SPI - input data and status registers 0 (continued)
Input register 0 (write) Status register 0 (read)
Bit
Name
Comment
Name
Comment
OUT11 – HS
on/off
OUT11 – HS
over-current
17
16
15
14
13
12
11
10
9
OUT10 – HS
on/off
OUT10 – HS
over-current
OUT9 – HS
on/off
OUT9 – HS
over-current
OUT8 – HS
on/off
OUT8 – HS
over-current
OUT7 – HS
on/off
OUT7 – HS
over-current
If a bit is set the selected
output driver is switched
on. If the corresponding
PWM enable bit is set
(Input Register 1) the
driver is only activated if
PWM1 (PWM2) input
signal is high. The outputs
of OUT1-OUT6 are half
bridges. If the bits of HS-
and LS driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
avoid a high internal
OUT6 – HS
on/off
OUT6 – HS
over-current
In case of an over-current
event the corresponding
status bit is set and the output
driver is disabled. If the over-
current Recovery Enable bit is
set (Input Register 1) the
output will be automatically
reactivated after a delay time
resulting in a PWM modulated
current with a programmable
duty cycle (Bit 21).
OUT6 – LS
on/off
OUT6 – LS
over-current
OUT5 – HS
on/off
OUT5 – HS
over-current
OUT5 – LS
on/off
OUT5 – LS
over-current
OUT4 – HS
on/off
OUT4 – HS
over-current
8
If the over-current recovery bit
is not set the microcontroller
has to clear the over-current
bit (Reset Bit) to reactivate the
output driver.
OUT4 – LS
on/off
OUT4 – LS
over-current
7
current from VS to GND.
In test mode (CSN>7.5 V)
this bit combinations are
used to multiplex internal
signals to the DO output.
OUT3 – HS
on/off
OUT3 – HS
over-current
6
OUT3 – LS
on/off
OUT3 – LS
over-current
5
OUT2 – HS
on/off
OUT2 – HS
over-current
4
OUT2 – LS
on/off
OUT2 – LS
over-current
3
OUT1 – HS
on/off
OUT1 – HS
over-current
2
OUT1 – LS
on/off
OUT1 – LS
over-current
1
A logical NOR combination of
all bits 1 to 22 in both status
registers.
0
0
No error bit
28/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Functional description of the SPI
Status register 1 (read)
Table 20. SPI - input data and status registers 1
Input register 1 (write)
Bit
Name
Comment
Name
Comment
If Enable bit is set the device
will be switched in active mode.
If Enable Bit is cleared device
go into standby mode and all
bits are cleared. After power-
on reset device starts in
standby mode.
A broken VCC or SPI
connection of the L9950
can be detected by the
microcontroller, because
all 24 bits low or high is
not a valid frame.
23
Enable bit
Always 1
OUT11 OC
Recovery
Enable
In case of an overvoltage
or undervoltage event
the corresponding bit is
set and the outputs are
deactivated. If VS
voltage recovers to
normal operating
conditions outputs are
reactivated automatically.
22
21
VS overvoltage
VS undervoltage
OUT10 OC
Recovery
Enable
In case of an thermal
shutdown all outputs are
switched off. The
In case of an over-current
OUT9 OC
Recovery
Enable
event the over-current status
bit (Status Register 0) is set
and the output is switched off.
If the over-current Recovery
Enable bit is set the output will
be automatically reactivated
after a delay time resulting in a
PWM modulated current with a
programmable duty cycle (Bit
21 of Input Data Register 0).
Depending on occurrence of
Overcurrent Event and internal
clock phase it is possible that
one recovery cycle is executed
even if this bit is set to zero.
20
19
Thermal shutdown microcontroller has to
clear the TSD bit by
setting the Reset Bit to
reactivate the outputs.
This bit is for information
purpose only. It can be
used for a thermal
management by the
microcontroller to avoid a
thermal shutdown.
OUT8 OC
Recovery
Enable
Temperature
warning
After switching the
device from standby
mode to active mode an
internal timer is started
to allow charge pump to
settle before the outputs
can be activated. This bit
is cleared automatically
after start up time has
finished. Since this bit is
controlled by internal
clock it can be used for
synchronizing testing
OUT7 OC
Recovery
enable
18
Not ready bit
events(e.g. measuring
filter times).
Doc ID 10311 Rev 10
29/39
Functional description of the SPI
L9950 - L9950XP
Table 20. SPI - input data and status registers 1 (continued)
Input register 1 (write)
Status register 1 (read)
Bit
17
16
15
14
13
12
Name
Comment
Name
Comment
OUT6 OC
Recovery
Enable
OUT11 – HS
open load
The open load detection
monitors the load current
in each activated output
stage. If the load current
is below the open load
detection threshold for at
least 1 ms (tdOL) the
corresponding open load
bit is set. Due to
OUT5 OC
Recovery
Enable
OUT10 – HS
open load
OUT4 OC
Recovery
Enable
OUT9 – HS
open load
After 50 ms the bit can be
cleared. If over-current
condition still exists, a wrong
load can be assumed.
mechanical/electrical
inertia of typical loads a
short activation of the
outputs (e.g. 3 ms) can
be used to test the open
load status without
OUT3 OC
Recovery
Enable
OUT8 – HS
open load
OUT2 OC
Recovery
Enable
OUT7 – HS
open load
changing the
OUT1 OC
Recovery
Enable
mechanical/electrical
state of the loads.
OUT6 – HS
open load
OUT6 – LS
open load
OUT11 PWM1
Enable
11
10
9
OUT5 – HS
open load
OUT10 PWM2
Enable
The open load detection
monitors the load current
in each activated output
stage. If the load current
is below the open load
detection threshold for at
least 1 ms (tdOL) the
corresponding open load
bit is set. Due to
mechanical/electrical
inertia of typical loads a
short activation of the
outputs (e.g. 3 ms) can
be used to test the open
load status without
OUT5 – LS
open load
OUT9 PWM2
Enable
OUT4 – HS
open load
OUT8 PWM1
Enable
8
If the PWM1/2 Enable Bit is set
and the output is enabled
(Input Register 0) the output is
switched on if PWM1/2 input is
high and switched off if
PWM1/2 input is low. OUT9
and OUT10 is controlled by
PWM2 input all other outputs
are controlled by PWM1 input.
OUT4 – LS
open load
OUT7 PWM1
Enable
7
OUT3 – HS
open load
OUT6 PWM1
Enable
6
OUT3 – LS
open load
OUT4 PWM1
Enable
5
OUT2 –HS
open load
OUT4 PWM1
Enable
4
changing the
mechanical/electrical
state of the loads.
OUT2– LS
open load
OUT3 PWM1
Enable
3
OUT1 – HS
open load
OUT4 PWM1
Enable
2
OUT1 – LS
open load
OUT4 PWM1
Enable
1
A logical NOR
combination of all bits 1
to 22 in both status
registers.
0
1
No Error bit
30/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Packages thermal data
5
Packages thermal data
Figure 10. Packages thermal data
Doc ID 10311 Rev 10
31/39
Package and packing information
L9950 - L9950XP
6
Package and packing information
6.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
6.2
PowerSO-36 package information
Figure 11. PowerSO-36 package dimensions
32/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Package and packing information
Table 21. PowerSO-36 mechanical data
Millimeters
Typ.
Symbol
Min.
Max.
3.60
0.30
3.30
0.10
0.38
0.32
16.00
9.80
14.5
11.10
2.90
6.20
-
A
a1
a2
a3
b
-
-
0.10
-
-
-
0
-
0.22
-
c
0.23
-
D *
D1
E
15.80
-
9.40
-
13.90
-
E1 *
E2
E3
e
10.90
-
-
-
5.80
-
-
0.65
e3
G
-
11.05
-
0
-
-
-
-
-
-
-
-
0.10
15.90
1.10
1.10
-
H
15.50
h
-
L
0.8
M
-
-
-
-
N
10 deg
-
R
s
8 deg
Doc ID 10311 Rev 10
33/39
Package and packing information
L9950 - L9950XP
6.3
PowerSSO-36 package information
Figure 12. PowerSSO-36 package dimensions
Table 22. PowerSSO-36 mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
2.45
2.35
0.10
0.36
0.32
10.50
7.6
A
A2
a1
b
2.15
-
2.15
-
0
-
0.18
-
c
0.23
-
D(1)
10.10
-
E
7.4
-
e
-
0.5
-
e3
F
-
8.5
-
-
2.3
-
G
-
-
-
-
-
-
-
0.1
G1
H
0.06
10.5
0.4
10.1
-
h
k
0°
8°
34/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Package and packing information
Table 22. PowerSSO-36 mechanical data (continued)
Millimeters
Symbol
Min.
Typ.
-
Max.
L
M
N
O
Q
S
T
0.55
0.85
-
4.3
-
-
-
10°
-
1.2
0.8
2.9
3.65
1
-
-
-
-
-
-
-
U
X
Y
-
-
4.3
6.9
-
5.2
7.5
-
1. “D” and “E” do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.15 mm
per side (0.006”).
6.4
PowerSO-36 packing information
Figure 13. PowerSO-36 tube shipment (no suffix)
Doc ID 10311 Rev 10
35/39
Package and packing information
L9950 - L9950XP
Figure 14. PowerSO-36 tape and reel shipment (suffix “TR”)
TAPE DIMENSIONS
REEL DIMENSIONS
A0
B0
K0
K1
F
15.20 0.1
Base qty
Bulk qty
A (max)
B (min)
C (±0.2)
D (min)
G (+2 / -0)
N (min)
T (max)
600
600
330
1.5
16.60 0.1
3.90 0.1
3.50 0.1
11.50 0.1
24.00 0.1
24.00 0.3
13
P1
W
20.2
24.4
60
All dimensions are in mm.
30.4
36/39
Doc ID 10311 Rev 10
L9950 - L9950XP
Package and packing information
6.5
PowerSSO-36 packing information
Figure 15. PowerSSO-36 tube shipment (no suffix)
Base qty
49
Bulk qty
1225
C
Tube length (±0.5)
532
3.5
B
A
B
13.8
0.6
C (±0.1)
All dimensions are in mm.
A
Figure 16. PowerSSO-36 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base qty
Bulk qty
A (max)
B (min)
C (±0.2)
F
1000
1000
330
1.5
13
20.2
24.4
100
30.4
G (+2 / -0)
N (min)
T (max)
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape hole spacing
Component spacing
Hole diameter
P0 (±0.1)
P
12
D (±0.05)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
1.55
1.5
11.5
2.85
2
Hole diameter
Hole position
Compartment depth
Hole spacing
End
All dimensions are in mm.
Start
No components
500mm min
Top
cover
tape
No components Components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Doc ID 10311 Rev 10
37/39
Revision history
L9950 - L9950XP
7
Revision history
Table 23. Document revision history
Date
Revision
Description of changes
Apr-2004
1
First Issue
Changed maturity from product preview to final;
Jun-2004
2
Changed values in the Table 4: ESD protection
Jul-2004
Jun-2005
Jul-2005
3
4
5
Minor changes
PowerSSO-36 package insertion
Figure 1 modification
Features modification;
Table 7 modification (ICC; IS + ICC);
Figure 10 modification;
IQLL modification.
Sep-2005
6
Document restructured and reformatted.
14-Nov-2007
7
Added PowerSO-36 packing information and PowerSSO-36 packing
information.
05-Nov-2008
30-Mar-2009
8
9
Updated Table 22: PowerSSO-36 mechanical data.
Changed Section : Application on cover page
Changed Section 6.1: ECOPACK®
Table 22: PowerSSO-36 mechanical data:
– Changed A (max) value from 2.50 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed L (max) value from 0.90 to 0.85
09-Jun-2009
10
38/39
Doc ID 10311 Rev 10
L9950 - L9950XP
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39/39
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