L9903 [STMICROELECTRONICS]
MOTOR BRIDGE CONTROLLER; 汽车桥控制器
| 型号： | L9903 |
| 厂家： | 
ST |
| 描述： | MOTOR BRIDGE CONTROLLER |
| 文件： | 总17页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L9903
MOTOR BRIDGE CONTROLLER
PRODUCT PREVIEW
■
■
OPERATING SUPPLY VOLTAGE 8V TO 20V,
OVERVOLTAGE MAX. 40V
OPERATING SUPPLY VOLTAGE 6V WITH
IMPLEMENTED STEPUP CONVERTER
■ QUIESCENT CURRENT IN STANDBY MODE
LESS THAN 50µA
■
ISO 9141 COMPATIBLE INTERFACE
■
CHARGE PUMP FOR DRIVING A POWER
MOS AS REVERSE BATTERY PROTECTION
SO20
■ PWM OPERATION FREQUENCY UP TO
ORDERING NUMBER: L9903
30KHZ
■ PROGRAMMABLE CROSS CONDUCTION
PROTECTION TIME
■
OVERVOLTAGE, UNDERVOLTAGE, SHORT
CIRCUIT AND THERMAL PROTECTION
DESCRIPTION
Control circuit for power MOS bridge driver in auto-
motive applications with ISO 9141bus interface.
■
REAL TIME DIAGNOSTIC
BLOCK DIAGRAM
10
VS
R
CP
Ref er ence
VCC
-
+
1
BIAS
ST
11
CP
Charge
pump
=
V
STH
13
12
CB1
GH1
f
ST
VCC
Overvoltage
14
Undervoltage
S1
R
DG
2
Thermal shutdown
DG
R
S1
=
V
S1TH
19
GL1
4
EN
R
R
EN
GL1
18
GL2
S2
5
DIR
R
GL2
R
DIR
VCC
17
R
PWM
3
PWM
R
S2
=
V
S2TH
6
PR
15
16
GH2
CB2
Timer
ISO-Interface
9
K
7
8
RX
TX
R
R
RX
VCC
=
0.5 • V
VS
TX
I
KH
20
GND
June 2000
1/17
This is preliminary information on a new product now in development. Details are subject to change without notice.
L9903
PIN FUNCTION
N°
1
Pin
ST
Description
Open Drain Switch for Stepup converter
Open drain diagnostic output
PWM input for H-bridge control
Enable input
2
DG
PWM
EN
3
4
5
DIR
PR
Direction select input for H-bridge control
6
Programmable cross conduction protection time
ISO 9141 interface, receiver output
7
RX
8
TX
ISO 9141 interface, transmitter input
9
K
ISO 9141 Interface, bidirectional communication K-line
Supply voltage
10
11
12
13
14
15
16
17
18
19
20
VS
CP
Charge pump for driving a power MOS as reverse battery protection
Gate driver for power MOS highside switch in halfbridge 1
External bootstrap capacitor
GH1
CB1
S1
Source/drain of halfbridge 1
GH2
CB2
S2
Gate driver for power MOS highside switch in halfbridge 2
External bootstrap capacitor
Source/drain of halfbridge 2
GL2
GL1
GND
Gate driver for power MOS lowside switch in halfbridge 2
Gate driver for power MOS lowside switch in halfbridge 1
Ground
PIN CONNECTION (Top view)
ST
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
GL1
GL2
S2
DG
PWM
EN
DIR
PR
RX
TX
CB2
GH2
S1
CB1
GH1
CP
K
VS
SO20
2/17
L9903
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
-0.3 to 40
-100
Unit
V
V
I
, V
Bootstrap voltage
Bootstrap current
CB1
CB2
, I
mA
V
CB1 CB2
V
Charge pump voltage
Charge pump current
Logic input voltage
-0.3 to 40
-1
CP
CP
I
mA
V
V
,V
-0.3 to 7
DIR
EN
,V
,V
PWM TX
I
,I
Logic input current
±1
mA
DIR EN
,I
,I
PWM TX
V
I
,V
Logic output voltage
Logic output current
Gate driver voltage
Gate driver current
Gate driver voltage
Gate driver current
K-line voltage
-0.3 to 7
-1
V
mA
V
DG RX
,I
DG RX
V
, V
-0.3 to V + 10
GH1 GH2
SX
I
, I
-1
-0.3 to 10
-10
mA
V
GH1 GH2
V
GL1
, V
GL2
GL2
I
, I
mA
V
GL1
V
-20 to V
S
K
PR
PR
V
Programming input voltage
Programming input current
Source/drain voltage
Source/drain current
Output voltage
-0.3 to 7
-1
V
I
mA
V
V
I
, V
-2 to V + 2
S1
S2
VS
, I
S1 S2
-10
-0.3 to 40
-1
mA
V
V
ST
I
Step up output current
DC supply voltage
mA
V
ST
V
-0.3 to 27
40
VSDC
V
Pulse supply voltage (T £ 500ms)
DC supply current
V
VSP
I
-10
mA
VS
For externally applied voltages or currents exceeding these limits damage of the device may occur!
All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body
model with R=1.5kΩ, C=100pF and discharge voltage ±2kV, corresponding to a maximum discharge energy of
0.2mJ.
3/17
L9903
THERMAL DATA
Symbol
Parameter
Value
-40 to 150
min 150
typ 15
Unit
°C
T
Operating junction temperature
J
T
Junction temperature thermal shutdown threshold
Junction thermal shutdown hysteresis
°C
JSD
T
°C
JSDH
1)
R
85
°C/W
th j-amb
Thermal resistance junction to ambient
1. see application note 110 for SO packages.
ELECTRICAL CHARACTERISTCS (8V < V < 20V, V =HIGH, -40°C ≤ T ≤ 150°C, unless otherwise spec-
VS
EN
J
ified. The voltages are refered to GND and currents are assumed positive, when current flows into the pin.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Supply (VS)
V
Overvoltage disable HIGH
threshold
20
22
24
V
VS OVH
2)
V
1.6
V
V
VS OVh
Overvoltage threshold hysteresis
V
Undervoltage disable HIGH
threshold
6
7
VS UVH
V
Undervoltage threshold
0.66
V
VS UVh
2)
hysteresis
I
Supply current
Supply current
V
= 0 ; V = 13.5V; T < 85°C
50
20
µA
VSL
EN
VS
J
I
V
V
= 13.5V; V = HIGH;
mA
VSH
VS
EN
= LOW;
DIR
f
= 20kHz; C
= 0.1µF;
PWM
CBX
C
R
= 4.7nF; C
= 4.7nF;
GLX
GHX
= 10kΩ; C = 150pF
PR
PR
Enable input (EN)
V
Low level
High level
1.5
V
V
V
ENL
V
3.5
16
ENH
2)
V
1
ENh
Hysteresis threshold
R
Input pull down resistance
V
= 5V
EN
50
100
1.5
kΩ
EN
H-bridge control inputs (DIR, PWM)
V
Input low level
Input high level
V
V
DIRL
V
PWML
V
3.5
16
DIRH
V
PWMH
2)
V
1
V
DIRh
Input threshold hysteresis
Internal pull up resistance
V
PWMh
R
V
= 0; V = 0
PWM
50
100
kΩ
DIR
DIR
3)
R
PWM
to internal VCC
4/17
L9903
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
DIAGNOSTIC output (DG)
V
R
Output drop
I
= 1mA
DG
0.6
40
V
DG
DG
Internal pull up resistance
V
= 0V
10
20
2
kΩ
DG
3)
to internal VCC
4)
Programmable cross conduction protection
N
Threshold voltage ratio V
/
1.8
2.2
PR
PRH
R
= 10kΩ
PR
V
PRL
I
Current capability
-0.5
mA
PR
V
= 2V
PR
ISO interface, transmission input (TX)
V
Input low level
1.5
40
V
V
TXL
V
Input high level
3.5
10
TXH
V
Input hysteresis voltage 2)
1
V
TXh
R
Internal pull up resistance to
internal VCC 3)
V
= 0
20
kΩ
TX
TX
ISO interface, receiver output (RX)
V
Output voltage high stage
4.5
5
5.5
20
V
RXL
TX = HIGH; I = 0; V = V
VS
RX
K
R
Internal pull up resistance
TX = HIGH;
= 0V
10
40
k
Ω
RX
3)
V
RX
to internal VCC
R
ON resistance to ground
TX = LOW;
= 1mA
90
W
RXON
I
RX
t
Output high delay time
Output low delay time
Fig. 1
0.5
0.5
µs
µs
RXH
t
RXL
ISO interface, K-line (K)
V
Input low level
-20V
0.45 ·
KL
V
VS
V
Input high level
0.55 ·
VVS
V
KH
VS
V
Input hysteresis voltage 2)
0.025·
0.8V
Kh
V
VS
I
Input current
V
= HIGH
-5
25
30
µA
W
KH
TX
TX
TX
R
ON resistance to ground
Short circuit current
Transmission frequency
V
V
= LOW; I =10mA
10
KON
KSC
K
I
= LOW
40
60
130
mA
kHz
f
100
K
2. not tested in production: guaranteed by design and verified in characterization
3. Internal V is 4.5V ... 5.5V
VCC
4. see page 18 for calculation of programmable cross conduction protection time
5/17
L9903
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
Parameter
Test Condition
= 13.5V; Fig. 1
VS
Min.
Typ.
Max.
Unit
t
Rise time
V
2
6
µs
Kr
External loads at K-line:
R = 510Ω pull up
K
to V
VS
C = 2.2nF to GND
K
t
Fall time
2
4
4
6
µs
µs
µs
µs
Kf
t
Switch high delay time
Switch low delay time
Short circuit detection time
17
17
40
KH
t
KL
t
V
= 13.5V;
VS
10
SH
TX = LOW
V
> 0.55 · V
K
VS
Charge pump
V
Charge pump voltage
V
V
V
= 8V
V
7V
V
10V
+
V
14V
V
14V
+
VS
CP
VS
VS
VS
VS
= 13.5V
= 20V
+
VS
+
VS
V
+
VS
V
VS
10V
+14V
I
t
Charging current
V
= 13.5V
-50
-75
1.2
µA
CP
CP
VS
V
= V + 8V
CP VS
2)
V
C
= 13.5V
= 10nF
4
ms
VS
Charging time
= V + 8V
CP
V
CP
VS
f
Charge pump frequency
V
= 13.5V
250
500
750
kHz
CP
VS
Drivers for external highside power MOS
V
V
Bootstrap voltage
V
V
V
= 8V; I
=13.5V; I
= 20V; I
= 0; V = 0
7.5
10
10
14
14
14
V
V
V
CB1
CB2
VS
VS
VS
CBX
SX
= 0; V = 0
SX
CBX
= 0; V = 0
SX
CBX
R
R
ON-resistance of SINK stage
10
W
GH1L
GH2L
V
= 8V; V = 0
SX
CBX
I
= 50mA; T = 25°C
J
GHX
20
W
V
= 8V; V = 0
SX
CBX
I
= 50mA; T = 125°C
J
GHX
R
R
ON-resistance of SOURCE stage
Gate ON voltage (SOURCE)
I
I
= -50mA; T = 25°C
10
20
W
W
GH1H
GH2H
GHX
GHX
J
= -50mA; T = 125°C
J
V
V
V
C
= V = 8V; I
= 0;
V
+6.5V
V
VS
+14V
GH1H
GH2H
VS
SX
GHX
VS
= 0.1µF
CBX
V
C
= V = 13.5V; I
= 0;
V
10V
+
V
VS
+14V
VS
SX
GHX
VS
= 0.1µF
CBX
V
C
= V = 20V; I
= 0;
V
+10V
V
VS
+14V
VS
SX
GHX
VS
= 0.1µF
CBX
6/17
L9903
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
Parameter
Test Condition
EN = LOW
Min.
Typ.
Max.
Unit
R
R
Gate discharge resistance
10
100
kΩ
GH1
GH2
R
R
Sink resistance
10
100
kΩ
S1
S2
Drivers for external lowside power MOS
R
R
ON-resistance of SINK stage
ON-resistance of SOURCE stage
Gate ON voltage (SOURCE)
I
I
= 50mA; T = 25°C
10
20
W
W
GL1L
GL2L
GLX
GLX
J
= 50mA; T = 125°C
J
R
I
I
= -50mA; T = 25°C
10
20
W
W
GL1H,
GLX
GLX
J
R
= -50mA; T = 125°C
J
GL2H
V
V
V
V
= 8V; I
= 0
7V
10V
10V
V
V
GL1H,
VS
VS
VS
GLX
VS
VS
V
GL2H
= 13.5V; I
= 0
GLX
= 20V;I
= 0
14V
GLX
R
GL1
Gate discharge resistance
EN = LOW
10
100
kΩ
R
GL2
2. not tested in production: guaranteed by design and verified in characterization
Timing of the drivers
t
t
Propagation delay time
Fig. 2
500
ns
GH1LH
GH2LH
V
V
C
= 13.5V
= V =0
VS
S1
S2
= 0.1µF
CBX
RPR= 10kW
Propagation delay time including Fig. 2
t
t
0.7
1
1.3
µs
GH1LH
GH2LH
cross conduction protection time
V
V
C
= 13.5V
VS
t
= V =0
CCP
S1
S2
= 0.1µF
CBX
t
t
Propagation delay time
500
ns
GH1HL
GH2HL
C
R
= 150pF;
PR
= 10kΩ;
PR
5)
t
Propagation delay time
Fig. 2
500
ns
GL1LH
V
V
C
= 13.5V
t
VS
GL2LH
= V =0
S1
S2
= 0.1µF
CBX
R
= 10kΩ
PR
t
Propagation delay time including Fig. 2
0.7
1
1.3
µs
GL1LH
cross conduction protection time
V
V
C
= 13.5V
t
VS
GL2LH
t
= V =0
CCP
S1
S2
= 0.1µF
CBX
t
Propagation delay time
500
ns
GL1HL
t
GL2HL
C
R
= 150pF;
PR
= 10kΩ;
PR
5)
7/17
L9903
ELECTRICAL CHARACTERISTICS
(continued)
Fig. 2
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
t
Rise time
Fall time
Rise time
Fall time
1
µs
GH1r
V
V
C
= 13.5V
= V =0
t
VS
GH2r
S1
S2
= 0.1µF
t
t
1
1
1
µs
µs
µs
GH1f
GH2f
CBX
C
C
R
= 4.7nF
= 4.7nF
GHX
GLX
t
t
GL1r
GL2r
= 10kΩ;
PR
t
GL1f
t
GL2f
Short Circuit Detection
V
V
Threshold voltage
4
V
S1TH
S2TH
t
Detection time
5
1
10
15
µs
SCd
Step up converter (ST)
(5.2V
V
< 10V)
VS
≤
V
ST disable HIGH threshold
10
2
V
V
STH
V
ST disable threshold hysteresis
STh
2)
voltage
R
Open drain ON resistance
20
Ω
DSON
V
= 5.2V;
VS
I
= 50mA
ST
f
Clock frequency
50
100
149
kHz
ST
2. not tested in production: guaranteed by design and verified in characterization
5. tested with differed values in production but guaranteed by design and verified in characterization
8/17
L9903
Figure 1. Timing of the ISO-interface
V
TX
0.7
• V
V C C
0.3
•
V
0.3 • V
VC C
V C C
t
t
t
t
t
KH
KL
V
K
t
t
Kr
K f
80%
I
>
I
KSC
K
0.55
0.45
• V
V S
•
V
V S
20%
t
t
RXH
RXL
V
RX
0.7
• V
V C C
0.3
• V
VC C
open dr ai n
tr ansis tor at
K -pin
t
SH
ON
OFF
Figure 2. Timing of the drivers for the external MOS regarding the inputs DIR and PWM
PW M
or
t
D IR
t
t
GH XHL
GH XLH
t
t
GH Xf
G HXr
80%
20%
GHX
t
t
t
GLXH L
GLXLH
80%
20%
GLX
t
t
t
G LXr
GLXf
9/17
L9903
Figure 3. I(V) characteristics of the K-Line for TX = HIGH and VVS=13.5V
IK [mA]
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-20
-10
0
10
20
VK [V]
Figure 4. Driving sequence
EN
DIR
PW M
braking
GH1
GL1
GH2
GL2
Note:
Before standby mode
(EN = low) a braking phase
is mandatory to discharge
the stored energy of the
motor.
10/17
L9903
Figure 5. Charging time of an external capacitor of 10nF connected to CP pin at V =8V and
VS
V
=13.5V
VS
voltage [V]
30
Charging time of a 10nF load at CP
CP for VS=13.5V
25
20
15
10
5
CP for VS=8V
EN
0
0
1
2
3
4
time [ms]
Figure 6. Application Circuit Diagram
V
BAT
D1
Gate
Protection
VS
10
1
R
C P
R
C
C
1
S2
ST
S1
Voltage
Reference
BIAS
VC C
-
+
Regu la tor
11
C P
C harge
pu mp
V
=
STH
13
12
CB1
GH1
R
f
C1
ST
V
CC
C
B1
VC C
O v erv oltage
Un de rvoltage
14
S1
R
DG
DG
EN
2
4
T he rmal s hu tdown
M
R
S
1
V
=
S1T H
R
R
19
G L1
R
R
G L
E
N
1
18
G L2
S2
DIR
5
R
G L
2
R
D IR
VC C
µC
17
R
PW
M
PWM
PR
3
6
R
S
2
V
=
C
S2T H
B2
R
15
16
GH2
CB2
Tim
e r
C
R
PR
PR
ISO- Interf ac e
9
K
RX
TX
7
8
K-Line
R
R
R X
V
0.5
• V
V S
=
C C
T X
I
KH
20
GND
G ND
11/17
L9903
FUNCTIONAL DESCRIPTION
General
The L9903 integrated circuit (IC) is designed to control four external N-channel MOS transistors in H-Bridge con-
figuration for DC-motor driving in automotive applications. It includes an ISO9141 compatible interface. A typical
application is shown in fig.6.
Voltage supply
The IC is supplied via an external reverse battery protection diode to the V pin. The typical operating voltage
VS
range is down to 8V.
Extended supply voltage range (ST)
The operating battery voltage range can be extended down to 6V using the additional components shown in
fig.7. A small inductor of L~150µH (I ~500mA) in series to the battery supply builts up a step up converter
peak
with the switching open drain output ST. The switching frequency is typical 100kHz with a fixed duty cycle of
50%. The step up converter starts below V < 8V, increases the supply voltage at the VS pin and switches off
VS
at V > 10V to avoid EME at nominal battery voltage. The diode D2 in series with the ST pin is necessary only
VS
for systems with negative battery voltage. No additional load can be driven by the step up converter.
Figure 7.
L9903
V
L1
D1
BAT
VS
ST
C1
C2
D2
-
+
V
=
STH
f
ST
12/17
L9903
FUNCTIONAL DESCRIPTION
(continued)
Control inputs (EN, DIR, PWM)
The cmos level inputs drive the device as shown in fig.4 and described in the truth table.
The device is activated with enable input HIGH signal. For enable input floating (not connected) or VEN=0V the
device is in standby mode. When activating the device a wake-up time of 50µs is recommended to stabilize the
internal supplies.
The DIR and PWM inputs control the driver of the external H-Bridge transistors. The motor direction can be
choosen with the DIR input, the duty cycle and frequency with the PWM input. Unconnected inputs are defined
by internal pull up resistors. During wake-up and braking and before disactivating the IC via enable both inputs
should be driven HIGH.
Truth table:
Driver stage for external
Status
Control inputs
EN DIR PWM TS
Device status
Diagnostic
Comment
power MOS
OV
x
UV
x
SC
x
GH1 GL1 GH2 GL2
DG
T
1
2
0
x
x
x
x
x
R
L
R
L
R
L
R
L
standby mode
1
1
0
0
0
L
thermal
shutdown
3
4
5
1
1
1
x
x
x
x
x
x
0
0
0
1
0
0
0
1
0
0
0
1
L
L
L
L
L
L
L
L
L
L
L
overvoltage
undervoltage
6)
6)
6)
6
6)
X
X
X
X
short circuit
6
7
8
1
1
1
0
x
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
L
H
H
H
L
L
H
H
L
L
L
H
H
H
braking mode
H
Symbols: x Don’t care
R:Resistive output
L: Output in sink condition
TS:Thermal shutdown
OV:Overvoltage
0: Logic LOW or not active
1: Logic HIGH or active
H: Output in source condition
UV:Undervoltage
T: Tristate
SC:Short Circuit
6. Only those external MOS transistors of the H-Bridge which are in short circuit condition are switched off. All others remain driven
by DIR and PWM.
Thermal shutdown
When the junction temperature exceeds T
all driver are switched in sink condition (L), the K- output is off and
JSD
the diagnostic DG is LOW until the junction temperature drops below T
- T
.
JSD
JHYST
Overvoltage Shutdown
When the supply voltage V exceeds the overvoltage threshold V
VS
all driver are switched in sink condi-
VSOVH
tion (L), the K- output is off and the diagnostic DG is LOW.
13/17
L9903
FUNCTIONAL DESCRIPTION
Undervoltage Shutdown
(continued)
For supply voltages below the undervoltage disable threshold the gate driver remains in sink condition (L) and
the diagnostic DG is low.
Short Circuit Detection
The output voltage atthe S1 and S2 pin of the H-Bridge is monitored by comparators to detect shorts to ground
or battery. The activated external highside MOS transistor will be switched off if the voltage drop remains below
the comparator threshold voltage V
and V for longer than the short current detection time t . The
S2TH SCd
S1TH
transistor remains in off condition, the diagnostic output goes LOW until the DIR or PWM input status will be
changed. The status doesn’t change for the other MOS transistors. The external lowside MOS transistor will be
switched off if the voltage drop passes over the comparator threshold voltage V
and V
for longer than
S1TH
S2TH
the short current detection time t . The transistor remains in off condition, the diagnostic output goes LOW
SCd
until the DIR or PWM input status will be changed. The status doesn’t change for the other MOS transistors.
Diagnostic Output (DG)
The diagnostic output provides a real time error detection, if monitors the following error stacks: Thermal shut-
down, overvoltage shutdown , undervoltage shutdown and short circuit shutdown. The open drain output with
internal pull up resistor is LOW if an error is occuring.
Bootstrap capacitor (CB1,CB2)
To ensure, that the external power MOS transistors reach the required R , a minimum gate source voltage
DSON
of 5V for logic level and 10V for standard power MOS transistors has to be guaranteed. The highside transistors
require a gate voltage higher than the supply voltage. This is achieved with the internal chargepump circuit in
combination with the bootstrap capacitor. The bootstrap capacitor is charged, when the highside MOS transistor
is OFF and the lowside is ON. When the lowside is switched OFF, the charged bootstrap capacitor is able to
supply the gate driver of the highside power MOS transistor. For effective charging the values of the bootstrap
capacitors should be larger than the gate-source capacitance of the power MOS and respect the required PWM
ratio.
Chargepump circuit (CP)
The reverse battery protection can be obtained with an external N-channel MOS transistor as shown in fig.6. In
this case its drain-bulk diode provides the protection. The output CP is intended to drive the gate of this tran-
sistor above the battery voltage to switch on the MOS and to bypass the drain-bulk diode with the R
. The
DSON
CP has a connection to VS through an internal diode and a 20kΩ resistor.
Gate drivers for the external N-channel power MOS transistors (GH1, GH2, GL1, GL2)
High level at EN activates the driver of the external MOS under control of the DIR and PWM inputs (see truth
table and driving sequence fig.4). The external power MOS gates are connected via series resistors to the de-
vice to reduce electro magnetic emission (EME) of the system. The resistors influence the switching behaviour.
They have to be choosen carefully. Too large resistors enlarge the charging and discharging time of the power
MOS gate and can generate cross current in the halfbridges. The driver assures a longer switching delay time
from source to sink stage in order to prevent the cross conduction.
The gate source voltage is limited to 14V. The charge/discharge current is limited by the R
of the driver.
DSON
The drivers are not protected against shorts.
14/17
L9903
FUNCTIONAL DESCRIPTION (continued)
Programmable cross conduction protection
The external power MOS transistors in H-Bridge ( two half bridges) configuration are switched on with an addi-
tional delay time t to prevent cross conduction in the halfbridge. The cross conduction protection time
is determined by the external capacitor C and resistor R at the PR pin. The capacitor C is charged
CCP
t
CCP
PR
PR
PR
up to the voltage limit V . A level change on the control inputs DIR and PWM switches off the concerned ex-
PRH
ternal MOS transistor and the charging source at the PR pin. The resistor R discharges the capacitor C
.
PR
PR
The concerned external power MOS transistor will be switched on again when the voltage at PR reaches the
value of V . After that the CPR will be charged again. The capacitor C should be choosen between 100pF
PRL
PR
and 1nF. The resistor R should be higher than 7kW. The delay time can be expressed as follows:
PR
t
t
= R · C · ln N
with N = V
/ V
= 2
PRL
CCP
PR
PR
PR
PR
PRH
= 0.69 · R · C
CCP
PR
PR
ISO-Interface
The ISO-Interface provides the communication between the micro controller and a serial bus with a baud rate
up to 60kbit/s via a single wire which is V and GND compatible. The logic level transmission input TX drives
BAT
the open drain K-output. The K output can be connected to a serial bus with a pull up resistor to V . The K-
BAT
pin is protected against overvoltage, short to GND and VS and can be driven beyond V and GND. During lack
VS
of V or GND the output shows high impedance characteristic. The open drain output RX with an internal pull
VS
up resistor monitors the status at the K-pin to read the received data and control the transmitted data. Short
circuit condition at K-pin is recognized if the internal open drain transistor isn’t able to pull the voltage potential
at K-pin below the threshold of 0.45·V . Then the RX stays in high condition. A timer starts and switches the
VS
open drain transistor after typ. 20µs off. A next low at the TX input resets the timer and the open drain transistor
switches on again.
Figure 8. Functional schematic of the ISO-interface
RX
K
R
RX
0.5 •V
=
VS
V
CC
R
TX
TX
I
KH
R
S
R
delay
Q
T
SH
15/17
L9903
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A
A1
B
C
D
E
e
2.35
0.1
2.65 0.093
0.3 0.004
0.104
0.012
0.020
0.013
0.512
0.299
0.33
0.23
12.6
7.4
0.51 0.013
0.32 0.009
13
0.496
0.291
7.6
1.27
0.050
H
h
10
0.25
0.4
10.65 0.394
0.75 0.010
0.419
0.030
0.050
L
1.27 0.016
SO20
K
0° (min.)8° (max.)
L
h x 45°
A
A1
K
B
C
e
H
D
20
11
E
1
10
SO20MEC
16/17
L9903
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights ofthird partieswhich may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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17/17
相关型号：
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