L9903TR [STMICROELECTRONICS]
MOTOR BRIDGE CONTROLLER; 汽车桥控制器
| 型号： | L9903TR |
| 厂家： | 
ST |
| 描述： | MOTOR BRIDGE CONTROLLER |
| 文件： | 总17页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L9903
MOTOR BRIDGE CONTROLLER
1
FEATURES
Figure 1. Package
■ OPERATING SUPPLY VOLTAGE 8V TO 20V,
OVERVOLTAGE MAX. 40V
■ OPERATING SUPPLY VOLTAGE 6V WITH
IMPLEMENTED STEPUP CONVERTER
■ QUIESCENT CURRENT IN STANDBY MODE
SO20
LESS THAN 50µA
■ ISO 9141 COMPATIBLE INTERFACE
Table 1. Order Codes
■ CHARGE PUMP FOR DRIVING A POWER
MOS AS REVERSE BATTERY PROTECTION
Part Number
L9903
Package
SO20
■ PWM OPERATION FREQUENCY UP TO
30KHZ
L9903TR
Tape & Reel
■ PROGRAMMABLE CROSS CONDUCTION
PROTECTION TIME
2
DESCRIPTION
■ OVERVOLTAGE, UNDERVOLTAGE, SHORT
Control circuit for power MOS bridge driver in auto-
motive applications with ISO 9141bus interface.
CIRCUIT AND THERMAL PROTECTION
■ REAL TIME DIAGNOSTIC
Figure 2. Block Diagram
10
VS
R
CP
Reference
BIAS
VCC
-
+
1
ST
11
CP
Charge
pump
=
V
STH
13
12
CB1
GH1
f
ST
VCC
Overvoltage
14
Undervoltage
S1
R
DG
2
DG
EN
Thermal shutdown
R
=
S1
V
S1TH
19
GL1
4
5
R
R
EN
GL1
18
GL2
S2
DIR
R
GL2
R
R
DIR
VCC
17
PWM
3
6
PWM
PR
R
S2
=
V
S2TH
15
16
GH2
CB2
Timer
ISO-Interface
9
K
7
8
RX
TX
R
R
RX
VCC
=
0.5
V
VS
•
TX
I
KH
20
GND
REV. 4
1/17
October 2005
L9903
Table 2. Pin Function
N°
1
Pin
ST
Description
Open Drain Switch for Stepup converter
Open drain diagnostic output
PWM input for H-bridge control
Enable input
2
DG
PWM
EN
3
4
5
DIR
PR
Direction select input for H-bridge control
6
Programmable cross conduction protection time
ISO 9141 interface, receiver output
7
RX
8
TX
ISO 9141 interface, transmitter input
9
K
ISO 9141 Interface, bidirectional communication K-line
Supply voltage
10
11
12
13
14
15
16
17
18
19
20
VS
CP
Charge pump for driving a power MOS as reverse battery protection
Gate driver for power MOS highside switch in halfbridge 1
External bootstrap capacitor
GH1
CB1
S1
Source/drain of halfbridge 1
GH2
CB2
S2
Gate driver for power MOS highside switch in halfbridge 2
External bootstrap capacitor
Source/drain of halfbridge 2
GL2
GL1
GND
Gate driver for power MOS lowside switch in halfbridge 2
Gate driver for power MOS lowside switch in halfbridge 1
Ground
Figure 3. Pin Connection (Top view)
ST
DG
PWM
EN
1
20
19
18
17
16
15
14
13
12
11
GND
GL1
GL2
S2
2
3
4
DIR
PR
5
CB2
GH2
S1
6
RX
7
TX
8
CB1
GH1
CP
K
9
VS
10
SO20
2/17
L9903
Table 3. Absolute Maximum Ratings
Symbol
, V
Parameter
Value
-0.3 to 40
-100
Unit
V
V
I
Bootstrap voltage
CB2
CB1
, I
Bootstrap current
mA
V
CB1 CB2
V
Charge pump voltage
Charge pump current
Logic input voltage
-0.3 to 40
-1
CP
CP
I
mA
V
V
,V
EN
-0.3 to 7
DIR
,V
,V
PWM TX
I
,I
Logic input current
1
mA
DIR EN
,I
,I
PWM TX
V
I
,V
Logic output voltage
Logic output current
Gate driver voltage
Gate driver current
Gate driver voltage
Gate driver current
K-line voltage
-0.3 to 7
-1
V
mA
V
DG
RX
,I
DG RX
V
, V
-0.3 to V + 10
GH1 GH2
SX
I
, I
-1
-0.3 to 10
-10
mA
V
GH1 GH2
V
, V
GL1
GL1
GL2
I
, I
mA
V
GL2
V
-20 to V
S
K
V
Programming input voltage
Programming input current
Source/drain voltage
Source/drain current
Output voltage
-0.3 to 7
-1
V
PR
I
mA
V
PR
V
I
, V
-2 to V + 2
S1
S2
VS
, I
-10
-0.3 to 40
-1
mA
V
S1 S2
V
ST
ST
I
Step up output current
DC supply voltage
mA
V
V
VSDC
-0.3 to 27
40
V
Pulse supply voltage (T < 500ms)
DC supply current
V
VSP
I
VS
-100
mA
For externally applied voltages or currents exceeding these limits damage of the device may occur!
All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body
model with R=1.5k
0.2mJ.
Ω, C=100pF and discharge voltage 2kV, corresponding to a maximum discharge energy of
Table 4. Thermal Data
Symbol
Parameter
Value
-40 to 150
min 150
typ 15
Unit
°C
T
Operating junction temperature
J
T
Junction temperature thermal shutdown threshold
Junction thermal shutdown hysteresis
°C
JSD
T
°C
JSDH
1)
R
85
°C/W
th j-amb
Thermal resistance junction to ambient
1. see application note 110 for SO packages.
.
3/17
L9903
Table 5. Electrical Characteristcs
(8V < V < 20V, V = HIGH, -40°C
≤
T
≤ 150°C, unless otherwise specified. The voltages are refered to
J
VS
EN
GND and currents are assumed positive, when current flows into the pin
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Supply (VS)
V
Overvoltage disable HIGH
threshold
20
22
24
V
VS OVH
Overvoltage threshold hysteresis 2)
V
1.6
V
V
VS OVh
V
Undervoltage disable HIGH
threshold
6
7
VS UVH
V
Undervoltage threshold
0.66
8.1
V
VS UVh
2)
hysteresis
I
Supply current
V
= 0 ; V = 13.5V; T < 85°C
50
13
µA
VSL
EN
VS
J
I
Supply current, pwm-mode
V
V
= 13.5V; V = HIGH;
mA
VSH
VS
EN
= LOW; S1 = S2 = GND
DIR
f
= 20kHz; C
= 0.1µF;
= 4.7nF;
PWM
CBX
GHX
C
R
= 4.7nF; C
GLX
= 10kΩ; C = 150pF
PR
PR
I
Supply current, dc-mode
V
V
= 13.5V; V = HIGH;
5.8
10
mA
VSD
VS
EN
= LOW; S1 = S2 = GND
DIR
V
PWM
= LOW; C
= 4.7nF
GHX
R
= 10kΩ; C = 150pF
PR
PR
Enable input (EN)
V
Low level
High level
1.5
V
V
V
ENL
V
3.5
16
ENH
2)
V
1
ENh
Hysteresis threshold
R
Input pull down resistance
V
= 5V
50
100
1.5
kΩ
EN
EN
H-bridge control inputs (DIR, PWM)
V
Input low level
Input high level
V
V
DIRL
V
PWML
V
3.5
16
DIRH
V
PWMH
2)
V
1
V
DIRh
Input threshold hysteresis
Internal pull up resistance
V
PWMh
R
V
= 0; V = 0
PWM
50
100
kΩ
DIR
DIR
3)
R
PWM
to internal VCC
DIAGNOSTIC output (DG)
V
Output drop
I
= 1mA
= 0V
0.6
40
V
DG
DG
DG
R
Internal pull up resistance
V
10
20
2
kΩ
DG
3)
to internal VCC
4)
Programmable cross conduction protection
N
Threshold voltage ratio V
/
PRH
1.8
2.2
1.5
PR
R
= 10kΩ
PR
V
PRL
I
Current capability
-0.5
mA
V
PR
V
= 2V
PR
ISO interface, transmission input (TX)
V
Input low level
TXL
4/17
L9903
Table 5. Electrical Characteristcs (continued)
(8V < V < 20V, V = HIGH, -40°C
≤
T ≤
J
150°C, unless otherwise specified. The voltages are refered to
VS
EN
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition
Input high level
Min.
Typ.
Max.
Unit
V
V
3.5
TXH
V
Input hysteresis voltage 2)
1
V
TXh
R
TX
Internal pull up resistance to
internal VCC 3)
V
= 0
TX
10
20
40
kΩ
ISO interface, receiver output (RX)
V
Output voltage high stage
4.5
5
5.5
20
V
RXL
TX = HIGH; I = 0; V = V
VS
RX
K
R
Internal pull up resistance
TX = HIGH;
= 0V
10
40
kΩ
RX
3)
V
RX
to internal VCC
R
ON resistance to ground
TX = LOW;
= 1mA
90
Ω
RXON
I
RX
t
Output high delay time
Output low delay time
Fig. 1
0.5
0.5
µs
µs
RXH
t
RXL
ISO interface, K-line (K)
V
Input low level
-20V
0.45 ·
KL
V
VS
V
Input high level
0.55 ·
VVS
V
KH
VS
V
Input hysteresis voltage 2)
0.025·
0.8V
Kh
V
VS
I
Input current
V
= HIGH
-5
25
30
µA
Ω
KH
TX
TX
TX
R
ON resistance to ground
Short circuit current
Transmission frequency
V
V
= LOW; I =10mA
10
KON
KSC
K
I
= LOW
40
60
130
mA
kHz
f
100
2
K
2. not tested in production: guaranteed by design and verified in characterization
3. Internal V is 4.5V ... 5.5V
VCC
4. see page 18 for calculation of programmable cross conduction protection time
t
Rise time
V
= 13.5V; Fig. 1
VS
6
µs
Kr
External loads at K-line:
R = 510Ω pull up
K
to V
VS
C = 2.2nF to GND
K
t
Fall time
2
4
4
6
µs
µs
µs
µs
Kf
t
Switch high delay time
Switch low delay time
Short circuit detection time
17
17
40
KH
t
KL
t
V
= 13.5V;
VS
10
SH
TX = LOW
V > 0.55 · V
K
VS
Charge pump
Charge pump voltage
V
V
VS
V
VS
V
VS
= 8V
V
VS
+7V
VVS
+14V
VVS
+14V
VVS
CP
= 13.5V
= 20V
V
VS
+10V
V
VS
+10V
+14V
5/17
L9903
Table 5. Electrical Characteristcs (continued)
(8V < V < 20V, V = HIGH, -40°C
≤
T ≤
J
150°C, unless otherwise specified. The voltages are refered to
VS
EN
GND and currents are assumed positive, when current flows into the pin
Symbol Parameter Test Condition
Charging current = 13.5V
Min.
Typ.
Max.
Unit
I
t
V
VS
-50
-75
µA
CP
V
= V + 8V
CP
VS
2)
V
C
= 13.5V
= 10nF
1.2
4
ms
CP
VS
Charging time
= V + 8V
CP
V
CP
VS
f
Charge pump frequency
V
= 13.5V
250
500
750
kHz
CP
VS
Drivers for external highside power MOS
V
V
Bootstrap voltage
V
VS
V
VS
V
VS
= 8V; I
=13.5V; I
= 20V; I
= 0; V = 0
7.5
10
10
14
14
14
V
V
V
CB1
CB2
CBX
SX
= 0; V = 0
SX
CBX
= 0; V = 0
SX
CBX
R
R
ON-resistance of SINK stage
10
Ω
GH1L
GH2L
V
= 8V; V = 0
SX
CBX
I
= 50mA; T = 25°C
J
GHX
20
Ω
V
CBX
= 8V; V = 0
SX
I
= 50mA; T = 125°C
GHX
J
R
R
ON-resistance of SOURCE stage
Gate ON voltage (SOURCE)
I
I
= -50mA; T = 25°C
10
20
Ω
Ω
GH1H
GH2H
GHX
J
= -50mA; T = 125°C
GHX
J
V
V
V
C
= V = 8V; I
= 0;
V
+6.5V
V
VS
+14V
GH1H
VS
SX
GHX
VS
= 0.1µF
GH2H
CBX
V
VS
= V = 13.5V; I
= 0;
V
VS
V
VS
SX
GHX
C
= 0.1µF
+10V
+14V
CBX
V
VS
= V = 20V; I
= 0;
V
VS
V
VS
SX
GHX
C
= 0.1µF
+10V
+14V
CBX
R
R
Gate discharge resistance
Sink resistance
EN = LOW
10
100
100
kΩ
kΩ
GH1
GH2
R
R
10
S1
S2
Drivers for external lowside power MOS
R
R
ON-resistance of SINK stage
ON-resistance of SOURCE stage
Gate ON voltage (SOURCE)
I
I
= 50mA; T = 25°C
10
20
Ω
Ω
GL1L
GL2L
GLX
J
= 50mA; T = 125°C
GLX
J
R
I
I
= -50mA; T = 25°C
10
20
Ω
Ω
GL1H,
GLX
J
R
= -50mA; T = 125°C
GL2H
GLX
J
V
GL1H,
V
V
V
= 8V; I
= 0
7V
10V
10V
V
V
VS
VS
VS
GLX
VS
VS
V
GL2H
= 13.5V; I
= 0
GLX
= 20V; I
= 0
14V
GLX
R
R
Gate discharge resistance
EN = LOW
10
100
kΩ
GL1
GL2
2. not tested in production: guaranteed by design and verified in characterization
Timing of the drivers
t
t
Propagation delay time
Fig. 2
500
ns
GH1LH
V
VS
= 13.5V
GH2LH
V
S1
= V =0
S2
C
= 0.1µF
CBX
RPR= 10kW
6/17
L9903
Table 5. Electrical Characteristcs (continued)
(8V < V < 20V, V = HIGH, -40°C
≤
T ≤
J
150°C, unless otherwise specified. The voltages are refered to
VS
EN
GND and currents are assumed positive, when current flows into the pin
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
t
t
Propagation delay time including Fig. 2
0.7
1
1.3
µs
GH1LH
cross conduction protection time
V
VS
= 13.5V
GH2LH
t
V
S1
= V =0
CCP
S2
C
= 0.1µF
CBX
t
t
Propagation delay time
500
500
ns
ns
GH1HL
GH2HL
C
R
5)
= 150pF;
= 10kΩ;
PR
PR
t
t
Propagation delay time
Fig. 2
GL1LH
V
V
= 13.5V
VS
GL2LH
= V =0
S1
S2
C
= 0.1µF
CBX
R
= 10kΩ
PR
t
t
Propagation delay time including Fig. 2
0.7
1
1.3
µs
ns
GL1LH
cross conduction protection time
V
VS
= 13.5V
GL2LH
t
V
S1
= V =0
CCP
S2
= 0.1µF
C
CBX
t
t
Propagation delay time
500
GL1HL
GL2HL
C
R
5)
= 150pF;
= 10kΩ;
PR
PR
t
t
Rise time
Fall time
Rise time
Fall time
Fig. 2
1
1
1
1
µs
µs
µs
µs
GH1r
V
V
= 13.5V
= V =0
VS
GH2r
S1
S2
= 0.1µF
t
t
GH1f
C
CBX
GH2f
t
t
GL1r
C
C
R
= 4.7nF
= 4.7nF
GHX
GLX
GL2r
= 10kΩ;
PR
t
t
GL1f
GL2f
Short Circuit Detection
V
V
Threshold voltage
4
V
S1TH
S2TH
t
Detection time
5
1
10
15
µs
SCd
Step up converter (ST)
(5.2V ≤ V < 10V)
VS
V
ST disable HIGH threshold
10
2
V
V
STH
V
ST disable threshold hysteresis
STh
2)
voltage
R
Open drain ON resistance
20
Ω
DSON
V
VS
= 5.2V;
I
ST
= 50mA
f
ST
Clock frequency
50
100
149
kHz
2. not tested in production: guaranteed by design and verified in characterization
5. tested with differed values in production but guaranteed by design and verified in characterization
7/17
L9903
Figure 4. Timing of the ISO-interface
V
TX
0.7
•
V
V C C
0.3
t
V
0.3
V
V C C
•
•
VC C
t
t
t
t
KL
KH
V
K
t
t
Kr
Kf
80%
I
> I
KSC
K
0.55
0.45
•
V
V S
•
V
V S
20%
t
t
RXH
RXL
V
RX
0.7
•
V
VC C
0.3
•
V
V C C
open drain
transistor at
K-pin
t
SH
ON
OFF
Figure 5. Timing of the drivers for the external MOS regarding the inputs DIR and PWM
PWM
or
DIR
50%
t
t
tGHXLH
tGHXr
tGHXHL tGHXf
80%
20%
GHX
GLX
tGLXHL tGLXf
tGLXr
tGLXLH
80%
20%
t
8/17
L9903
Figure 6. I(V) characteristics of the K-Line for TX = HIGH and VVS=13.5V
IK [mA]
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-20
-10
0
10
20
VK [V]
Figure 7. Driving sequence
EN
DIR
PW M
braking
G H1
G L1
G H2
G L2
Note:
Before standby mode
(EN = low) a braking phase
is mandatory to discharge
the stored energy of the
motor.
9/17
L9903
Figure 8. Charging time of an external capacitor of 10nF connected to CP pin at VVS=8V and
VVS=13.5V
voltage [V]
Charging time of a 10nF load at CP
30
CP for VS=13.5V
25
CP for VS=8V
20
15
10
EN
5
0
0
1
2
3
4
time [ms]
Figure 9. Application Circuit Diagram
V
BAT
D1
VS 10
R
CP
C
C
S2
ST
S1
Voltage
Reference
BIAS
VCC
-
+
1
Regulator
11 CP
Charge
pump
V
=
STH
13 CB1
12 GH1
R
f
C1
ST
V
CC
C
B1
VCC
Overvoltage
Undervoltage
14 S1
S1
R
DG
DG
EN
2
4
Thermal shutdown
M
R
R
V
=
S1TH
R
R
19 GL1
GL1
R
EN
18 GL2
GL2
DIR
5
R
R
R
R
DIR
VCC
µC
17 S2
S2
PWM
PWM
PR
3
6
V
=
C
S2TH
B2
R
15 GH2
16 CB2
Timer
C
R
PR
PR
ISO-Interface
9
K
RX
TX
7
8
K-Line
R
R
RX
VCC
0.5 • V
=
VS
TX
I
KH
20 GND
GND
10/17
L9903
3
FUNCTIONAL DESCRIPTION
3.1 General
The L9903 integrated circuit (IC) is designed to control four external N-channel MOS transistors in H-Bridge con-
figuration for DC-motor driving in automotive applications. It includes an ISO9141 compatible interface. A typical
application is shown in fig.9.
3.2 Voltage supply
The IC is supplied via an external reverse battery protection diode to the V pin. The typical operating voltage
VS
range is down to 8V.
The supply current consumption of the IC composes of static and a dynamic part. The static current is typically
5.8mA. The dynamical current I
is depending of the PWM frequency f and the required gate charge Q
PWM Gate
dyn
of the external power mos transistor. The current can be estimated by the expression:
I
= 2 · f · Q
dyn
PWM
Gate
An external power transistor with a gate charge of Q
= 160nC and a PWM frequency of f
= 20kHz re-
PWM
Gate
quires a dynamical supply current of I
= 6.4mA.
dyn
The total supply current consumption is I = 5.8mA + 6.4mA = 12.2mA.
VS
3.3 Extended supply voltage range (ST)
The operating battery voltage range can be extended down to 6V using the additional components shown in
fig.7. A small inductor of L~150µH (I ~500mA) in series to the battery supply builts up a step up converter
peak
with the switching open drain output ST. The switching frequency is typical 100kHz with a fixed duty cycle of
50%. The step up converter starts below V < 8V, increases the supply voltage at the V pin and switches off
VS
S
at V > 10V to avoid EME at nominal battery voltage. The diode D2 in series with the ST pin is necessary only
VS
for systems with negative battery voltage. No additional load can be driven by the step up converter.
Figure 10.
L9903
V
L1
D1
BAT
VS
ST
C1
C2
D2
-
+
V
=
STH
f
ST
11/17
L9903
3.4 Control inputs (EN, DIR, PWM)
The cmos level inputs drive the device as shown in fig.7 and described in the truth table.
The device is activated with enable input HIGH signal. For enable input floating (not connected) or VEN=0V the
device is in standby mode. When activating the device a wake-up time of 50µs is recommended to stabilize the
internal supplies.
The DIR and PWM inputs control the driver of the external H-Bridge transistors. The motor direction can be
choosen with the DIR input, the duty cycle and frequency with the PWM input. Unconnected inputs are defined
by internal pull up resistors. During wake-up and braking and before disactivating the IC via enable both inputs
should be driven HIGH.
Table 6. Truth table:
Driver stage for external
Status
Control inputs
EN DIR PWM TS
Device status
Diagnostic
Comment
power MOS
OV
x
UV
x
SC
x
GH1 GL1 GH2 GL2
DG
T
7)
7)
1
2
0
x
x
x
x
x
R
L
R
L
standby mode
R
R
1
1
0
0
0
L
L
L
thermal
shutdown
3
4
5
1
1
1
x
x
x
x
x
x
0
0
0
1
0
0
0
1
0
0
0
1
L
L
L
L
L
L
L
L
L
L
L
overvoltage
undervoltage
6)
6)
6)
6
6)
X
X
X
X
short circuit
6
7
8
1
1
1
0
x
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
L
H
H
H
L
L
H
H
L
L
L
H
H
H
braking mode
H
Symbols: x Don't care
R:Resistive output
L: Output in sink condition
TS:Thermal shutdown
OV:Overvoltage
0: Logic LOW or not active
1: Logic HIGH or active
H: Output in source condition
T: Tristate
UV:Undervoltage
SC:Short Circuit
6. Only those external MOS transistors of the H-Bridge which are in short circuit condition are switched off. All others remain driven
by DIR and PWM.
7. See Application Note AN2229
3.5 Thermal shutdown
When the junction temperature exceeds T
the diagnostic DG is LOW until the junction temperature drops below T
all driver are switched in sink condition (L), the K- output is off and
JSD
- T
.
JSD
JHYST
3.6 Overvoltage Shutdown
When the supply voltage V exceeds the overvoltage threshold V
all driver are switched in sink condition
VSOVH
VS
(L), the K- output is off and the diagnostic DG is LOW.
3.7 Undervoltage Shutdown
For supply voltages below the undervoltage disable threshold the gate driver remains in sink condition (L) and
the diagnostic DG is low.
12/17
L9903
3.8 Short Circuit Detection
The output voltage at the S1 and S2 pin of the H-Bridge is monitored by comparators to detect shorts to ground
or battery. The activated external highside MOS transistor will be switched off if the voltage drop remains below
the comparator threshold voltage V
and V
for longer than the short current detection time t
. The
SCd
S1TH
S2TH
transistor remains in off condition, the diagnostic output goes LOW until the DIR or PWM input status will be
changed. The status doesn't change for the other MOS transistors. The external lowside MOS transistor will be
switched off if the voltage drop passes over the comparator threshold voltage V
and V
for longer than
S1TH
S2TH
the short current detection time t
. The transistor remains in off condition, the diagnostic output goes LOW
SCd
until the DIR or PWM input status will be changed. The status doesn't change for the other MOS transistors.
3.9 Diagnostic Output (DG)
The diagnostic output provides a real time error detection, if monitors the following error stacks: Thermal shut-
down, overvoltage shutdown , undervoltage shutdown and short circuit shutdown. The open drain output with
internal pull up resistor is LOW if an error is occuring.
3.10 Bootstrap capacitor (CB1,CB2)
To ensure, that the external power MOS transistors reach the required R
, a minimum gate source voltage
DSON
of 5V for logic level and 10V for standard power MOS transistors has to be guaranteed. The highside transistors
require a gate voltage higher than the supply voltage. This is achieved with the internal chargepump circuit in
combination with the bootstrap capacitor. The bootstrap capacitor is charged, when the highside MOS transistor
is OFF and the lowside is ON. When the lowside is switched OFF, the charged bootstrap capacitor is able to
supply the gate driver of the highside power MOS transistor. For effective charging the values of the bootstrap
capacitors should be larger than the gate-source capacitance of the power MOS and respect the required PWM
ratio.
3.11 Chargepump circuit (CP)
The reverse battery protection can be obtained with an external N-channel MOS transistor as shown in fig.6. In
this case its drain-bulk diode provides the protection. The output CP is intended to drive the gate of this tran-
sistor above the battery voltage to switch on the MOS and to bypass the drain-bulk diode with the R
. The
DSON
CP has a connection to VS through an internal diode and a 20k
Ω resistor.
3.12 Gate drivers for the external N-channel power MOS transistors (GH1, GH2, GL1, GL2)
High level at EN activates the driver of the external MOS under control of the DIR and PWM inputs (see truth
table and driving sequence fig.4). The external power MOS gates are connected via series resistors to the de-
vice to reduce electro magnetic emission (EME) of the system. The resistors influence the switching behaviour.
They have to be choosen carefully. Too large resistors enlarge the charging and discharging time of the power
MOS gate and can generate cross current in the halfbridges. The driver assures a longer switching delay time
from source to sink stage in order to prevent the cross conduction.
The gate source voltage is limited to 14V. The charge/discharge current is limited by the R
The drivers are not protected against shorts.
of the driver.
DSON
3.13 Programmable cross conduction protection
The external power MOS transistors in H-Bridge ( two half bridges) configuration are switched on with an addi-
tional delay time t to prevent cross conduction in the halfbridge. The cross conduction protection time t
CCP
CCP
is determined by the external capacitor C and resistor R
at the PR pin. The capacitor C is charged up
PR
PR
PR
to the voltage limit V
. A level change on the control inputs DIR and PWM switches off the concerned external
PRH
MOS transistor and the charging source at the PR pin. The resistor R discharges the capacitor C . The con-
PR
PR
cerned external power MOS transistor will be switched on again when the voltage at PR reaches the value of
. After that the CPR will be charged again. The capacitor C should be choosen between 100pF and 1nF.
V
PRL
PR
The resistor R should be higher than 7kW. The delay time can be expressed as follows:
PR
13/17
L9903
t
t
= R · C · ln N
with N = V
/ V
= 2
PRL
CCP
PR
PR
PR
PR
PRH
= 0.69 · R · C
CCP
PR
PR
3.14 ISO-Interface
The ISO-Interface provides the communication between the micro controller and a serial bus with a baud rate
up to 60kbit/s via a single wire which is V and GND compatible. The logic level transmission input TX drives
BAT
the open drain K-output. The K output can be connected to a serial bus with a pull up resistor to V
. The K-
BAT
pin is protected against overvoltage, short to GND and VS and can be driven beyond V and GND. During lack
VS
of V or GND the output shows high impedance characteristic. The open drain output RX with an internal pull
VS
up resistor monitors the status at the K-pin to read the received data and control the transmitted data. Short
circuit condition at K-pin is recognized if the internal open drain transistor isn't able to pull the voltage potential
at K-pin below the threshold of 0.45·V . Then the RX stays in high condition. A timer starts and switches the
VS
open drain transistor after typ. 20µs off. A next low at the TX input resets the timer and the open drain transistor
switches on again.
Figure 11. Functional schematic of the ISO-interface
RX
K
R
RX
0.5 •V
VS
=
V
CC
R
TX
TX
I
KH
R
S
R
delay
Q
T
SH
14/17
L9903
Figure 12. SO20 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.104
A
A1
B
2.35
0.10
0.33
0.23
12.60
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
13.00 0.496
0.012
0.200
C
0.013
(1)
D
0.512
E
e
7.40
7.60 0.291
0.299
0.050
1.27
H
10.0
0.25
0.40
10.65 0.394
0.75 0.010
1.27 0.016
0˚ (min.), 8˚ (max.)
0.10
0.419
h
0.030
L
0.050
k
ddd
0.004
SO20
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
0016022 D
15/17
L9903
Table 7. Revision History
Date
Revision
Description of Changes
Migration from ST-Press to EDOCS DMS
January 2004
3
4
October 2005
Inserted on pag 12 AN2229 ref.
16/17
L9903
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
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17/17
相关型号：
L9907TR
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