L8202 [STMICROELECTRONICS]
MULTIFUNCTION ANALOG ASIC; 多功能模拟量ASIC
| 型号： | L8202 |
| 厂家： | 
ST |
| 描述： | MULTIFUNCTION ANALOG ASIC |
| 文件： | 总15页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L8202
MULTIFUNCTION ANALOG ASIC
1 FEATURES
Figure 1. Package
■ Flexible Motor Driver configuration
– 4 DC Motor drivers (1.5A Peak Current) or
– 2 DC Motor drivers & 1 Dual Full Bridge Step-
per Motor driver
TQFP64
■ 2 Switching Voltage regulators
■ 6 Open Drain Drivers
■ Serial Input Port
Table 1. Order Codes
Part Number
Package
L8202
TQFP64 (Exposed Pad Down)
■ 4 Operational amplifiers
■ Low voltage Supervisor
■ Thermal Protection
The regulated Voltages are: VCC that can be ei-
ther 3.3V or +5V and VDD, programmable by a re-
sistor divider network from +3V to +17V
2 DESCRIPTION
L8202 is a multifunction analog ASIC designed for
MFP Inkjet printer applications.
It is possible to increase the Output Current capa-
bility of the VDD regulator by adding an external
discrete Power DMOS.
L8202 integrates 4 full H Bridge drivers, 2 switch-
ing Buck type voltage regulators, 4 operational
amplifiers, 6 open drain drivers, Reset Generation
circuitry and over temperature protection circuitry.
An internal regulator is present in the IC in order to
supply several internal blocks. The 5V output volt-
age is filtered on pin V5 (Typical filter capacitor =
100nF) .
Figure 2. Block Diagram
PWM gen.
L8202
DC motor
DC MTR #1 H
Drive
OP.
Amps
LM358
like
DC MTR #2 H
Drive
DC motor
Phase A H
Drive
2 DC
motor
VPH regulator
1 Stepper motor or
Phase B H
Drive
Vcc regulator
3.3V or 5V
SERIAL
INTERFACE
LED
Drivers
Sleep mode
Reset gen.
Vcc switch
Rev. 2
1/15
February 2005
L8202
Table 2. Pin Description
N°
1
Pin
PH_A+
Function
Stepper Motor Driver Output A plus
2
R_Sense_A
PH_A-
Phase A Stepper Motor Driver Current Sense Resistor
Stepper Motor Driver Output A minus
3
4
No Connection
5
Test
This pin is used to measure internal Temperature of ASIC.
Gate drive pin for external Power DMOS. N/C when internal FET is used.
6
VDD_gate
VDD_source1
7
Source pin #1 for VDD internal FET. Used as differential input when external Power
DMOS is used.
8
VDD_source2
Source pin #2 for VDD internal FET. Used as differential input when external Power
DMOS is used.
9
VDD_drain1
VDD_drain2
Vs(VDD)
Drain pin #1 for VDD internal FET. N/C when an external Power DMOS is used.
Drain pin #2 for VDD internal FET. N/C when an external Power DMOS is used.
VDD regulator Supply voltage.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD_FB
Feedback for VDD Regulator
No Connection
PH_B-
R_Sense_B
PH_B+
Stepper Motor Driver Output B minus
Phase B Stepper Motor Driver Current Sense Resistor
Stepper Motor Driver Output B plus
DC4 or Stepper PH_B Supply voltage.
Source pin for Vcc Regulator. Internally tied to other Vs.
Output pin for Vcc Regulator
Vs(DC4)
Vs(Vcc)
Vcc_out
ODD 6
Open Drain Driver #6
Vcc_Select
Vcc_FB
This pin is used to select 5V or 3.3V for Vcc
Feedback for Vcc Regulator
DC4_PWM
DC3_PWM
DC1_PWM
DC2_PWM
Analog_GND
PWM input for DC motor driver #4
PWM input for DC motor driver #3
PWM input for DC motor driver #1
PWM input for DC motor driver #2
Analog Ground.
Vcc_Switch_Out Vcc switched output pin.
Vcc_In
V5
Vcc input pin.
5V output pin.
No Connection.
Vs(DC1)
DC1B
DC1 Supply voltage.
Negative output for DC motor driver #1
2/15
L8202
Table 2. (continued)
N°
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin
GND(DC1)
DC1A
Function
DC1 Ground.
Positive output for DC motor driver #1
Open Drain Driver #5.
ODD 5
ODD 4
ODD 3
ODD 2
ODD1
Open Drain Driver #4.
Open Drain Driver #3.
Open Drain Driver #2.
Open Drain Driver #1.
nCS
Chip Select, active Low
Serial Clock
SCLK
SDI
Serial Data In
nRESET
GND(Logic)
DC2A
nRESET pin.
Logic Ground
Positive output for DC motor driver #2
DC2 Ground.
GND(DC2)
DC2B
Negative output for DC motor driver #2
DC2 Supply voltage.
Vs(DC2)
OA_GND
OA4-
Ground for Op-Amps
Inverting Input for Op-Amp #4
Non-Inverting Input For Op-Amp #4
Output for Op-Amp #4.
OA4+
OA4Out
OA3-
Inverting Input for Op-Amp #3
Non-Inverting Input for Op-Amp #3
Output for Op-Amp #3
OA3+
OA3Out
OA2-
Inverting Input for Op-Amp #2
Non-Inverting Input for Op-Amp #2
Output for Op-Amp #2.
OA2+
OA2Out
OA1-
Inverting Input for Op-Amp #1
Non-Inverting Input for Op-Amp #1
Output for Op-Amp #1.
OA1+
OA1Out
OA_Supply
Vs(DC3)
Op Amp Supply voltage.
DC3 or Stepper PH_A Supply voltage.
3/15
L8202
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
Vs
Supply voltage, including ripple
Differential Voltage between Power pins, Supply pins and Ground
44
VOD
44
V
Vcc_IN, Vcc_FB VCC
VDD Max VDD Voltage (@I
7
V
= 0.0A)
17
V
VDD
I
VDD Output current
3
A
VDD
V
Op Amp Supply Voltage
Op Amp Differential Voltage
Maximum voltage on nRESET
Junction Temperature
7
7
V
CCOpAmp
V
V
DIFF OpAmp
Vmaxrst*
Vcc_in
150
V
T
°C
°C
j
T
Storage Temperature
-55 to 150
stg
Table 4. Recommended Operating Conditions (Tj = 25°C, VS= 32V, unless otherwise specified)
Symbol
Vs
Parameter
Supply voltage, including ripple
Vs Standby Current
Test Conditions
Min.
Typ.
30
3
Max.
38
Unit
V
24
IVs
In the stand by
15
mA
mode(sleep=1)
Vcc_IN,
Vcc_FB
Vcc voltage
Vcc = 3.3V
Vcc = 5.0V
3.15
4.8
3.3
5.0
3.45
5.25
V
Ivcc_in
Vcc input current
nReset = 0, Ivcc_switch = 0
Vcc = 3.3V
Vcc = 5.0V
2
5
mA
Figure 3. Pin Connections
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
PH_A+
R_SENSE_A
PH_A-
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DC2B
GND (DC2)
DC2A
GND (LOGIC)
nRESET
SDI
TEXT
VDD_GATE
VDD_SOURCE1
VDD_SOURCE2
VDD_DRAIN1
VDD_DRAIN2
Vs (VDD)
SCLK
nCS
ODD1
ODD2
10
11
12
13
14
ODD3
VDD_FB
ODD4
ODD5
PHB-
R_SENSE
PH_B
DC1A
GND (DC1)
DC1B
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D04IN1529
4/15
L8202
3 SERIAL INTERFACE
L8202 Analog ASIC integrates an SPI interface (write only) for data exchange with the Digital ASIC.
The Input word is 19 bits long.
3 Input Pins are dedicated to the Serial Interface: nCS (Chip Select, active Low), SDI (Serial Data In),
SCLK (Serial Clock). nCS must be pulled low to activate a Serial Input command.
Data present at the SDI pin are shifted into the L8202 on the 19 rising edges of SCLK.
The first bit present at the SDI, after the nCS is pulled low, and shifted into the L8202 at the first SCLK
rising edge is the LSB. ( SDI will remain at the value presented with the last bit of data ). The low to high
transition of nCS, after the 19th Sclk rising edge, loads the data into the internal L8202 ASIC input register.
The serial interface is cleared by nRESET.
Figure 4. SPI Operation
LSB
0
MSB
18
SDI
1
2
3
4
5
6
7
17
nCS
Tdelay sck_cs
Tdelay cs_sck
Table 5. SPI Timing specifications
(Tamb = 25 °C, VS = 32 V, unless otherwise specified)
Symbol
Fck
Parameter
Serial clock frequency
Min.
6
Typ.
Max.
Unit
MHz
ns
8
12
Tckhw
SCLK high width
30
30
10
10
10
10
10
0
Tcklw
SCLK low width
ns
Tdelay_cs-sck
Tdelay_sck-cs
Tdata_setup
Tdata_hold
Tdelay_cs
Tr_data
Delay nCS falling to first SCLK rising
Delay last SCLK rising edge to nCS rising
Data valid to SCLK set up time
Data hold time
ns
ns
ns
ns
Delay required from (n-1)CS to nCS
SDI rise time
ns
20
20
20
ns
Tf_data
SDI fall time
0
ns
Tr/f_sck
SCLK rise/fall time
0
ns
5/15
L8202
Table 6. SPI Bit Definition
RESET
VALUE
BIT #
Symbol
DESCRIPTION
0
STAND_BY
1
A Logic “1” inhibits OpAmps and Motors, and puts the L8202 into a lower power
state.
Chip must power up with Stand By Mode active.
VDD regulators operate independently from Stand By Mode.
1
2
3
4
VDD_EN
MDC1_D
MDC2_D
VSW_EN
0
0
0
1
A logic "1" enables the VDD regulator. Chip must power up with the VDD
regulators inactive.
Controls the direction of current flow through the DC motor windings. A high level
causes current to flow from DC1A(source) to DC1B(sink).
Controls the direction of current flow through the DC motor windings. A high level
causes current to flow from DC2A(source) to DC2B(sink).
A high level causes the 5V switch turn on. Chip must power up with the 5V switch
closed.
5
6
ODD 1
ODD 2
0
0
0
0
0
0
0
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
Controls Open Drain Driver. A high level causes Open Drain Driver Turn On.
7
ODD 3
8
ODD 4
9
ODD 5
10
11
ODD 6
SEL_MTR
Selection of motor type. A high level selects DC motor. A logic 0 level selects
Step motor.
12
I1_PH_B
1
This input and I0_PH_B select the output of three comparators to set the current
level. Current also depends on the sensing resistor and reference voltage.
13
14
I0_PH_B
D_PH_B
1
0
See I1_PH_B
This TTL-compatible logic input sets the direction of current flow through the
load. A high level causs current to flow from OUT A (source) to OUT B(sink). A
Schmitt triger on this input provides good noise immunity and a delay circuit
prevents output stage short circuits during switching.
15
I1_PH_A
1
This input and I0_PH_A select the output of three comparators to set the current
level. Current also depends on the sensing resistor and reference voltage.
16
17
18
I0_PH_A
D_PH_A
Test
1
0
0
See I1_PH_A
See D_PH_B
A high level forces the device to enter in Test Mode.
6/15
L8202
4 DC/DC CONVERTERS SPECIFICATION
L8202 contains 2 DC/DC converters.
VCC converter is programmable by the Vcc_Select pin for an Output Voltage rated at 3.3V or 5V (1.2A
max.). VDD voltage is programmable by a resistor divider network to voltages from +3V to +17V.
The switching frequency of the two converters is 200KHz.
The Vcc and the VDD regulators are protected by thermal protection circuit with thermal hysteresys (Out-
put Voltages are switched off during thermal protection event). The output voltages, Vcc and VDD are
short circuit protected.
4.1 VCC Regulator
Table 7. Electrical Characteristcs (Tj = 25 °C, VS = 32 V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC_o
Vcc Regulator Output Voltage.
Vcc value selected by Vcc_select Vcc = 5V From 10mA to 1.2A
pin.
Vcc = 3.3V From 10mA to 1.2A
3.23
4.90
3.3
5
3.37
5.20
V
V
I
Over current Threshold level
1.6
4.8
A
OC_detect
I
time Blankig time for overcurrent
detect
400
200
ns
OC_BK
I
Vcc external load current
Operating frequency
10
1200
225
mA
Vcc_load
f
ck
Tamb = 10 to 55°C
175
KHz
4.2 VDD Regulator
Table 8. Electrical Characteristcs (Tj = 25 °C, VS = 32 V, unless otherwise specified)
Symbol
Parameter
Test Conditions
24V≤ Vs ≤ 38V
Min.
Typ.
Max.
Unit
V
VDD Regulator Output Voltage
range
3
17
V
DD_O
Vref
Internal reference voltage for error
amp
-2%
1.24
+2%
3.0
V
IVDD_load
Vcc external load current
Over current detect level
0.01
2.0
A
A
I
During start up
3.2
5.5
250
OC_det_SU
IOC_det_SC Over current detect level
Current sense voltage
During short circuit
4.0
A
V
Using external Power DMOS,
this is a voltage of Ext. resistor
between Vs and VDD_source
-20%
+20%
Vs-10
mV
Sen_VDD
IOC_BK time Blankig time for overcurrent detect
300
ns
V
VGS_C
Gate to source clamp voltage
Transient time after which max load Vs high, ASIC receives
Vs-15
75
T
ms
Full_LOAD
can be applied to VDD regulator
command to turn on VDD Reg
IST_UP
fck
Maximum load current appliable
during start up.
1.2
A
Operating Frequency
Tamb = 10 to 55°C
175
200
225
KHz
7/15
L8202
5 DC MOTOR DRIVERS OPERATIONS
L8202 provides PWM bi-directional drive for two DC motors.
The PWM modulation is provided by the MDx_PWM input, and the current direction into the motor by the
MDCx_D bit in the serial input port.
The driver is protected versus overloads on the output lines to a max. current of 2 Amps peak.
The current protection circuit is implemented only on the High Side Drivers, so current protection is pro-
vided to motor currents only, but not to shorts between Motor Outputs to GND or Vs.
A blanking period following a current turn-on event is included to prevent false current protection.
The H Bridges are protected versus cross-conduction.
Thermal protection with hysteresys is provided to the Motor Drivers.
During thermal protection event the Bridge Outputs are forced into a high impedance status.
If nReset is low the motor drive outputs are forced in high impedance
Table 9. Absolute Maximum Ratings (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
IDC_O
Pulsed Output Current
DC Motor Overcurrent
Threshold
1.5
A
A
2
Table 10. Electrical Characteristcs (Tj = 25 °C, VS = 32 V, unless otherwise specified)
Symbol
Parameter
ON Resistance
Test Conditions
Min.
Typ.
0.31
0.32
Max.
Unit
RDS(ON)
I
= -0.75A (from output to
GND) or ILOAD = +0.75A (from
Vs to output) @Tamb =25°
W
LOAD
fPWM
PWM frequency
10
500
1
30
99
KHz
ns
Ton,Toff min. Minimum Ton and Toff time
DCPWM PWM Duty Cycle range
%
Table 11. Truth Table
Internal
Thermal Bit
Inputs
Outputs
MDCx_D
DCx_PWM
DCxA
DCxB
L
L
L
L
H
L
H
L
H
H
H
L
H
H
X
H
H
H
X
H
All transistors turned off All transistors turned off
8/15
L8202
6 STEPPER MOTOR DRIVER OPERATIONS
Two H Bridges are provided to implement current control through the two widings of a Bipolar Stepper Mo-
tor.
The phase and current level information are programmed over the serial input port (see Serial Interface
Bits definition section).
Four current levels (0%,33%,66%,100%) are programmable through the status of IN0 and IN1 bits in the
Input Serial Port.
This drive enters the fast current decay mode when both the I0_PH_X and I1_PH_X inputs set to the high
logic level (current is recirculated from GND to Vs supply).
A blanking period following a current turn-on event is included to prevent false current protection.
The H Bridges are protected versus cross-conduction.
Thermal protection with hysteresys is provided to the Motor Drivers.
During thermal protection event the Bridge Outputs are forced into a high impedance status.
Table 12. Absolute Maximum Ratings (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
ISTEP_O
Pulsed Output Current
1.5
A
Table 13. Electrical Characteristcs (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
ON Resistance
Test Conditions
Min.
Typ.
Max.
Unit
R
I
= -0.6 A (from output to
0.55
W
DS(ON)
LOAD
GND) or I
Vs to output) @Tamb = 25°C
= +0.6 A (from
LOAD
0.4
V
V
Comparator High Threshold
Voltage
I0_PH_x = 0
I1_PH_x = 0
500
mV
mV
mV
mA
Comp_HT
Comparator Medium Threshold I0_PH_x = 1
Voltage
333
167
0.5
Comp_MT
I1_PH_x = 0
V
Comparator Low Threshold
Voltage
I0_PH_x = 0
I1_PH_x = 1
Comp_LT
ILEAK_VOFF VoOFF Output Leakage
Current for Stepper Motor
Driver Outputs
VoOFF = 5V
I0_PH_x = 1
I1_PH_x = 1
Toff
Tj
Off time
20
30
20
40
µs
°C
°C
Thermal shutdown
140
Tj(enable_
hysterisys)
Stepper Motor driver thermal
enable junction temperature
hysterisys
Table 14. Truth Table
I
I0_PH_x
I1_PH_x
STEP_O_PH_x
L
H
L
L
L
100%
66 %
H
H
33 %
H
0 %
Notes: 1. The 100% current is fixed by the sense resistor, and the Maximum Threshold of the Voltage Comparator
9/15
L8202
7 OPERATIONAL AMPLIFLIERS
L8202 contains four general purpose Op-Amps,with their own Supply rail and Gnd rail. OpAmps are inhib-
ited when L8202 is in sleep mode
Table 15. Absolute Maximum Ratings (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Vcc
Parameter
Supply Voltage
Test Conditions
Min.
Typ.
Max.
5.2
Unit
V
3.2
Vid
Differential Input Voltage
5.2
V
Table 16. Electrical Characteristcs (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Vio
Parameter
Input Offset Voltage
Test Conditions
Vinp = Vcc-1.5
Min.
Typ.
Max.
Unit
mV
-9
9
Avd
Large Signal Voltage Gain
130
V/mV
V
Vicm
Input Common Mode Voltage
Range
Full range
DC
0
Vcc-
1.5
CMR
Common Mode Rejection
Ratio
70
10
10
dB
Isource
Output Current Source
Vcc = 5/3.3V
Vo = Vcc-2V
20
20
mA
Isink
Output Sink Current
Vcc = 5/3.3V, Vo = 2V
mA
V
VOH
High Level Output Voltage
Sourcing 2mA, Vcc = 5.2V,
full range
Vcc-
0.5
VOL
SR
Low Level Output Voltage
Slew Rate
Sinking 2mA, Vcc=5.2V, full
range
0.5
V
Full Range
Cload = 100pF
0.3
V/µs
GBP
Gain Bandwidth Product
* Guaranted by design
8 OPEN DRAIN DRIVERS
L8202 contains 6 open Drain Drivers. These drivers are controlled by the Serial Interface by the bit ODD1/
6, each driver is able to sink 30mA from either 3.3V or 5v Supply.
Table 17. Electrical Characteristics (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
1
Unit
µA
I
High State Output Current
Low State Output Voltage
ODDx = 0, Vcc = 5.0V or 3.3V
ODD_H
V
ODDx = 1, Vcc = 5.0V or 3.3V,
Iload = 30mA
300
mV
ODD_L
10/15
L8202
9 VOLTAGE SUPERVISOR
nRESET is an Output/Input signal (active low), that is used both to provide the information about the status
of Vcc and Vs supplies, both to provide a Reset signal to the internal logic when driven "low" from an ex-
ternal source for a period > 30µs.
When nRESET is asserted, Motor Drivers and VDD regulator are forced in the inactive state and the Serial
Input Port is loaded with the "Reset Value".
To avoid false assertion due to glitches, nRESET is released to the "high" state with a delay of 100ms.
Delay period is calculated from the moment Vcc is passing the Vcc threshold.
At power down no delay is present, and nRESET is asserted low by Vcc or Vs falling low respect to their
thresholds
Figure 5.
Vs
A
V
TH_VCC
Vcc
nRESET
Td
Tdeglitch
Td
Note A. L8202 ignores very brief transients.
This should be less than Tdeglitch
Table 18. Electrical Characteristics (Tj = 25°C, VS = 32V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Ioh = -0.1 mA
Min.
Typ.
Max.
Unit
Vout_high
High-level output voltage at
nRESET
Vcc-
0.5V
V
Vout_low
Rp_up
Low-level output voltage at
nRESET
0.2
5
V
Vcc< VTH_VCC
Vs=38V
Internal pull-up resistance
between Vcc_in and nRESET
2
3
KΩ
V
Threshold voltage at Vcc &
Vcc_in
Vcc = 3.3V
Vcc_in = 3.3V
2.87
2.82
3.07
3.10
V
TH_VCC
Vcc = 5.0V
Vcc_in = 3.3V
4.35
2.87
4.65
3.10
VTH_Vs-
VTH_Vs+
Low threshold voltage at Vs
High threshold voltage at Vs
Hysteresis Voltage
Vcc > VTH_VCC
Vs decreasing
18.0
20.0
V
V
V
Vcc > VTH_VCC
Vs increasing
19.25
21.25
V
( VTH_Vs+ ) -( VTH_Vs-
)
1.2
HYST_Vs
Table 19. Switching Characteristics (Tj = 25 °C, VS = 32V, unless otherwise specified)
Symbol
Td
Parameter
nRESET delay
Test Conditions
Min.
70
Typ.
100
20
Max.
130
30
Unit
ms
µs
Vcc >= V
TH_VCC
Tdeglitch
Vcc out of tolerance
persistence time
nRESET deasserted
10
Vcc < V
TH_VCC
Trise
Tfall
Rise Time at nRESET
Fall Time at nRESET
10 to 90%, 50pF Load
90 to 10%, 50pF Load
750
50
ns
ns
11/15
L8202
10 APPLICATION CIRCUIT
Figure 6.
V_bulk
+
U1
L8202
C1
C2
Vcc
63
OpAmp_Supply
62
61
60
59
58
57
56
55
54
53
52
51
50
32
25
35
33
34
V_bulk
PWM1
OA1Out
OA1+
V_bulk(DC1)
DC1_PWM
DC1A
DC motor
DC motor
DC MTR #1 H
Drive
OA1-
OA2Out
OA2+
OA2-
OA3Out
OA3+
DC1B
L1
GND(DC1)
OP.
Amps
VPH
R1
C3
49
26
46
48
47
V_bulk
PWM2
V_bulk(DC2)
DC2_PWM
DC2A
DC2B
GND(DC2)
150uH 3A rms
OA3-
DC MTR #2 H
Drive
OA4Out
OA4+
OA4-
OpAmp_GND
V_bulk
64
24
1
V_bulk(DC3)
DC3_PWM
PH_A+
C4
2200uF
+
C5
D1
V_bulk
V_bulk
11
7
Phase A H
Drive
V_bulk(VPH)
VPH_source1
VPH_source2
VPH_gate
VPH_drain1
VPH_drain2
VPH_FB
R2
3
PH_A-
8
2
R_Sense_A
6
9
10
12
VPH regulator
3A DC Load
Stepper motor
V_bulk
17
23
16
14
15
V_bulk(DC4)
DC4_PWM
PH_B+
PH_B-
R_sense_B
Phase B H
Drive
18
19
21
22
Vbulk(Vcc)
Vcc_drain
Vcc_select
Vcc_FB
Vcc regulator
3.3V or 5V
Vcc
40
39
38
37
36
20
LED1
LED2
LED3
LED4
LED5
LED6
R3
0.62 ohm
R4
0.62 ohm
L4
Vcc
SCLK
42
43
41
SCLK
SDATA
nCS
SDATA
SERIAL
INTERFACE
LED
Drivers
220uH 1.2A rms, 4.8A sat
nCS
C6
1000uF
+
C7
Reset
D2
SCLK
SDATA
nCS
1
2
3
4
5
From microcontroller
PWM1
R5
1K
PWM2
C8
100nF
Figure 7.
V_bulk
+
U1
63
L8202
C1
C2
Vcc
OpAmp_Supply
62
61
60
59
58
57
56
55
54
53
52
51
50
32
V_bulk
PWM1
DC motor
OA1Out
OA1+
V_bulk(DC1)
DC1_PWM
DC1A
25
35
33
34
DC MTR #1 H
Drive
OA1-
OA2Out
OA2+
DC1B
GND(DC1)
L1
R1
OP.
OA2-
VPH
R2
C3
Amps
OA3Out
OA3+
49
26
46
48
47
V_bulk
PWM2
V_bulk(DC2)
DC2_PWM
DC2A
DC2B
GND(DC2)
OA3-
DC MTR #2 H
Drive
DC motor
DC motor
DC motor
OA4Out
OA4+
OA4-
OpAmp_GND
64
24
1
3
2
V_bulk
PWM3
V_bulk(DC3)
DC3_PWM
PH_A+
PH_A-
R_Sense_A
+
C5
C4
D1
V_bulk
11
7
Phase A H
Drive
V_bulk(VPH)
VPH_source1
VPH_source2
VPH_gate
VPH_drain1
VPH_drain2
VPH_FB
R3
8
6
VPH regulator
3A DC Load
9
10
12
17
23
16
14
15
V_bulk
PWM4
V_bulk(DC4)
DC4_PWM
PH_B+
PH_B-
R_sense_B
Phase B H
Drive
V_bulk
SCLK
18
19
21
Vbulk(Vcc)
Vcc_drain
Vcc_select
Vcc_FB
Vcc regulator
3.3V or 5V
Vcc 22
40
39
38
37
36
20
LED1
LED2
LED3
LED4
LED5
LED6
L2
Vcc
42
43
41
SCLK
SDATA
nCS
SDATA
nCS
SERIAL
INTERFACE
LED
Drivers
220uH 1.2A rms, 4.8A sat
C6
+
C7
1000uF
D2
Reset
SCLK
SDATA
nCS
PWM1
PWM2
PWM3
PWM4
1
2
3
4
5
6
7
From microcontroller
R4
1K
C8
100nF
12/15
L8202
Figure 8. TQFP64 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.
TYP. MAX. MIN.
1.20
TYP. MAX.
0.0472
A
A1
A2
b
0.05
0.95
0.17
0.09
0.15 0.002
0.006
1.00
0.22
1.05 0.0374 0.0393 0.0413
0.27 0.0066 0.0086 0.0086
c
0.20 0.0035
0.0078
D
11.80 12.00 12.20 0.464 0.472 0.480
9.80 10.00 10.20 0.386 0.394 0.401
D1
D2
D3
E
2.00
0.787
7.50
0.295
11.80 12.00 12.20 0.464 0.472 0.480
9.80 10.00 10.20 0.386 0.394 0.401
E1
E2
E3
e
2.00
0.787
7.50
0.50
0.60
1.00
3.5˚
0.295
0.0197
L
0.45
0˚
0.75 0.0177 0.0236 0.0295
0.0393
L1
k
TQFP64 (10x10x1.0mm)
Exposed Pad Down
7˚
0˚
3.5˚
7˚
ccc
0.080
0.0031
7278840 B
13/15
L8202
Table 20. Revision History
Date
Revision
Description of Changes
January 2005
February 2005
1
2
First Issue
Changed the maturity from Preliminary Data to Final Datasheet.
14/15
L8202
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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15/15
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